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1. 发明授权

US07640315B1 Implementing locks in a distributed processing system 有权
标题翻译：在分布式处理系统中实现锁定
公开(公告)号：US07640315B1
公开(公告)日：2009-12-29
申请号：US09633087
申请日：2000-08-04
申请人： Derrick R. Meyer , Jonathan M. Owen , Mark D. Hummel , James B. Keller
发明人： Derrick R. Meyer , Jonathan M. Owen , Mark D. Hummel , James B. Keller
IPC分类号： G06F15/16
CPC分类号： G06F9/52
摘要： A messaging scheme to synchronize processes within a distributed memory multiprocessing computer system having two or more processing nodes interconnected using an interconnect structure of dual-unidirectional links. Each unidirectional link forms a point-to-point interconnect to transfer packetized information between two processing nodes. A lock acquisition request from a lock requesting node is placed into service by an arbitrating node when no previous lock requests are pending for service. The arbitrating node transmits a broadcast message to all nodes in the system, which, in turn, respond with a corresponding probe response message to inform the arbitrating node of cessation of issuance of new requests by the node sending the probe response message. The arbitrating node informs the lock requesting node of the requesting node's lock ownership by transmitting a target done message thereto. After completion of lock operations, the lock requesting node sends a lock release request to the arbitrating node, which, in turn, informs all processing nodes of lock release by transmitting another broadcast message within the system. The messaging protocol is completed when each node sends another probe response to the arbitrating node, which, in turn, sends a final target done message to the lock requesting node. Lock operations are performed without contention for system resources and without deadlocks among various processing nodes.
摘要翻译：用于使具有使用双向单向链路的互连结构互连的两个或多个处理节点的分布式存储器多处理计算机系统内的进程同步的消息传递方案。每个单向链路形成点对点互连以在两个处理节点之间传送分组信息。当没有先前的锁定请求正在等待服务时，来自锁定请求节点的锁定获取请求被仲裁节点投入使用。仲裁节点向系统中的所有节点发送广播消息，后者又响应相应的探测响应消息，通知仲裁节点发送探测响应消息的节点发出新请求。仲裁节点通过向其发送目标完成消息来向锁请求节点通知请求节点的锁拥有权。锁定操作完成后，锁定请求节点向仲裁节点发送锁定释放请求，仲裁节点又通过在系统内传送另一个广播消息来通知所有处理节点的锁定释放。当每个节点向仲裁节点发送另一个探测响应时，完成消息协议，该仲裁节点又向锁定请求节点发送最终的目标完成消息。执行锁定操作而不对系统资源产生争用，并且在各种处理节点之间没有死锁。

2. 发明授权

US06745272B2 System and method of increasing bandwidth for issuing ordered transactions into a distributed communication system 有权
标题翻译：增加带宽的系统和方法，用于将有序交易发布到分布式通信系统中
公开(公告)号：US06745272B2
公开(公告)日：2004-06-01
申请号：US09826262
申请日：2001-04-04
申请人： Jonathan M. Owen , Mark D. Hummel , Derrick R. Meyer , James B. Keller
发明人： Jonathan M. Owen , Mark D. Hummel , Derrick R. Meyer , James B. Keller
IPC分类号： G06F1300
CPC分类号： H04L1/1671
摘要： A method and system of expediting issuance of a second request of a pair of ordered requests into a distributed coherent communication fabric. The first request of the ordered pair is issued into the coherent communication fabric and directed to a first target. Issuance of the second request into the coherent communication fabric is stalled until the first target receives and orders the first request and transmits a response acknowledging the same.
摘要翻译：一种将一对有序请求的第二请求发布到分布式相干通信结构中的方法和系统。有序对的第一个请求被发布到相干通信结构中，并被引导到第一个目标。将第二个请求发送到相干通信结构中停止，直到第一个目标接收并订购第一个请求并发送确认该响应的响应。

3. 发明授权

US07069361B2 System and method of maintaining coherency in a distributed communication system 有权
公开(公告)号：US07069361B2
公开(公告)日：2006-06-27
申请号：US09840449
申请日：2001-04-23
申请人： Jonathan M. Owen , Mark D. Hummel , Derrick R. Meyer , James B. Keller
发明人： Jonathan M. Owen , Mark D. Hummel , Derrick R. Meyer , James B. Keller
IPC分类号： G06F13/00
CPC分类号： H04L1/1671
摘要： A method and system of expediting issuance of a second request of a pair of ordered requests into a distributed coherent communication fabric. The first request of the ordered pair is issued into the coherent communication fabric and directed to a first target. Issuance of the second request into the coherent communication fabric is stalled until the first target receives and orders the first request and transmits a response acknowledging the same.

4. 发明授权

US06760838B2 System and method of initializing and determining a bootstrap processor [BSP] in a fabric of a distributed multiprocessor computing system 有权
标题翻译：在分布式多处理器计算系统的结构中初始化和确定引导处理器[BSP]的系统和方法
公开(公告)号：US06760838B2
公开(公告)日：2004-07-06
申请号：US09773763
申请日：2001-01-31
申请人： Jonathan M. Owen , Mark D. Hummel , Derrick R. Meyer
发明人： Jonathan M. Owen , Mark D. Hummel , Derrick R. Meyer
IPC分类号： G06F15177
CPC分类号： G06F15/177
摘要： A method for initializing a computing system comprising a plurality of devices which communicate on a communication link comprising a plurality of independent point-to-point links is provided, each of the point-to-point links interconnecting a respective pair of the plurality of devices. The method includes a link initialization procedure comprising initially configuring each respective pair of devices to communicate on the respective interconnecting link using common communication parameters, including a common frequency and a common link width. The link initialization procedure also may include an optimization procedure for determining maximum communication parameters for each interconnected pair of devices. If the maximum compatible parameters differ from the common parameters for any pair of devices, then the pair of devices may be reconfigured to communicate on the interconnecting link using the maximum compatible parameters. Once a communication capability has been established, the establishment of one or more communication fabrics for the computer system may be performed. This scheme includes designating a bootstrap processor, locating the boot ROM, establishing the manner in which the devices are interconnected, and defining routing directions for routing communications among the various devices in the computing system.
摘要翻译：提供了一种用于初始化包括在包括多个独立点对点链路的通信链路上通信的多个设备的计算系统的方法，每个点对点链路互连所述多个设备中的相应对。该方法包括链路初始化过程，其包括首先使用包括公共频率和公共链路宽度的公共通信参数在每个互连链路上配置每个相应设备对进行通信。链路初始化过程还可以包括用于确定每个互连的设备对的最大通信参数的优化过程。如果最大兼容参数与任何设备对的公共参数不同，则可以使用最大兼容参数将该对设备重新配置为在互连链路上进行通信。一旦建立了通信能力，就可以执行用于计算机系统的一个或多个通信结构的建立。该方案包括指定引导处理器，定位引导ROM，建立设备互连的方式，以及定义用于在计算系统中的各种设备之间路由通信的路由选择方向。

5. 发明授权

US06665742B2 SYSTEM FOR RECONFIGURING A FIRST DEVICE AND/OR A SECOND DEVICE TO USE A MAXIMUM COMPATIBLE COMMUNICATION PARAMETERS BASED ON TRANSMITTING A COMMUNICATION TO THE FIRST AND SECOND DEVICES OF A POINT-TO-POINT LINK 有权
标题翻译：用于重新配置第一设备和/或第二设备的系统，以便基于向点到点链路的第一和第二设备发送通信来使用最大的兼容通信参数
公开(公告)号：US06665742B2
公开(公告)日：2003-12-16
申请号：US09773777
申请日：2001-01-31
申请人： Jonathan M. Owen , Mark D. Hummel , Derrick R. Meyer
发明人： Jonathan M. Owen , Mark D. Hummel , Derrick R. Meyer
IPC分类号： G06F1310
CPC分类号： H04L29/06 , H04L69/24
摘要： A method for initializing a computing system comprising a plurality of devices which communicate on a communication link comprising a plurality of independent point-to-point links is provided, each of the point-to-point links interconnecting a respective pair of the plurality of devices. The method includes a link initialization procedure comprising initially configuring each respective pair of devices to communicate on the respective interconnecting link using common communication parameters, including a common frequency and a common link width. The link initialization procedure also may include an optimization procedure for determining maximum communication parameters for each interconnected pair of devices. If the maximum compatible parameters differ from the common parameters for any pair of devices, then the pair of devices may be reconfigured to communicate on the interconnecting link using the maximum compatible parameters. Once a communication capability has been established, the establishment of one or more communication fabrics for the computer system may be performed.
摘要翻译：提供了一种用于初始化包括在包括多个独立点对点链路的通信链路上通信的多个设备的计算系统的方法，每个点对点链路互连所述多个设备中的相应对。该方法包括链路初始化过程，其包括首先使用包括公共频率和公共链路宽度的公共通信参数在每个互连链路上配置每个相应设备对进行通信。链路初始化过程还可以包括用于确定每个互连的设备对的最大通信参数的优化过程。如果最大兼容参数与任何设备对的公共参数不同，则可以使用最大兼容参数将该对设备重新配置为在互连链路上进行通信。一旦建立了通信能力，就可以执行用于计算机系统的一个或多个通信结构的建立。

6. 发明授权

US06360314B1 Data cache having store queue bypass for out-of-order instruction execution and method for same 失效
标题翻译：具有存储队列旁路的数据高速缓存用于无序指令执行及其方法
公开(公告)号：US06360314B1
公开(公告)日：2002-03-19
申请号：US09115186
申请日：1998-07-14
申请人： David Arthur James Webb, Jr. , James B. Keller , Derrick R. Meyer
发明人： David Arthur James Webb, Jr. , James B. Keller , Derrick R. Meyer
IPC分类号： G06F938
CPC分类号： G06F9/3834 , G06F9/3826
摘要： A bypass mechanism is disclosed for a computer system that executes load and store instructions out of order. The bypass mechanism compares the address of each issuing load instruction with a set of recent store instructions that have not yet updated memory. A match of the recent stores provides the load data instead of having to retrieve the data from memory. A store queue holds the recently issued stores. Each store queue entry and the issuing load includes a data size indicator. Subsequent to a data bypass, the data size indicator of the issuing load is compared against the data size indicator of the matching store queue entry. A trap is signaled when the data size indicator of the issuing load differs from the data size indicator of the matching store queue entry. The trap signal indicates that the data provided by the bypass mechanism was insufficient to satisfy the requirements of the load instruction. The bypass mechanism also operates in cases in which multiple prior stores to the same address are pending when a load that needs to read that address issues.
摘要翻译：公开了一种用于执行装载和存储指令的计算机系统的旁路机构。旁路机制将每个发布加载指令的地址与尚未更新内存的一组最近的存储指令进行比较。最近的商店的匹配提供了加载数据，而不是从内存中检索数据。商店队列持有最近发布的商店。每个存储队列条目和发布加载包括数据大小指示符。在数据旁路之后，将发布负载的数据大小指示符与匹配存储队列条目的数据大小指示符进行比较。当发布负载的数据大小指示符与匹配的存储队列条目的数据大小指示符不同时，用信号通知陷阱。陷阱信号表示旁路机构提供的数据不足以满足加载指令的要求。在需要读取该地址的负载发生问题的情况下，旁路机制还可以在多个先前存储到同一地址的情况下进行操作。

7. 发明授权

US06888843B2 Response virtual channel for handling all responses 失效
标题翻译：响应虚拟通道来处理所有响应
公开(公告)号：US06888843B2
公开(公告)日：2005-05-03
申请号：US09398624
申请日：1999-09-17
申请人： James B. Keller , Derrick R. Meyer
发明人： James B. Keller , Derrick R. Meyer
IPC分类号： G06F13/40 , H04L12/54
CPC分类号： G06F13/405
摘要： A computer system employs virtual channels and allocates different resources to the virtual channels. Packets which do not have logical/protocol-related conflicts are grouped into a virtual channel. Accordingly, logical conflicts occur between packets in separate virtual channels. The packets within a virtual channel may share resources (and hence experience resource conflicts), but the packets within different virtual channels may not share resources. Since packets which may experience resource conflicts do not experience logical conflicts, and since packets which may experience logical conflicts do not experience resource conflicts, deadlock-free operation may be achieved. Additionally, nodes within the computer system may be configured to preallocate resources to process response packets. Some response packets may have logical conflicts with other response packets, and hence would normally not be allocable to the same virtual channel. However, by preallocating response-processing resources, response packets are accepted by the destination node. Thus, any resource conflicts which may occur are temporary (as the response packets which make forward progress are processable). Viewed in another way, response packets may be logically independent if the destination node is capable of processing the response packets upon receipt. Accordingly, a response virtual channel is formed to which each response packet belongs.
摘要翻译：计算机系统采用虚拟通道并为虚拟通道分配不同的资源。没有逻辑/协议相关冲突的数据包被分组成虚拟通道。因此，在分离的虚拟通道中的分组之间发生逻辑冲突。虚拟通道内的数据包可能共享资源（从而遇到资源冲突），但不同虚拟通道内的数据包可能不共享资源。由于可能遇到资源冲突的数据包不会出现逻辑冲突，并且由于可能遇到逻辑冲突的数据包不会遇到资源冲突，因此可能会实现无死锁操作。此外，计算机系统内的节点可以被配置为预先分配资源以处理响应分组。一些响应分组可能与其他响应分组具有逻辑冲突，因此通常不能分配给相同的虚拟信道。然而，通过预分配响应处理资源，响应分组被目的节点接受。因此，可能发生的任何资源冲突都是临时的（因为可以进行进展的响应数据包是可处理的）。以另一种方式观察，如果目的地节点在接收时能够处理响应分组，则响应分组可以在逻辑上是独立的。因此，形成每个响应分组所属的响应虚拟信道。

8. 发明授权

US06374344B1 Methods and apparatus for processing load instructions in the presence of RAM array and data bus conflicts 有权
标题翻译：在存在RAM阵列和数据总线冲突的情况下处理加载指令的方法和装置
公开(公告)号：US06374344B1
公开(公告)日：2002-04-16
申请号：US09200248
申请日：1998-11-25
申请人： David Arthur James Webb, Jr. , James B. Keller , Derrick R. Meyer
发明人： David Arthur James Webb, Jr. , James B. Keller , Derrick R. Meyer
IPC分类号： G06F1208
CPC分类号： G06F12/0859
摘要： A technique handles load instructions within a data processor that includes a cache circuit having a data cache and a tag memory indicating valid entries within the data cache. The technique involves writing data to the data cache during a series of four processor cycles in response to a first load instruction. Additionally, the technique involves updating the tag memory and preventing reading of the tag memory in response to the first load instruction during a first processor cycle in the series of processor cycles. Furthermore, the technique involves reading tag information from the tag memory during a processor cycle of the series of four processor cycles following the first processor cycle in response to a second load instruction.
摘要翻译：一种技术处理数据处理器内的加载指令，该数据处理器包括具有数据高速缓存的高速缓冲存储器和指示数据高速缓存内的有效条目的标签存储器。该技术涉及在响应于第一加载指令的四个处理器周期的一系列期间将数据写入数据高速缓存。此外，该技术涉及在一系列处理器周期中的第一处理器周期期间响应于第一加载指令更新标签存储器并防止标签存储器的读取。此外，该技术涉及在响应于第二加载指令的第一处理器周期之后的四个处理器周期的系列的处理器周期期间从标签存储器读取标签信息。

9. 发明授权

US06557048B1 Computer system implementing a system and method for ordering input/output (IO) memory operations within a coherent portion thereof 有权
标题翻译：实现用于在其相干部分内对输入/输出（IO）存储器操作进行排序的系统和方法的计算机系统
公开(公告)号：US06557048B1
公开(公告)日：2003-04-29
申请号：US09431364
申请日：1999-11-01
申请人： James B. Keller , Derrick R. Meyer , Dale E. Gulick , Larry D. Hewitt
发明人： James B. Keller , Derrick R. Meyer , Dale E. Gulick , Larry D. Hewitt
IPC分类号： G06F1300
CPC分类号： G06F13/4059
摘要： A computer system is presented which implements a system and method for ordering input/output (I/O) memory operations. In one embodiment, the computer system includes a processing subsystem and an I/O subsystem. The processing subsystem includes multiple processing nodes interconnected via coherent communication links. Each processing node may include a processor executing software instructions. The I/O subsystem includes one or more I/O nodes serially coupled via non-coherent communication links. Each I/O node may embody one or more I/O functions (e.g., modem, sound card, etc.). One of the processing nodes includes a host bridge which translates packets moving between the processing subsystem and the I/O subsystem. One of the I/O nodes is coupled to the processing node including the host bridges. The I/O node coupled to the processing node produces and/or provides transactions having destinations or targets within the processing subsystem to the processing node including the host bridge. The I/O node may, for example, produce and/or provide a first transaction followed by a second transaction. The host bridge may dispatch the second transaction with respect to the first transaction according to a predetermined set of ordering rules. For example, the host bridge may: (i) receive the first and second transactions, (ii) dispatch the first transaction within the processing subsystem, and (iii) dispatch the second transaction within the processing subsystem dependent upon progress of the first transaction within the processing subsystem and the predetermined set of ordering rules.
摘要翻译：提出了一种实现用于排序输入/输出（I / O）存储器操作的系统和方法的计算机系统。在一个实施例中，计算机系统包括处理子系统和I / O子系统。处理子系统包括通过相干通信链路互连的多个处理节点。每个处理节点可以包括执行软件指令的处理器。 I / O子系统包括通过非相干通信链路串联耦合的一个或多个I / O节点。每个I / O节点可以体现一个或多个I / O功能（例如，调制解调器，声卡等）。其中一个处理节点包括一个主机桥，它转换在处理子系统和I / O子系统之间移动的数据包。其中一个I / O节点耦合到包括主机桥的处理节点。耦合到处理节点的I / O节点产生和/或提供具有处理子系统内包含主机桥的处理节点的目的地或目标的事务。 I / O节点可以例如产生和/或提供第一事务，随后是第二事务。主桥可以根据预定的一组排序规则来分派关于第一事务的第二事务。例如，主桥可以：（i）接收第一和第二事务，（ii）在处理子系统内调度第一事务，以及（iii）根据第一事务的进度在处理子系统内调度第二事务处理子系统和预定的一套排序规则。

10. 发明授权

US06938094B1 Virtual channels and corresponding buffer allocations for deadlock-free computer system operation 有权
标题翻译：虚拟通道和相应的缓冲区分配，用于无死锁的计算机系统操作
公开(公告)号：US06938094B1
公开(公告)日：2005-08-30
申请号：US09399281
申请日：1999-09-17
申请人： James B. Keller , Derrick R. Meyer
发明人： James B. Keller , Derrick R. Meyer
IPC分类号： G06F12/08 , G06F13/38 , G06F15/173 , G06F15/177 , H04L12/28
CPC分类号： G06F15/17381
摘要： A computer system employs virtual channels and allocates different resources to the virtual channels. Packets which do not have logical/protocol-related conflicts are grouped into a virtual channel. Accordingly, logical conflicts occur between packets in separate virtual channels. The packets within a virtual channel may share resources (and hence experience resource conflicts), but the packets within different virtual channels may not share resources. Since packets which may experience resource conflicts do not experience logical conflicts, and since packets which may experience logical conflicts do not experience resource conflicts, deadlock-free operation may be achieved. Additionally, each virtual channel may be assigned control packet buffers and data packet buffers. Control packets may be substantially smaller in size, and may occur more frequently than data packets. By providing separate buffers, buffer space may be used efficiently. If a control packet which does not specify a data packet is received, no data packet buffer space is allocated. If a control packet which does specify a data packet is received, both control packet buffer space and data packet buffer space is allocated.
摘要翻译：计算机系统采用虚拟通道并为虚拟通道分配不同的资源。没有逻辑/协议相关冲突的数据包被分组成虚拟通道。因此，在分离的虚拟通道中的分组之间发生逻辑冲突。虚拟通道内的数据包可能共享资源（从而遇到资源冲突），但不同虚拟通道内的数据包可能不共享资源。由于可能遇到资源冲突的数据包不会发生逻辑冲突，并且由于可能遇到逻辑冲突的数据包不会遇到资源冲突，因此可能会实现无死锁操作。另外，每个虚拟信道可以被分配控制分组缓冲器和数据分组缓冲器。控制分组的大小可能会更小，并且可能比数据分组更频繁地发生。通过提供单独的缓冲区，可以有效地使用缓冲区空间。如果接收到不指定数据分组的控制分组，则不分配数据分组缓冲空间。如果接收到指定数据分组的控制分组，则分配控制分组缓冲区空间和数据分组缓冲区空间。

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