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61. 发明申请

US20080137414A1 Multi-level cell memory device and method thereof 有权
标题翻译：多级单元存储装置及其方法
公开(公告)号：US20080137414A1
公开(公告)日：2008-06-12
申请号：US11808173
申请日：2007-06-07
申请人： Sung Chung Park , Jun Jin Kong , Young Hwan Lee , Dong Ku Kang
发明人： Sung Chung Park , Jun Jin Kong , Young Hwan Lee , Dong Ku Kang
IPC分类号： G11C7/10
CPC分类号： G11C11/5621 , G11C7/1006 , G11C29/00
摘要： A Multi-Level Cell (MLC) memory device and method thereof are provided. The example MLC memory device may be configured to perform data operations, and may include an MLC memory cell, a first coding device performing a first coding function, the first coding function being one of an encoding function and a decoding function, a second coding device performing a second coding function, the second coding function being one of an encoding function and a decoding function and a signal module configured to perform at least one of instructing the MLC memory cell to store data output by the second coding device if the first and second coding functions are encoding functions, and generating a demapped bit stream based on data retrieved from the MLC memory cell if the first and second coding functions are decoding functions.
摘要翻译：提供了一种多级单元（MLC）存储器件及其方法。示例MLC存储器件可以被配置为执行数据操作，并且可以包括MLC存储器单元，执行第一编码功能的第一编码装置，作为编码功能和解码功能之一的第一编码功能，第二编码装置执行第二编码功能，所述第二编码功能是编码功能和解码功能之一;以及信号模块，被配置为执行指令所述MLC存储器单元存储由所述第二编码装置输出的数据中的至少一个，如果所述第一和第二编码功能编码功能是编码功能，并且如果第一和第二编码功能是解码功能，则基于从MLC存储器单元检索的数据来生成解映射比特流。

62. 发明授权

US08654580B2 Non-volatile memory devices and systems including the same, and methods of programming non-volatile memory devices 有权
标题翻译：包括其的非易失性存储器件和系统以及编程非易失性存储器件的方法
公开(公告)号：US08654580B2
公开(公告)日：2014-02-18
申请号：US13316636
申请日：2011-12-12
申请人： Dong Ku Kang , Seung-Bum Kim , Tae-Young Kim , Sun-Jun Park
发明人： Dong Ku Kang , Seung-Bum Kim , Tae-Young Kim , Sun-Jun Park
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/16
摘要： A method is for programming a memory block of a non-volatile memory device. The non-volatile memory device is operatively connected to a memory controller, and the memory block defined by a plurality of word lines located between a string select line and a common source line corresponding to the string select line. The method includes programming a first sub-block of the memory block, determining in the non-volatile memory device when a reference word line is programmed during programming of the first sub-block, and partial erasing a second sub-block of the memory block upon determining that the reference word line is programmed during programming of the first sub-block.
摘要翻译：一种用于编程非易失性存储器件的存储器块的方法。非易失性存储器件可操作地连接到存储器控制器，并且由位于串选择线和对应于字符串选择行的公共源线之间的多个字线定义的存储器块。该方法包括对存储块的第一子块进行编程，在第一子块的编程期间对参考字线进行编程以及部分擦除存储块的第二子块时，确定非易失性存储器件一旦确定在第一子块的编程期间编程了参考字线。

63. 发明授权

US08499215B2 Multi-level cell memory devices and methods of storing data in and reading data from the memory devices 有权
标题翻译：多级单元存储器件以及将数据存储在存储器件中并从其读取数据的方法
公开(公告)号：US08499215B2
公开(公告)日：2013-07-30
申请号：US11802656
申请日：2007-05-24
申请人： Jun Jin Kong , Sung Chung Park , Dong Ku Kang , Young Hwan Lee , Si Hoon Hong , Jae Woong Hyun
发明人： Jun Jin Kong , Sung Chung Park , Dong Ku Kang , Young Hwan Lee , Si Hoon Hong , Jae Woong Hyun
IPC分类号： H03M13/29 , G11C29/00
CPC分类号： G11C16/10 , G11C7/1006 , G11C11/5628 , G11C11/5642 , G11C16/0483
摘要： A multi-level cell (MLC) memory device may include ‘a’ number of m-bit MLC memory cells; an encoder that encodes ‘k’ bits of data at a code rate of k/n to generate an encoded bit stream; and a signal mapping module that applies pulses to the MLC memory cells in order to write the encoded bit stream in the MLC memory cells. In the device, ‘a’ and ‘m’ may be integers greater than or equal to 2, ‘k’ and ‘n’ may be integers greater than or equal to 1, and ‘n’ may be greater than ‘k’. A method of storing data in the device may include encoding ‘k’ bits of data at a code rate of k/n to generate an encoded bit stream. A method of reading data from the device may include decoding ‘n’ bits of data at a code rate of n/k to generate a decoded bit stream.
摘要翻译：多级单元（MLC）存储器件可以包括“a”个m位MLC存储器单元; 编码器，其以k / n的码率对“k”位数据进行编码，以产生编码比特流; 以及信号映射模块，其向MLC存储器单元施加脉冲以便将编码比特流写入MLC存储器单元。在设备中，'a'和'm'可以是大于或等于2的整数，'k'和'n'可以是大于或等于1的整数，'n'可能大于'k'。在设备中存储数据的方法可以包括以k / n的码率对'k'位数据进行编码，以产生编码比特流。从设备读取数据的方法可以包括以n / k的码率对'n'比特的数据进行解码，以产生解码比特流。

64. 发明授权

US08345484B2 Nonvolatile memory device and system, and method of programming a nonvolatile memory device 有权
标题翻译：非易失性存储器件和系统以及非易失性存储器件的编程方法
公开(公告)号：US08345484B2
公开(公告)日：2013-01-01
申请号：US12859860
申请日：2010-08-20
申请人： Dong-Ku Kang , Hyeong-Jun Kim
发明人： Dong-Ku Kang , Hyeong-Jun Kim
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/10 , G11C16/3454
摘要： A method of programming a non-volatile memory including N-bit multi-level cell (MLC) memory includes executing an incremental step pulse programming (ISPP) operation on the MLC memory cells, where the ISPP operation includes a programming sequence of first through Nth page programming operations, where N is an integer of 2 or more. The programming sequence further includes an erase programming that is executed after the (N−1)th page programming operation and before the Nth page programming operation, where the erase page programming increases a threshold voltage distribution of erase cells among the MLC memory cells.
摘要翻译：一种编程包括N位多电平单元（MLC）存储器的非易失性存储器的方法包括在MLC存储器单元上执行增量步进脉冲编程（ISPP）操作，其中ISPP操作包括第一至第N的编程序列页编程操作，其中N是2或更大的整数。编程序列还包括在第（N-1）页编程操作之后和在第N页编程操作之前执行的擦除编程，其中擦除页编程增加MLC存储器单元中的擦除单元的阈值电压分布。

65. 发明授权

US08208298B2 MSB-based error correction for flash memory system 有权
标题翻译：基于MSB的闪存系统的纠错
公开(公告)号：US08208298B2
公开(公告)日：2012-06-26
申请号：US12836249
申请日：2010-07-14
申请人： Dong-Ku Kang , Seung-Jae Lee , Jun-Jin Kong
发明人： Dong-Ku Kang , Seung-Jae Lee , Jun-Jin Kong
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C11/5642 , G06F11/1068 , G11C16/0483 , G11C16/26 , G11C16/3418 , G11C2029/0411
摘要： A flash memory system includes a multi-bit flash memory device having a memory cell array including memory cells arranged in rows and columns; a read circuit configured to read data from the memory cell array; and control logic configured to control the read circuit so as to successively read data from a selected memory cell and adjacent memory cells to the selected memory cell in response to a request for a read operation with respect to MSB data stored in the selected memory cell. A compare circuit is configured to compare data read from the adjacent memory cells to the selected memory cell provided from the multi-bit flash memory device and to correct data read from the selected memory cells based upon the comparison result.
摘要翻译：闪存系统包括具有存储单元阵列的多位闪存器件，该存储器单元阵列包括以行和列排列的存储器单元; 读取电路，被配置为从存储单元阵列读取数据; 以及控制逻辑，被配置为控制所述读取电路，以便响应于对存储在所选择的存储器单元中的MSB数据的读取操作的请求，连续地将数据从所选择的存储器单元和相邻存储器单元读取到所选择的存储器单元。比较电路被配置为将从相邻存储器单元读取的数据与从多位闪存器件提供的所选择的存储器单元进行比较，并且基于比较结果校正从所选存储器单元读取的数据。

66. 发明授权

US08112693B2 Error control code apparatuses and methods of using the same 有权
标题翻译：错误控制代码设备及其使用方法
公开(公告)号：US08112693B2
公开(公告)日：2012-02-07
申请号：US11905734
申请日：2007-10-03
申请人： Jun Jin Kong , Seung-Hwan Song , Dong Hyuk Chae , Kyoung Lae Cho , Seung Jae Lee , Nam Phil Jo , Sung Chung Park , Dong Ku Kang
发明人： Jun Jin Kong , Seung-Hwan Song , Dong Hyuk Chae , Kyoung Lae Cho , Seung Jae Lee , Nam Phil Jo , Sung Chung Park , Dong Ku Kang
IPC分类号： G11C29/00
CPC分类号： G06F11/1072
摘要： An Error Control Code (ECC) apparatus applied to a memory of a Multi-Level Cell (MLC) method may include: a bypass control signal generator generating a bypass control signal; and an ECC performing unit that may include at least two ECC decoding blocks, determining whether to bypass a portion of the at least two ECC decoding blocks based on the bypass control signal, and/or performing an ECC decoding. In addition or in the alternative, the ECC performing unit may include at least two ECC encoding blocks, determining whether to bypass a portion of the at least two ECC encoding blocks based on the bypass control signal, and/or performing an ECC encoding. An ECC method applied to a memory of a MLC method and a computer-readable recording medium storing a program for implementing an EEC method applied to a memory of a MLC method are also disclose.
摘要翻译：应用于多电平单元（MLC）方法的存储器的错误控制码（ECC）装置可以包括：旁路控制信号发生器，其生成旁路控制信号; 以及ECC执行单元，其可以包括至少两个ECC解码块，基于旁路控制信号确定是否绕过所述至少两个ECC解码块的一部分，和/或执行ECC解码。另外或在替代方案中，ECC执行单元可以包括至少两个ECC编码块，基于旁路控制信号确定是否绕过至少两个ECC编码块的一部分，和/或执行ECC编码。还公开了应用于MLC方法的存储器的ECC方法和存储用于实现应用于MLC方法的存储器的EEC方法的程序的计算机可读记录介质。

67. 发明授权

US08028215B2 Error control code apparatuses and methods of using the same 有权
标题翻译：错误控制代码设备及其使用方法
公开(公告)号：US08028215B2
公开(公告)日：2011-09-27
申请号：US11905733
申请日：2007-10-03
申请人： Jun Jin Kong , Seung-Hwan Song , Young Hwan Lee , Dong Hyuk Chae , Kyong Lae Cho , Nam Phil Jo , Sung Chung Park , Dong Ku Kang
发明人： Jun Jin Kong , Seung-Hwan Song , Young Hwan Lee , Dong Hyuk Chae , Kyong Lae Cho , Nam Phil Jo , Sung Chung Park , Dong Ku Kang
IPC分类号： H03M13/00 , G06F11/00
CPC分类号： G06F11/1008
摘要： An Error Control Code (ECC) apparatus may include a control signal generator that generates an ECC control signal based on channel information. The ECC apparatus also may include: a plurality of ECC encoding controllers that output data respectively inputted via storage elements corresponding to the ECC control signal; and/or an encoding unit that encodes, using a plurality of data outputted from the plurality of ECC encoding controllers, encoding input data into a number of subdata corresponding to the ECC control signal. In addition or in the alternative, the ECC apparatus may include: a plurality of ECC decoding controllers that output data respectively inputted via the storage elements corresponding to the ECC control signal; and/or a decoding unit that decodes, using a plurality of data outputted from the plurality of ECC decoding controllers, a number of decoding input data corresponding to the ECC control signal into one piece of output data.
摘要翻译：错误控制码（ECC）装置可以包括基于频道信息产生ECC控制信号的控制信号发生器。 ECC装置还可以包括：多个ECC编码控制器，其输出经由与ECC控制信号对应的存储元件分别输入的数据; 和/或编码单元，其使用从所述多个ECC编码控制器输出的多个数据，将输入数据编码为对应于所述ECC控制信号的多个子数据进行编码。另外或者可选地，ECC装置可以包括：多个ECC解码控制器，其输出经由与ECC控制信号对应的存储元件分别输入的数据; 和/或解码单元，其使用从所述多个ECC解码控制器输出的多个数据将对应于所述ECC控制信号的多个解码输入数据解码为一条输出数据。

68. 发明授权

US07898853B2 Multi-bit data memory system and read operation 有权
标题翻译：多位数据存储系统和读操作
公开(公告)号：US07898853B2
公开(公告)日：2011-03-01
申请号：US12204860
申请日：2008-09-05
申请人： Seung-Jae Lee , Dong-Ku Kang , Seung-Hwan Song , Jun-Jin Kong , Dong-Hyuk Chae , Sung-Chung Park
发明人： Seung-Jae Lee , Dong-Ku Kang , Seung-Hwan Song , Jun-Jin Kong , Dong-Hyuk Chae , Sung-Chung Park
IPC分类号： G11C16/04
CPC分类号： G11C11/5642 , G11C16/3418
摘要： Provided is a read operation for a N-bit data non-volatile memory system. The method includes determining in relation to data states of adjacent memory cells associated with a selected memory cell in the plurality of memory cells whether read data obtained from the selected memory cell requires compensation, and if the read data requires compensation, replacing the read data with compensated read data.
摘要翻译：提供了一种用于N位数据非易失性存储器系统的读取操作。该方法包括：确定与多个存储器单元中的所选存储单元相关联的相邻存储器单元的数据状态，从所选择的存储器单元获得的读取数据是否需要补偿，以及如果读取的数据需要补偿，则用补偿读数据。

69. 发明授权

US07876614B2 Multi-bit flash memory device and program and read methods thereof 有权
标题翻译：多位闪存设备及其程序和读取方法
公开(公告)号：US07876614B2
公开(公告)日：2011-01-25
申请号：US12255211
申请日：2008-10-21
申请人： Dong-Ku Kang , Dong-Hyuk Chae , Seung-Jae Lee
发明人： Dong-Ku Kang , Dong-Hyuk Chae , Seung-Jae Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/3418 , G11C2211/5646
摘要： The flash memory device of the present invention is configured to program a plurality of bits per unit cell, wherein a program condition of a selected bit is set according to whether a program for the most previous bit to the selected bit for programming is skipped or not skipped. As a result, an accurate programming and reading operation is possible even in case a program for a middle bit is skipped.
摘要翻译：本发明的闪速存储器件被配置为对每个单位单元的多个位进行编程，其中根据用于编程的选择位的最前一位的程序是否被跳过来设置所选位的程序状态跳过因此，即使在中间位的程序被跳过的情况下也可以进行准确的编程和读取操作。

70. 发明授权

US07800954B2 Apparatus for reading data and method using the same 有权
标题翻译：用于读取数据的装置和使用该装置的方法
公开(公告)号：US07800954B2
公开(公告)日：2010-09-21
申请号：US12007921
申请日：2008-01-17
申请人： Seung-Hwan Song , Jun Jin Kong , Sung Chung Park , Dong Hyuk Chae , Seung Jae Lee , Dong Ku Kang
发明人： Seung-Hwan Song , Jun Jin Kong , Sung Chung Park , Dong Hyuk Chae , Seung Jae Lee , Dong Ku Kang
IPC分类号： G11C11/34
CPC分类号： G11C16/26 , G11C7/1006 , G11C11/5642
摘要： The method for reading data according to example embodiments includes comparing a threshold voltage of a memory cell with a first boundary voltage, comparing the threshold voltage with a second boundary voltage having a higher voltage level than that of the first boundary voltage, and determining data of the memory cell based on the threshold voltage, the first boundary voltage, and the second boundary voltage.
摘要翻译：根据示例实施例的用于读取数据的方法包括将存储器单元的阈值电压与第一边界电压进行比较，将阈值电压与具有比第一边界电压的电压电平更高的电压电平的第二边界电压进行比较，以及确定数据所述存储单元基于所述阈值电压，所述第一边界电压和所述第二边界电压。

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