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1. 发明授权

US08345484B2 Nonvolatile memory device and system, and method of programming a nonvolatile memory device 有权
标题翻译：非易失性存储器件和系统以及非易失性存储器件的编程方法
公开(公告)号：US08345484B2
公开(公告)日：2013-01-01
申请号：US12859860
申请日：2010-08-20
申请人： Dong-Ku Kang , Hyeong-Jun Kim
发明人： Dong-Ku Kang , Hyeong-Jun Kim
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/10 , G11C16/3454
摘要： A method of programming a non-volatile memory including N-bit multi-level cell (MLC) memory includes executing an incremental step pulse programming (ISPP) operation on the MLC memory cells, where the ISPP operation includes a programming sequence of first through Nth page programming operations, where N is an integer of 2 or more. The programming sequence further includes an erase programming that is executed after the (N−1)th page programming operation and before the Nth page programming operation, where the erase page programming increases a threshold voltage distribution of erase cells among the MLC memory cells.
摘要翻译：一种编程包括N位多电平单元（MLC）存储器的非易失性存储器的方法包括在MLC存储器单元上执行增量步进脉冲编程（ISPP）操作，其中ISPP操作包括第一至第N的编程序列页编程操作，其中N是2或更大的整数。编程序列还包括在第（N-1）页编程操作之后和在第N页编程操作之前执行的擦除编程，其中擦除页编程增加MLC存储器单元中的擦除单元的阈值电压分布。

2. 发明申请

US20110044104A1 NONVOLATILE MEMORY DEVICE AND SYSTEM, AND METHOD OF PROGRAMMING A NONVOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件和系统，以及非易失性存储器件的编程方法
公开(公告)号：US20110044104A1
公开(公告)日：2011-02-24
申请号：US12859860
申请日：2010-08-20
申请人： Dong-Ku Kang , Hyeong-Jun Kim
发明人： Dong-Ku Kang , Hyeong-Jun Kim
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/10 , G11C16/3454
摘要： A method of programming a non-volatile memory including N-bit multi-level cell (MLC) memory includes executing an incremental step pulse programming (ISPP) operation on the MLC memory cells, where the ISPP operation includes a programming sequence of first through Nth page programming operations, where N is an integer of 2 or more. The programming sequence further includes an erase programming that is executed after the (N−1)th page programming operation and before the Nth page programming operation, where the erase page programming increases a threshold voltage distribution of erase cells among the MLC memory cells
摘要翻译：一种编程包括N位多电平单元（MLC）存储器的非易失性存储器的方法包括在MLC存储器单元上执行增量步进脉冲编程（ISPP）操作，其中ISPP操作包括第一至第N的编程序列页编程操作，其中N是2或更大的整数。编程序列还包括在第（N-1）页编程操作之后和第N页编程操作之前执行的擦除编程，其中擦除页编程增加MLC存储器单元中的擦除单元的阈值电压分布

3. 发明授权

US08477533B2 Over-sampling read operation for a flash memory device 有权
公开(公告)号：US08477533B2
公开(公告)日：2013-07-02
申请号：US13402922
申请日：2012-02-23
申请人： Dong-Ku Kang
发明人： Dong-Ku Kang
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C11/5642
摘要： A flash memory device and a reading method are provided where memory cells are divided into at least two groups. Memory cells are selected according to a threshold voltage distribution. Data stored in the selected memory cells are detected and the data is latched corresponding to one of the at least two groups according to a first read operation. A second read operation detects and latches data of the memory cells corresponding to another one of the at least two groups. The data is processed through a soft decision algorithm during the second read operation.

4. 发明授权

US07791938B2 MSB-based error correction for flash memory system 有权
标题翻译：基于MSB的闪存系统的纠错
公开(公告)号：US07791938B2
公开(公告)日：2010-09-07
申请号：US12169109
申请日：2008-07-08
申请人： Dong-Ku Kang , Seung-Jae Lee , Jun-Jin Kong
发明人： Dong-Ku Kang , Seung-Jae Lee , Jun-Jin Kong
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C11/5642 , G06F11/1068 , G11C16/0483 , G11C16/26 , G11C16/3418 , G11C2029/0411
摘要： A flash memory system includes a multi-bit flash memory device having a memory cell array including memory cells arranged in rows and columns; a read circuit configured to read data from the memory cell array; and control logic configured to control the read circuit so as to successively read data from a selected memory cell and adjacent memory cells to the selected memory cell in response to a request for a read operation with respect to MSB data stored in the selected memory cell. A compare circuit is configured to compare data read from the adjacent memory cells to the selected memory cell provided from the multi-bit flash memory device and to correct data read from the selected memory cells based upon the comparison result.
摘要翻译：闪存系统包括具有存储单元阵列的多位闪存器件，该存储器单元阵列包括以行和列排列的存储器单元; 读取电路，被配置为从存储单元阵列读取数据; 以及控制逻辑，被配置为控制所述读取电路，以便响应于对存储在所选择的存储器单元中的MSB数据的读取操作的请求，连续地将数据从所选择的存储器单元和相邻存储器单元读取到所选择的存储器单元。比较电路被配置为将从相邻存储器单元读取的数据与从多位闪存器件提供的所选择的存储器单元进行比较，并且基于比较结果校正从所选存储器单元读取的数据。

5. 发明授权

US07545677B2 Nonvolatile memory device and methods of programming and reading the same 有权
标题翻译：非易失性存储器件和编程和读取方法
公开(公告)号：US07545677B2
公开(公告)日：2009-06-09
申请号：US12136150
申请日：2008-06-10
申请人： Seung-Jae Lee , Dong-Hyuk Chae , Dong-Ku Kang
发明人： Seung-Jae Lee , Dong-Hyuk Chae , Dong-Ku Kang
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/26 , G11C2216/14
摘要： A read method of a non-volatile memory device includes reading an initial threshold voltage value of an index cell from threshold voltage information cells that store information indicating the initial threshold voltage, determining a current threshold voltage value from the index cell, and comparing the initial threshold voltage value and the current threshold voltage value to calculate a shifted threshold voltage level of the index cell. A read voltage is changed by the shifted threshold voltage level to read user data using the changed read voltage.
摘要翻译：非易失性存储器件的读取方法包括从存储指示初始阈值电压的信息的阈值电压信息单元读取索引单元的初始阈值电压值，从索引单元确定当前阈值电压值，以及比较初始值阈值电压值和电流阈值电压值，以计算索引单元的偏移阈值电压电平。读取电压由偏移的阈值电压电平改变，以便使用改变的读取电压来读取用户数据。

6. 发明授权

US09691472B2 Non-volatile memory device and method of programming the same 有权
公开(公告)号：US09691472B2
公开(公告)日：2017-06-27
申请号：US15067620
申请日：2016-03-11
申请人： Dong-Ku Kang
发明人： Dong-Ku Kang
IPC分类号： G11C11/34 , G11C11/56 , G11C16/04 , G11C16/10 , G11C16/32
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/32 , G11C2211/5641 , G11C2211/5648
摘要： A non-volatile memory device and a method of programming a non-volatile memory device including a plurality of memory cells that are stacked in a vertical direction over a substrate and connected to n word lines, wherein n is an integer greater than or equal to 3. The method includes programming memory cells of second to n−1-th word lines, from among first to n-th word lines that are sequentially disposed in the vertical direction over the substrate, to a multi-level state, wherein a multi-level program operation is sequentially performed from the second to n−1-th word lines in an order in which the word lines are disposed; and programming memory cells of the first word line to a single level state after the programming memory cells of the second to n−1-th word lines to a multi-level state.

7. 发明授权

US08149618B2 Over-sampling read operation for a flash memory device 有权
标题翻译：闪存设备的过采样读取操作
公开(公告)号：US08149618B2
公开(公告)日：2012-04-03
申请号：US12034872
申请日：2008-02-21
申请人： Dong-Ku Kang
发明人： Dong-Ku Kang
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C11/5642
摘要： A flash memory device and a reading method are provided where memory cells are divided into at least two groups. Memory cells are selected according to a threshold voltage distribution. Data stored in the selected memory cells are detected and the data is latched corresponding to one of the at least two groups according to a first read operation. A second read operation detects and latches data of the memory cells corresponding to another one of the at least two groups. The data is processed through a soft decision algorithm during the second read operation.
摘要翻译：提供闪存器件和读取方法，其中存储器单元被分成至少两组。根据阈值电压分布选择存储单元。根据第一读取操作，检测存储在所选择的存储器单元中的数据并且对应于至少两个组中的一个锁存数据。第二读取操作检测并锁存与至少两个组中的另一组对应的存储单元的数据。在第二次读取操作期间通过软判决算法处理数据。

8. 发明申请

US20100277979A1 MSB-BASED ERROR CORRECTION FOR FLASH MEMORY SYSTEM 有权
标题翻译：用于闪存存储器系统的基于MSB的错误校正
公开(公告)号：US20100277979A1
公开(公告)日：2010-11-04
申请号：US12836249
申请日：2010-07-14
申请人： Dong-Ku Kang , Seung-Jae Lee , Jun-Jin Kong
发明人： Dong-Ku Kang , Seung-Jae Lee , Jun-Jin Kong
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C11/5642 , G06F11/1068 , G11C16/0483 , G11C16/26 , G11C16/3418 , G11C2029/0411
摘要： A flash memory system includes a multi-bit flash memory device having a memory cell array including memory cells arranged in rows and columns; a read circuit configured to read data from the memory cell array; and control logic configured to control the read circuit so as to successively read data from a selected memory cell and adjacent memory cells to the selected memory cell in response to a request for a read operation with respect to MSB data stored in the selected memory cell. A compare circuit is configured to compare data read from the adjacent memory cells to the selected memory cell provided from the multi-bit flash memory device and to correct data read from the selected memory cells based upon the comparison result.
摘要翻译：闪存系统包括具有存储单元阵列的多位闪存器件，该存储器单元阵列包括以行和列排列的存储器单元; 读取电路，被配置为从存储单元阵列读取数据; 以及控制逻辑，被配置为控制所述读取电路，以便响应于对存储在所选择的存储器单元中的MSB数据的读取操作的请求，连续地将数据从所选择的存储器单元和相邻存储器单元读取到所选择的存储器单元。比较电路被配置为将从相邻存储器单元读取的数据与从多位闪存器件提供的所选择的存储器单元进行比较，并且基于比较结果校正从所选存储器单元读取的数据。

9. 发明授权

US07701775B2 Flash memory device utilizing multi-page program method 有权
标题翻译：闪存设备采用多页程序方式
公开(公告)号：US07701775B2
公开(公告)日：2010-04-20
申请号：US12034876
申请日：2008-02-21
申请人： Dong-Ku Kang
发明人： Dong-Ku Kang
IPC分类号： G11C16/06
CPC分类号： G11C16/3454 , G11C11/5628 , G11C2211/5621 , G11C2216/14
摘要： A flash memory device is configured to store multi-bit data on one cell utilizing fewer program operations. The flash memory device includes a memory cell, a sense amplifier and a write driver circuit. The sense amplifier is connected to a word line and a bit line. The sense amplifier and write driver circuit store data bits to be programmed on the memory cell. The sense amplifier and write driver circuit drives the bit line through a program voltage during a program execution period when at least one bit from among the data bits to be programmed is a program data bit, and performs a verify read operation when a program verify code representing a verify read period corresponds to a state of the data bits to be programmed.
摘要翻译：闪存设备被配置为使用较少的程序操作在一个单元上存储多位数据。闪速存储器件包括存储单元，读出放大器和写入驱动器电路。读出放大器连接到字线和位线。读出放大器和写入驱动器电路存储要在存储器单元上编程的数据位。当要编程的数据位中的至少一位是程序数据位时，读出放大器和写入驱动器电路在程序执行期间驱动位线通过编程电压，并且当程序验证代码表示验证读取周期对应于要编程的数据位的状态。

10. 发明申请

US20090296482A1 Non-volatile memory device and method of operation therefor 有权
公开(公告)号：US20090296482A1
公开(公告)日：2009-12-03
申请号：US12461317
申请日：2009-08-07
申请人： Dong-Ku Kang , Hee-Won Lee
发明人： Dong-Ku Kang , Hee-Won Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C2211/5642
摘要： In one embodiment, the non-volatile memory device includes a plurality of normal memory cells, and at least one flag memory cell associated with one of the plurality of normal memory cells. A normal page buffer is configured to store data read from one of the plurality of normal memory cells. The normal page buffer includes a main latch storing the read data. A control circuit is configured to selectively change data stored in the main latch during a read operation based on a state of the flag memory cell.

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