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61. 发明申请

WO2019102213A1 REMOTE DEVICE CONTROL 审中-公开
公开(公告)号：WO2019102213A1
公开(公告)日：2019-05-31
申请号：PCT/GB2018/053397
申请日：2018-11-23
申请人： ARM LIMITED
发明人： GARNIER, Donatien , JOAUG, Jerome
IPC分类号： H04L29/06 , H04W88/16 , H04W4/70 , H04W12/06
摘要： Disclosed is a server arrangement for control of remote devices, such as Internet of Things devices. The server arrangement comprises a network interface for connection to a gateway device, a data store, and processing means. The processing means are configured to establish through the network interface a network connection to the gateway device, transfer security credentials over the network connection to the gateway device, to enable the gateway device to obtain control of one or more Internet of Things devices, establish an agency relationship with the gateway device to authorise the gateway device to perform control of Internet of Things devices on behalf of the server arrangement, creating a distributed management architecture, assign tasks to be performed the gateway device on behalf of the server arrangement, receive from the gateway device event data relating to Internet of Things devices, and store the event data in the data store.

62. 发明申请

WO2019069042A1 HANDLING ERRORS IN BUFFERS 审中-公开
公开(公告)号：WO2019069042A1
公开(公告)日：2019-04-11
申请号：PCT/GB2018/052450
申请日：2018-08-30
申请人： ARM LIMITED
发明人： VENU, Balaji , BOETTCHER, Matthias Lothar , EYOLE, Mbou
IPC分类号： G06F11/16 , G06F11/18 , G06F11/22 , G06F11/267
摘要： A buffer (72), (74), (76), (60), (78), (20), (82-90) has a number of entries for buffering items associated with data processing operations. Buffer control circuitry (100) has a redundant allocation mode in which, on allocating a given item to the buffer, the item is allocated to two or more redundant entries of the buffer. On reading or draining an item from the buffer, the redundant entries are compared and an error handling response is triggered if a mismatch is detected. By effectively reducing the buffer capacity, this simplifies testing for faults in buffer entries.

63. 发明申请

WO2019025754A1 COUNTING ELEMENTS IN DATA ITEMS IN A DATA PROCESSING APPARATUS 审中-公开
公开(公告)号：WO2019025754A1
公开(公告)日：2019-02-07
申请号：PCT/GB2018/052001
申请日：2018-07-13
申请人： ARM LIMITED
发明人： VICENTE, Alejandro Martinez , BEU, Jesse Garrett , EYOLE, Mbou , HAYES, Timothy
IPC分类号： G06F9/30
摘要： An apparatus and method of operating the apparatus are provided for performing a count operation. Instruction decoder circuitry is responsive to a count instruction specifying an input data item to generate control signals to control the data processing circuitry to perform a count operation. The count operation determines a count value indicative of a number of input elements of a subset of elements in the specified input data item which have a value which matches a reference value in a reference element in a reference data item. A plurality of count operations may be performed to determine a count data item corresponding to the input data item. A register scatter storage instruction, a gather index generation instruction, and respective apparatuses responsive to them, as well as simulator implementations are also provided.

64. 发明申请

WO2019012253A1 METHOD AND APPARATUS FOR TWO-LAYER COPY-ON-WRITE 审中-公开
公开(公告)号：WO2019012253A1
公开(公告)日：2019-01-17
申请号：PCT/GB2018/051901
申请日：2018-07-05
申请人： ARM LIMITED
发明人： BEARD, Jonathan Curtis , RUSITORU, Roxana , DUNHAM, Curtis Glenn
IPC分类号： G06F12/109 , G06F12/1036
摘要： A system, apparatus and method are provided in which a range of virtual memory addresses and a copy of that range are mapped to the same first system address range in a data processing system until an address in the virtual memory address range, or its copy, is written 5 to. The common system address range includes a number of divisions. Responsive to a write request to an address in a division of the common address range, a second system address range is generated. The second system address range is mapped to the same physical addresses as the first system address range, except that the division containing the address to be written to and its corresponding division in the second system address range are mapped to 10 different physical addresses. First layer mapping data may be stored in a range table buffer and updated when the second system address range is generated.

65. 发明申请

WO2019011653A1 TESTING BIT VALUES INSIDE VECTOR ELEMENTS 审中-公开
公开(公告)号：WO2019011653A1
公开(公告)日：2019-01-17
申请号：PCT/EP2018/067234
申请日：2018-06-27
申请人： ARM LIMITED
发明人： MAGKLIS, Grigorios , STEPHENS, Nigel John
IPC分类号： G06F9/30
摘要： An apparatus and method of operating an apparatus are provided. The apparatus is responsive to a bit-testing instruction which specifies a source vector register and an index to perform a bit-testing procedure on plural elements stored in the source vector register to generate plural result bits. The bit-testing procedure comprises, for each processed element of the plural elements, setting a respective result bit of the plural result bits in dependence on a value of a tested bit at a bit position in the processed element of the source vector register indicated by the index. This bit-testing instruction thus enables increased performance of program code which is required to perform multiple bit tests and can be suitably formulated into a vectorised form.

66. 发明申请

WO2019008324A1 AN APPARATUS AND METHOD FOR CONTROLLING EXECUTION OF INSTRUCTIONS 审中-公开
公开(公告)号：WO2019008324A1
公开(公告)日：2019-01-10
申请号：PCT/GB2018/051717
申请日：2018-06-20
申请人： ARM LIMITED
发明人： BARNES, Graeme Peter
IPC分类号： G06F9/30 , G06F9/32 , G06F9/34 , G06F9/38 , G06F21/00
摘要： An apparatus and method are provided for controlling execution of certain instructions. The apparatus has processing circuitry to execute a sequence of instructions, an integer storage element to store an integer value for access by the processing circuitry, and a capability storage element for storing a capability for access by the processing circuitry. A capability usage storage is then used to store capability usage information. The processing circuitry is responsive to execution of at least one instruction in the sequence of instructions to generate, in dependence on the capability usage information, a result to be stored in a destination storage element. In particular, when the capability usage information identifies a capability state, the result is generated as a capability, and the capability storage element is selected as the destination storage element. Conversely, when the capability usage information identifies a non-capability state, the result is generated as an integer value, and the integer storage element is selected as the destination storage element. This allows both capability and non-capability generating variants of an instruction to be specified, without requiring separate instructions to be provided within the instruction set.

67. 发明申请

WO2019002816A1 MEMORY REGION LOCKING 审中-公开
公开(公告)号：WO2019002816A1
公开(公告)日：2019-01-03
申请号：PCT/GB2018/051583
申请日：2018-06-11
申请人： ARM LIMITED
发明人： KOVACEVIC, Djordje , PARKER, Jason , EVANS, Matthew Lucien , STOCKWELL, Gareth Rhys
IPC分类号： G06F12/14 , G06F9/52
摘要： Apparatus for processing data uses memory access circuitry to enforce ownership rights of a plurality of memory regions within a memory, a given memory region among the plurality of memory regions having a given owning process specified from among a plurality of processes. A given owning process has exclusive rights to control access to given owned data stored within the given memory region. The memory access circuitry is responsive to a first access command from a first processing element for the given memory region to perform an access sequence comprising switching a lock flag for the given memory region to a locked state, performing an access operation specified by the access command, and switching the lock flag to an unlocked state. The memory access circuitry is responsive to a second access command from a second processing element for the given memory region while the lock flag is in said locked state to block action of the second access command.

68. 发明申请

WO2019002814A1 REALM MANAGEMENT UNIT-PRIVATE MEMORY REGIONS 审中-公开
公开(公告)号：WO2019002814A1
公开(公告)日：2019-01-03
申请号：PCT/GB2018/051581
申请日：2018-06-11
申请人： ARM LIMITED
发明人： PARKER, Jason , EVANS, Matthew Lucien , STOCKWELL, Gareth Rhys , KOVACEVIC, Djordje
IPC分类号： G06F12/14 , G06F21/62
摘要： Memory access circuitry (26) enforces ownership rights for memory regions. A given memory region is associated with an owner realm specified from multiple realms, each realm corresponding to a portion of at least one software process executed by processing circuitry (8). A realm management unit (RMU) (20) is provided to perform realm management operations for managing the realms. The memory access circuitry (26) controls access to a given memory region in dependence on at least one status attribute specifying whether the given memory region is an RMU-private memory region reserved for exclusive access by the RMU (20).

69. 发明申请

WO2019002813A1 SUB-REALMS 审中-公开
公开(公告)号：WO2019002813A1
公开(公告)日：2019-01-03
申请号：PCT/GB2018/051580
申请日：2018-06-11
申请人： ARM LIMITED
发明人： PARKER, Jason , EVANS, Matthew Lucien , STOCKWELL, Gareth Rhys , WEIDMANN, Martin
IPC分类号： G06F12/14
摘要： Memory access circuitry (26) enforces ownership rights for memory regions. A given memory region is associated with an owner realm specified from multiple realms, each realm corresponding to a portion of at least one software process executed by processing circuitry (8). A realm management unit (20) initialises the realms. The realm management unit is configured to initialise realms including a full realm which corresponds to a given software process and a sub-realm corresponding to a given address range within the given software process.

70. 发明申请

WO2019001896A1 ADDRESS TRANSLATION DATA INVALIDATION 审中-公开
公开(公告)号：WO2019001896A1
公开(公告)日：2019-01-03
申请号：PCT/EP2018/064497
申请日：2018-06-01
申请人： ARM LIMITED
发明人： HORSNELL, Matthew James , MAGKLIS, Grigorios , GRISENTHWAITE, Richard Roy
IPC分类号： G06F12/1027
摘要： A data processing system (2) including one or more transaction buffers (16, 18, 20) storing address translation data executes translation buffer invalidation instructions TLBI within respective address translation contexts VMID, ASID, X. Translation buffer invalidation signals generated as a consequence of execution of the translation buffer invalidation instructions are broadcast to respective translation buffers and include signals which specify the address translation context of the translation buffer invalidation instruction that was executed. This address translation context specified within the translation buffer invalidation signals is used to gate whether or not those translation buffer invalidation signals when received by translation buffers which are potential targets for the invalidation are or are not flushed. The address translation context data provided within the translation buffer invalidation signals may also be used to control whether or not local memory transactions for a local transactional memory access are or are not aborted upon receipt of the translation buffer invalidation signals.

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