基本信息:
- 专利标题： HANDLING ERRORS IN BUFFERS
- 申请号：PCT/GB2018/052450 申请日：2018-08-30
- 公开(公告)号：WO2019069042A1 公开(公告)日：2019-04-11
- 发明人： VENU, Balaji , BOETTCHER, Matthias Lothar , EYOLE, Mbou
- 申请人： ARM LIMITED
- 申请人地址： 110 Fulbourn Road Cherry Hinton Cambridge CB1 9NJ GB
- 专利权人： ARM LIMITED
- 当前专利权人： ARM LIMITED
- 当前专利权人地址： 110 Fulbourn Road Cherry Hinton Cambridge CB1 9NJ GB
- 代理机构： BERRYMAN, Robert
- 优先权： GB1716280.1 20171005
- 主分类号： G06F11/16
- IPC分类号： G06F11/16 ; G06F11/18 ; G06F11/22 ; G06F11/267
摘要：
A buffer (72), (74), (76), (60), (78), (20), (82-90) has a number of entries for buffering items associated with data processing operations. Buffer control circuitry (100) has a redundant allocation mode in which, on allocating a given item to the buffer, the item is allocated to two or more redundant entries of the buffer. On reading or draining an item from the buffer, the redundant entries are compared and an error handling response is triggered if a mismatch is detected. By effectively reducing the buffer capacity, this simplifies testing for faults in buffer entries.