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51. 发明申请

US20080316806A1 Phase change memory device 有权
标题翻译：相变存储器件
公开(公告)号：US20080316806A1
公开(公告)日：2008-12-25
申请号：US12213195
申请日：2008-06-16
申请人： Kiyoshi Nakai , Shuichi Tsukada , Yusuke Jono
发明人： Kiyoshi Nakai , Shuichi Tsukada , Yusuke Jono
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0023 , G11C11/5678 , G11C13/0004 , G11C13/0028 , G11C13/0069 , G11C2013/0078 , G11C2213/72
摘要： A phase change memory device comprises: a phase change element for rewritably storing data by changing a resistance state; a memory cell arranged at an intersection of a word line and a bit line and formed of the phase change element and a diode connected in series; a select transistor formed in a diffusion layer below the memory cell, for selectively controlling electric connection between an anode of the diode and a ground line in response to a potential of the word line connected to a gate; and a precharge circuit for precharging the diffusion layer below the memory cell corresponding to a non-selected word line to a predetermined voltage and for disconnecting the diffusion layer below the memory cell corresponding to a selected word line from the predetermined voltage.
摘要翻译：相变存储器件包括：相变元件，用于通过改变电阻状态来重写地存储数据; 存储单元，布置在字线和位线的交点处，并由所述相变元件和串联连接的二极管形成; 形成在存储单元下方的扩散层中的选择晶体管，用于响应于连接到栅极的字线的电位选择性地控制二极管的阳极与地线之间的电连接; 以及预充电电路，用于将对应于未选择字线的存储单元下面的扩散层预充电到预定电压，并且用于将与所选择的字线相对应的存储单元下面的扩散层与预定电压断开。

52. 发明申请

US20080062805A1 SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：半导体存储设备
公开(公告)号：US20080062805A1
公开(公告)日：2008-03-13
申请号：US11845605
申请日：2007-08-27
申请人： Kiyoshi Nakai
发明人： Kiyoshi Nakai
IPC分类号： G11C8/00
CPC分类号： G11C11/16 , G11C7/1078 , G11C7/1096 , G11C7/18 , H01L27/228 , H01L27/24
摘要： Semiconductor storage device of reduced layout area having memory cell rows accessed selectively. Memory cells, each including a programmable resistive element, are connected by a bit line to form a memory cell row. Selecting circuit for selecting a memory cell row includes a first NMOS transistor having first end connected to write amplifier, second end connected to the bit line, and a gate, and controlled such that, if the write amplifier outputs a voltage level on power-supply side after the block-select activating signal has been activated, a voltage of the same polarity as that of the power-supply voltage and exceeding the voltage level of the power supply is applied to the gate. A second NMOS transistor has first end to which the block-select activating signal is applied, a gate connected to the power supply, and second end connected to the gate of the first NMOS transistor.
摘要翻译：具有存储单元行选择性地减小的布局区域的半导体存储装置。每个包括可编程电阻元件的存储单元通过位线连接以形成存储单元行。用于选择存储单元行的选择电路包括第一NMOS晶体管，其第一端连接到写入放大器，连接到位线的第二端和栅极，并被控制，使得如果写入放大器在电源上输出电压电平在块选择激活信号被激活之后，与门电压相加的电压与电源电压相同极性的电压超过电源电压。第二NMOS晶体管具有施加块选择激活信号的第一端，连接到电源的栅极，以及连接到第一NMOS晶体管的栅极的第二端。

53. 发明申请

US20070023639A1 Liquid chromatographic apparatus 审中-公开
标题翻译：液相色谱仪
公开(公告)号：US20070023639A1
公开(公告)日：2007-02-01
申请号：US10595146
申请日：2004-09-01
申请人： Kazuko Yamashita , Kiyoshi Nakai
发明人： Kazuko Yamashita , Kiyoshi Nakai
IPC分类号： H01J49/00 , B01D59/44
CPC分类号： G01N30/463 , G01N30/461 , G01N30/465 , G01N2030/8411
摘要： An apparatus has a one-dimensional analysis column for separating a sample into a plurality of components, a preparative portion for fractionating the separated components, component by component and for keeping a fractionated component, a plurality of trap columns for trapping a component supplied from the preparative portion, a two-dimensional analysis column for further separating a component trapped in the trap columns, into a plurality of components, and a path switching mechanism for effecting switching between a state in which the preparative portion is connected to a first trap column out of the plurality of trap columns and in which the two-dimensional analysis column is connected to a second trap column out of the plurality of trap columns, and a state in which the preparative portion is connected to the second trap column out of the plurality of trap columns and in which the two-dimensional analysis column is connected to the first trap column out of the plurality of trap columns.
摘要翻译：一种装置具有用于将样品分离成多个组分的一维分析柱，用于分馏分离的组分的制备部分，逐个分离并用于保持分馏的组分，多个捕集柱用于捕获从制备部分，用于进一步将陷阱中捕获的成分分离成多个成分的二维分析柱;以及路径切换机构，用于在制备部分与第一捕集塔连接的状态之间进行切换并且其中所述二维分析列与所述多个陷阱列中的第二陷阱柱连接，并且所述制备部分连接到所述多个捕集塔中的所述第二捕集塔的状态捕集塔，并且其中二维分析列连接到多个陷阱co中的第一陷阱列毕业生

54. 发明授权

US06411160B1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US06411160B1
公开(公告)日：2002-06-25
申请号：US09376470
申请日：1999-08-18
申请人： Yoshiro Riho , Kiyoshi Nakai , Hidekazu Egawa , Yukihide Suzuki , Isamu Fujii
发明人： Yoshiro Riho , Kiyoshi Nakai , Hidekazu Egawa , Yukihide Suzuki , Isamu Fujii
IPC分类号： H01L2500
CPC分类号： H01L23/5222 , H01L23/50 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor integrated circuit device which comprises a first interconnect channel including a plurality of second-layer metal interconnect layers extended in a first direction over a semiconductor chip, a second interconnect channel including a plurality of third-layer metal interconnect layers extended in a second direction perpendicular to the first direction, an internal power supply circuit which receives a source voltage supplied from an external terminal and generates a voltage different from the source voltage, and which is provided with stabilizing capacitors, a large part of the stabilizing capacitors are in an area in which the second- and third-layer metal interconnect lines intersect each other.
摘要翻译：在一种半导体集成电路器件中，包括第一互连通道，第一互连通道包括在半导体芯片上沿第一方向延伸的多个第二层金属互连层，第二互连通道，包括在第二互连层中延伸的多个第三层金属互连层内部电源电路，其接收从外部端子提供的源极电压，并产生与源极电压不同的电压，并且设置有稳定电容器，大部分稳定化电容器处于第二和第三层金属互连线彼此相交的区域。

55. 发明授权

US5615156A Semiconductor memory device having plural memory mats with centrally located reserve bit or word lines 失效
标题翻译：半导体存储器件具有多个具有中心位置的保留位或字线的存储垫
公开(公告)号：US5615156A
公开(公告)日：1997-03-25
申请号：US250130
申请日：1994-05-27
申请人： Hiroyuki Yoshida , Takashi Inui , Shigeki Numaga , Kiyoshi Nakai , Yukihide Suzuki
发明人： Hiroyuki Yoshida , Takashi Inui , Shigeki Numaga , Kiyoshi Nakai , Yukihide Suzuki
IPC分类号： G11C11/401 , G11C29/00 , G11C29/04 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： G11C29/80
摘要： A semiconductor memory device having reserve bit lines or word lines for replacing defective bit lines or word lines which can increase a defect relief probability and improve an operational margin. The reserve bit lines or word lines are provided approximately in a central portion of a memory mat. Because of a low probability of defect occurrence in the reserve word lines or bit lines, the probability of defect occurrence can be made low when a defective word line or bit line is replaced with a reserve word line or bit line.
摘要翻译：具有备用位线或字线的半导体存储器件，用于替换有缺陷的位线或字线，这些位线或字线可以增加缺陷消除概率并提高操作余量。保留位线或字线大致设置在存储垫的中央部分。由于在备用字线或位线中存在缺陷发生的可能性低的情况，当用保留字线或位线替换缺陷字线或位线时，可能会使缺陷发生的概率变低。

56. 发明授权

US4260831A Oligomerization of m-isopropenylphenol 失效
标题翻译：间 - 异丙烯基苯酚的低聚
公开(公告)号：US4260831A
公开(公告)日：1981-04-07
申请号：US24424
申请日：1979-03-27
申请人： Shunsuke Matsushima , Kazuhiko Hata , Kentaro Mashita , Shuichi Kanagawa , Shinji Nakao , Kiyoshi Nakai , Kunimasa Kamio
发明人： Shunsuke Matsushima , Kazuhiko Hata , Kentaro Mashita , Shuichi Kanagawa , Shinji Nakao , Kiyoshi Nakai , Kunimasa Kamio
IPC分类号： C07C37/14 , C07C39/17 , C08G64/14
CPC分类号： C07C37/14 , C08G64/14 , C07C2102/08
摘要： m-Isopropenylphenol oligomer which is useful for the production of synthetic resins such as epoxy resins is produced by polymerizing m-isopropenylphenol at a temperature of 135.degree. to 230.degree. C. using a catalytic amount of an acid catalyst in the presence or absence of a solvent, or freezing m-isopropenylphenol in the presence or absence of an acid catalyst.
摘要翻译：可用于生产合成树脂如环氧树脂的间 - 异丙烯基苯酚低聚物是通过在135℃至230℃的温度下使用催化量的酸催化剂在存在或不存在溶剂或冷冻的异丙烯基苯酚在酸催化剂存在或不存在下进行。

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