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1. 发明申请

US20070023639A1 Liquid chromatographic apparatus 审中-公开
标题翻译：液相色谱仪
公开(公告)号：US20070023639A1
公开(公告)日：2007-02-01
申请号：US10595146
申请日：2004-09-01
申请人： Kazuko Yamashita , Kiyoshi Nakai
发明人： Kazuko Yamashita , Kiyoshi Nakai
IPC分类号： H01J49/00 , B01D59/44
CPC分类号： G01N30/463 , G01N30/461 , G01N30/465 , G01N2030/8411
摘要： An apparatus has a one-dimensional analysis column for separating a sample into a plurality of components, a preparative portion for fractionating the separated components, component by component and for keeping a fractionated component, a plurality of trap columns for trapping a component supplied from the preparative portion, a two-dimensional analysis column for further separating a component trapped in the trap columns, into a plurality of components, and a path switching mechanism for effecting switching between a state in which the preparative portion is connected to a first trap column out of the plurality of trap columns and in which the two-dimensional analysis column is connected to a second trap column out of the plurality of trap columns, and a state in which the preparative portion is connected to the second trap column out of the plurality of trap columns and in which the two-dimensional analysis column is connected to the first trap column out of the plurality of trap columns.
摘要翻译：一种装置具有用于将样品分离成多个组分的一维分析柱，用于分馏分离的组分的制备部分，逐个分离并用于保持分馏的组分，多个捕集柱用于捕获从制备部分，用于进一步将陷阱中捕获的成分分离成多个成分的二维分析柱;以及路径切换机构，用于在制备部分与第一捕集塔连接的状态之间进行切换并且其中所述二维分析列与所述多个陷阱列中的第二陷阱柱连接，并且所述制备部分连接到所述多个捕集塔中的所述第二捕集塔的状态捕集塔，并且其中二维分析列连接到多个陷阱co中的第一陷阱列毕业生

2. 发明授权

US08094483B2 Semiconductor device including bit line groups 有权
标题翻译：半导体器件包括位线组
公开(公告)号：US08094483B2
公开(公告)日：2012-01-10
申请号：US12628835
申请日：2009-12-01
申请人： Kiyoshi Nakai , Shuichi Tsukada
发明人： Kiyoshi Nakai , Shuichi Tsukada
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C7/18 , G11C2207/005
摘要： A semiconductor device includes: a first read/write amplifier; a second read/write amplifier; a first group of bit lines belonging to the first read/write amplifier; a second group of bit lines belonging to the second read/write amplifier and mixed with the first group of bit lines. One of the first group of bit lines and one of the second group of bit lines are selected in parallel. A reference potential is supplied to at least one of the first non-selected bit lines adjacent to the first selected bit line selected from the first group of bit lines, and to at least one of the second non-selected bit lines adjacent to the second selected bit line selected from the first group of bit lines. At least one of remaining ones of the first and second non-selected bit lines is set into a floating state.
摘要翻译：半导体器件包括：第一读/写放大器; 第二读/写放大器; 属于第一读/写放大器的第一组位线; 属于第二读/写放大器的第二组位线，并与第一组位线混合。第一组位线之一和第二组位线之一并行选择。将参考电位提供给与从第一组位线选择的第一选定位线相邻的第一非选择位线中的至少一个以及与第二组相邻的第二非选择位线中的至少一个从第一组位线选择的选定位线。将第一和第二未选择位线中的剩余的位中的至少一个设置为浮置状态。

3. 发明授权

US07554147B2 Memory device and manufacturing method thereof 失效
标题翻译：存储器件及其制造方法
公开(公告)号：US07554147B2
公开(公告)日：2009-06-30
申请号：US11374074
申请日：2006-03-14
申请人： Isamu Asano , Tsuyoshi Kawagoe , Kiyoshi Nakai , Yukio Fuji , Kazuhiko Kajigaya
发明人： Isamu Asano , Tsuyoshi Kawagoe , Kiyoshi Nakai , Yukio Fuji , Kazuhiko Kajigaya
IPC分类号： H01L27/108
CPC分类号： G11C13/0004 , G11C11/005 , H01L27/10894 , H01L27/10897 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： A memory device in which both DRAM and phase-change memory (PCRAM) are mounted is provided with a DRAM bit line, a PCRAM bit line or a PCRAM source line formed on an conductive layer shared with the DRAM bit line, and a sense amplifier connected between the DRAM bit line and the PCRAM bit line. The memory device further has a capacitive element disposed on the upper layer of the DRAM bit line, and a phase-change element disposed on the upper layer of the PCRAM bit line. The lower electrode of the capacitive element and the lower electrode of the phase-change memory element are formed on the shared conductive layer.
摘要翻译：其中安装了DRAM和相变存储器（PCRAM）的存储器件具有形成在与DRAM位线共享的导电层上的DRAM位线，PCRAM位线或PCRAM源线，以及读出放大器连接在DRAM位线和PCRAM位线之间。存储器件还具有设置在DRAM位线的上层上的电容元件和设置在PCRAM位线的上层上的相变元件。电容元件的下电极和相变存储元件的下电极形成在共用导电层上。

4. 发明授权

US07528402B2 Electrically rewritable non-volatile memory element 有权
标题翻译：电可重写的非易失性存储元件
公开(公告)号：US07528402B2
公开(公告)日：2009-05-05
申请号：US11594879
申请日：2006-11-09
申请人： Homare Sato , Kiyoshi Nakai
发明人： Homare Sato , Kiyoshi Nakai
IPC分类号： H01L47/00
CPC分类号： H01L45/143 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/148 , H01L45/1675
摘要： A non-volatile semiconductor memory device includes a plurality of lower electrodes arranged in a matrix manner, a plurality of recording layer patterns, each being arranged on the lower electrode, that contain a phase change material, and an interlayer insulation film that is provided between the lower electrode and the recording layer pattern and that has a plurality of apertures for exposing one portion of the lower electrode. The lower electrode and the recording layer pattern are connected in each aperture. The apertures extend in the X direction in parallel to one another. The recording layer patterns extend in the Y direction in parallel to one another. Thus the aperture can be formed with higher accuracy as compared to forming an independent aperture. Accordingly, high heating efficiency can be obtained while effectively preventing occurrence of poor connection or the like.
摘要翻译：一种非易失性半导体存储器件包括以矩阵方式布置的多个下电极，多个记录层图案，每个记录层图案布置在下电极上，其中包含相变材料，以及层间绝缘膜，下电极和记录层图案，并且具有用于暴露下电极的一部分的多个孔。下电极和记录层图案连接在每个孔中。孔在X方向上彼此平行地延伸。记录层图案在Y方向上彼此平行地延伸。因此，与形成独立的孔相比，可以以更高的精度形成孔。因此，可以有效地防止连接不良等的发生而获得高的加热效率。

5. 发明授权

US07333363B2 Semiconductor storage apparatus 有权
标题翻译：半导体存储装置
公开(公告)号：US07333363B2
公开(公告)日：2008-02-19
申请号：US11409088
申请日：2006-04-24
申请人： Kiyoshi Nakai , Kazuhiko Kajigaya , Isamu Asano
发明人： Kiyoshi Nakai , Kazuhiko Kajigaya , Isamu Asano
IPC分类号： G11C14/00
CPC分类号： G11C11/005 , G11C7/20 , G11C11/4072 , G11C13/0004
摘要： Disclosed is a semiconductor storage apparatus in which two sorts of memories, that is, a volatile memory and a non-volatile memory, are mounted on one chip. Data of a DRAM memory array are saved in a corresponding area of a non-volatile memory before entry to a data retention mode or before power down and data is transferred from the area of the non-volatile memory to the DRAM memory array in exiting from the data retention mode or power up. Normal read/write access is made to the DRAM memory array, while data retention is in an area of the non-volatile memory.
摘要翻译：公开了一种半导体存储装置，其中两种存储器，即易失性存储器和非易失性存储器安装在一个芯片上。 DRAM存储器阵列的数据在进入数据保持模式之前或在断电之前被保存在非易失性存储器的相应区域中，并且数据从非易失性存储器的区域传送到DRAM存储器阵列数据保留模式或上电。对DRAM存储器阵列进行正常读/写访问，而数据保留位于非易失性存储器的区域。

6. 发明申请

US20070114510A1 Electrically rewritable non-volatile memory element 有权
标题翻译：电可重写的非易失性存储元件
公开(公告)号：US20070114510A1
公开(公告)日：2007-05-24
申请号：US11594879
申请日：2006-11-09
申请人： Homare Sato , Kiyoshi Nakai
发明人： Homare Sato , Kiyoshi Nakai
IPC分类号： H01L29/06
CPC分类号： H01L45/143 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/148 , H01L45/1675
摘要： A non-volatile semiconductor memory device includes a plurality of lower electrodes arranged in a matrix manner, a plurality of recording layer patterns, each being arranged on the lower electrode, that contain a phase change material, and an interlayer insulation film that is provided between the lower electrode and the recording layer pattern and that has a plurality of apertures for exposing one portion of the lower electrode. The lower electrode and the recording layer pattern are connected in each aperture. The apertures extend in the X direction in parallel to one another. The recording layer patterns extend in the Y direction in parallel to one another. Thus the aperture can be formed with higher accuracy as compared to forming an independent aperture. Accordingly, high heating efficiency can be obtained while effectively preventing occurrence of poor connection or the like.
摘要翻译：一种非易失性半导体存储器件包括以矩阵方式布置的多个下电极，多个记录层图案，每个记录层图案布置在下电极上，其中包含相变材料，以及层间绝缘膜，下电极和记录层图案，并且具有用于暴露下电极的一部分的多个孔。下电极和记录层图案连接在每个孔中。孔在X方向上彼此平行地延伸。记录层图案在Y方向上彼此平行地延伸。因此，与形成独立的孔相比，可以以更高的精度形成孔。因此，可以有效地防止连接不良等的发生而获得高的加热效率。

7. 发明申请

US20070063180A1 Electrically rewritable non-volatile memory element and method of manufacturing the same 审中-公开
标题翻译：电可重写非易失性存储元件及其制造方法
公开(公告)号：US20070063180A1
公开(公告)日：2007-03-22
申请号：US11516510
申请日：2006-09-07
申请人： Isamu Asano , Natsuki Sato , Kiyoshi Nakai
发明人： Isamu Asano , Natsuki Sato , Kiyoshi Nakai
IPC分类号： H01L29/04
CPC分类号： H01L27/2436 , G11C2213/52 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1273 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1675 , H01L45/1683
摘要： A non-volatile memory element includes a recording layer that includes a phase change material, a lower electrode provided in contact with the recording layer, an upper electrode provided in contact with a portion of the upper surface of the recording layer, a protective insulation film provided in contact with the other portion of the upper surface of the recording layer, and an interlayer insulation film provided on the protective insulation film. High thermal efficiency can thereby be obtained because the size of the area of contact between the recording layer and the upper electrode is reduced. Providing the protective insulation film between the interlayer insulation film and the upper surface of the recording layer makes it possible to reduce damage sustained by the recording layer during patterning of the recording layer or during formation of the through-hole for exposing a portion of the recording layer.
摘要翻译：非易失性存储元件包括记录层，其包括相变材料，与记录层接触地设置的下电极，设置成与记录层的上表面的一部分接触的上电极，保护绝缘膜设置成与记录层的上表面的另一部分接触，以及设置在保护绝缘膜上的层间绝缘膜。由于记录层和上部电极之间的接触面积的尺寸减小，因此可获得高热效率。在层间绝缘膜和记录层的上表面之间提供保护性绝缘膜使得可以减少在记录层的图案化期间或在用于曝光记录部分的通孔的形成期间记录层所承受的损伤层。

8. 发明申请

US20060250863A1 Semiconductor memory apparatus and method for writing in the memory 有权
标题翻译：用于在存储器中写入的半导体存储装置和方法
公开(公告)号：US20060250863A1
公开(公告)日：2006-11-09
申请号：US11409097
申请日：2006-04-24
申请人： Kiyoshi Nakai , Kazuhiko Kajigaya
发明人： Kiyoshi Nakai , Kazuhiko Kajigaya
IPC分类号： G11C29/00
CPC分类号： G11C13/004 , G11C13/0004 , G11C13/0033 , G11C13/0069 , G11C2013/0042 , G11C2013/0076 , G11C2213/79
摘要： A phase change memory of high compatibility with DRAM. If a cell MC0, connected to a word line WL0L, is of a low resistance, current flowing through it is higher than that flowing in a dummy cell MR0, and hence a bit line SA_B is at a potential lower than that of a bit line SA_T. This difference is amplified by a sense amplifier SA and read out. Immediately before latching cell data by the sense amplifier, an NMOS transistor MN1 is turned off to disconnect a memory cell part from a sense amplifier part. An NMOS transistor MN10 then is turned on so that data on the selected word line are all in the set state. If then writing is to be carried out, writing is carried out in the sense amplifier SA from signal lines LIO and RIO, which are I/O lines. However, writing is not performed in the memory cells. Before a precharge command is entered to precharge the word line WL0L, under, the NMOS transistor MN1 is again turned on to write reset in the cell MC0.
摘要翻译：与DRAM兼容性高的相变存储器。如果连接到字线WL 0 L的单元MC 0具有低电阻，则流过其的电流高于在虚设单元MR 0中流动的电流，因此位线SA_B处于比其低的电位的位线SA_T。该差异由读出放大器SA放大并读出。在由读出放大器锁存单元数据之前，NMOS晶体管MN 1被截止以将存储单元部分与读出放大器部分断开。然后，NMOS晶体管MN 10导通，使得所选字线上的数据都处于设置状态。如果要进行写入，则在来自作为I / O线的信号线LIO和RIO的读出放大器SA中进行写入。但是，在存储单元中不执行写入。在进行预充电指令以预充电字线WL 0 L之前，NMOS晶体管MN 1再次导通以在单元MC 0中写入复位。

9. 发明申请

US20060239097A1 Semiconductor storage apparatus 有权
公开(公告)号：US20060239097A1
公开(公告)日：2006-10-26
申请号：US11409088
申请日：2006-04-24
申请人： Kiyoshi Nakai , Kazuhiko Kajigaya , Isamu Asano
发明人： Kiyoshi Nakai , Kazuhiko Kajigaya , Isamu Asano
IPC分类号： G11C7/00
CPC分类号： G11C11/005 , G11C7/20 , G11C11/4072 , G11C13/0004
摘要： Disclosed is a semiconductor storage apparatus in which two sorts of memories, that is, a volatile memory and a non-volatile memory, are mounted on one chip. Data of a DRAM memory array are saved in a corresponding area of a non-volatile memory before entry to a data retention mode or before power down and data is transferred from the area of the non-volatile memory to the DRAM memory array in exiting from the data retention mode or power up. Normal read/write access is made to the DRAM memory array, while data retention is in an area of the non-volatile memory.

10. 发明授权

US07017027B2 Address counter control system with path switching 失效
标题翻译：具有路径切换的地址计数器控制系统
公开(公告)号：US07017027B2
公开(公告)日：2006-03-21
申请号：US10669303
申请日：2003-09-24
申请人： Tomoyuki Inaba , Kiyoshi Nakai , Hideaki Kato
发明人： Tomoyuki Inaba , Kiyoshi Nakai , Hideaki Kato
IPC分类号： G06F9/00 , G06F12/02 , G05F12/16
CPC分类号： G11C8/04
摘要： An address-counter control system includes a counter circuit, path switches, and a control circuit. The counter circuit includes a first series of address counters which corresponds to a non-contiguous region portion and second and third series of address counters which correspond to respective contiguous region portions and which are located at two opposite ends of the first series of address counters. The path switches are provided at connection paths between the second and the third series of address counters. The path switches disconnect the first series of address counters and directly connect the second and third series of address counters or disconnect the direct connection between the second and third series of address counters and connect the first series of address counters to and between the second and the third series of address counters. The control circuit control the path switches.
摘要翻译：地址计数器控制系统包括计数器电路，路径开关和控制电路。计数器电路包括对应于不连续区域部分的第一系列地址计数器和对应于相应连续区域部分并且位于第一系列地址计数器的两个相对端处的第二和第三系列地址计数器。在第二和第三系列地址计数器之间的连接路径处提供路径切换。路径开关断开第一系列地址计数器，并直接连接第二和第三系列地址计数器，或断开第二和第三系列地址计数器之间的直接连接，并将第一系列地址计数器连接到第二和第二第三系列地址柜台。控制电路控制路径开关。

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