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51. 发明申请

US20050142707A1 Method of crystallizing/activating polysilicon layer and method of fabricating thin film transistor having the same polysilicon layer 有权
标题翻译：多晶硅层的结晶/活化方法和制造具有相同多晶硅层的薄膜晶体管的方法
公开(公告)号：US20050142707A1
公开(公告)日：2005-06-30
申请号：US10909457
申请日：2004-08-03
申请人： Yong Kim , Choong Sohn , Jin Lee
发明人： Yong Kim , Choong Sohn , Jin Lee
IPC分类号： H01L29/786 , H01L21/20 , H01L21/268 , H01L21/336 , H01L29/423 , H01L21/00 , H01L21/84
CPC分类号： H01L21/02675 , H01L21/02532 , H01L21/02595 , H01L21/2026 , H01L21/268 , H01L29/42384 , H01L29/66757
摘要： Provided is a method of crystallizing/activating a polysilicon layer and a method of fabricating a thin film transistor having the same polysilicon layer, in which when a gate material is patterned to form a gate electrode and define source/drain regions, the gate material on source/drain regions partially remains, so that crystallizing and activating processes are performed at the same time.
摘要翻译：提供了一种使多晶硅层结晶/活化的方法和制造具有相同多晶硅层的薄膜晶体管的方法，其中当栅极材料被图案化以形成栅电极并限定源极/漏极区域时，栅极材料在源极/漏极区域部分保留，从而同时进行结晶和激活过程。

52. 发明申请

US20050128680A1 Method of manufacturing multilayered ceramic capacitor by spin coating and multilayered ceramic capacitor 失效
标题翻译：通过旋涂和多层陶瓷电容器制造多层陶瓷电容器的方法
公开(公告)号：US20050128680A1
公开(公告)日：2005-06-16
申请号：US11011092
申请日：2004-12-15
申请人： Hyo Shin , Seung Ra , Yong Kim , Hyoung Kim , Ho Choo , Jung Lee
发明人： Hyo Shin , Seung Ra , Yong Kim , Hyoung Kim , Ho Choo , Jung Lee
IPC分类号： H01G4/12 , C04B35/468 , H01G4/30 , H01G9/00 , H01G13/00 , H01G13/04
CPC分类号： H01G4/30 , H01G4/1227 , Y10T29/417 , Y10T29/43 , Y10T29/435
摘要： Disclosed herein is a method of manufacturing a multilayered ceramic capacitor by a spin coating process, and a multilayered ceramic capacitor obtained by the above method. The method of the current invention provides a plurality of dielectric layers formed by spin coating, in which the process of coating the dielectric layer and the process of printing the inner electrode can be provided as a single process. Therefore, the thickness of the dielectric layer is easily controlled while the dielectric layer is formed to be thin. Further, since the dielectric layers and the inner electrodes are formed successively, the processes of separating and layering the dielectric layers, and the process of compressing the ceramic multilayered body can be omitted. Thereby, the ceramic multilayered body need not be compressed, and thus, a pillowing phenomenon does not occur in the multilayered ceramic capacitor.
摘要翻译：本文公开了通过旋涂工艺制造多层陶瓷电容器的方法和通过上述方法获得的多层陶瓷电容器。本发明的方法提供了通过旋涂形成的多个电介质层，其中涂覆介电层的过程和印刷内电极的过程可以作为单一工艺提供。因此，在电介质层形成得较薄的同时容易控制电介质层的厚度。此外，由于电介质层和内部电极依次形成，所以可以省略介电层的分离和分层工艺以及压缩陶瓷多层体的工艺。因此，陶瓷多层体不需要被压缩，因此在多层陶瓷电容器中不会发生卷绕现象。

53. 发明申请

US20050121712A1 Flash memory cell and method of manufacturing the same and programming/erasing/reading method of flash memory cell 审中-公开
标题翻译：闪存单元及其制造方法和闪存单元的编程/擦除/读取方法
公开(公告)号：US20050121712A1
公开(公告)日：2005-06-09
申请号：US11040969
申请日：2005-01-21
申请人： Sung Park , Young You , Yong Kim , Yoo Jeon
发明人： Sung Park , Young You , Yong Kim , Yoo Jeon
IPC分类号： G11C11/56 , G11C16/02 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/336 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/11521 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0458 , G11C2211/5612 , H01L27/115 , H01L29/7887
摘要： Disclosed is a flash memory cell and method of manufacturing the same, and programming/erasing/reading method thereof. The flash memory cell comprises a first tunnel oxide film formed at a given region of a semiconductor substrate, a first floating gate formed on the first tunnel oxide film, a second tunnel oxide film formed over the semiconductor substrate and along one sidewall of the first floating gate, a second floating g ate isolated from the first floating gate while contacting the second tunnel oxide film, a dielectric film formed on the first floating gate and the second floating gate, a control gate formed on the dielectric film, a first junction region formed in the semiconductor substrate below one side of the second tunnel oxide film, and a second junction region formed in the semiconductor substrate below one side of the first tunnel oxide film. Therefore, the present invention can implement 2-bit cell or 3-bit cell of a high density using the existing process technology. Further, it can reduce the manufacture cost and implement a high-integrated flash memory cell that is advantageous than a conventional flash memory cell in view of charge storage/retention as well as programming time.
摘要翻译：公开了一种闪存单元及其制造方法及其编程/擦除/读取方法。闪速存储单元包括形成在半导体衬底的给定区域的第一隧道氧化物膜，形成在第一隧道氧化物膜上的第一浮栅，形成在半导体衬底上并沿着第一浮置区的一个侧壁的第二隧道氧化膜栅极，与第一沟槽氧化膜接触时与第一浮栅隔离的第二浮置栅极，形成在第一浮置栅极和第二浮置栅极上的电介质膜，形成在电介质膜上的控制栅极，形成的第一结区域在第二隧道氧化膜的一侧以下的半导体衬底中形成的第二结区，以及形成在第一隧道氧化膜的一侧以下的半导体衬底中的第二结区。因此，本发明可以使用现有的工艺技术来实现高密度的2比特单元或3比特单元。此外，鉴于电荷存储/保持以及编程时间，它可以降低制造成本并实现比传统闪存单元有利的高集成闪存单元。

54. 发明申请

US20050056306A1 Apparatus and method for treating surfaces of semiconductor wafers using ozone 审中-公开
标题翻译：使用臭氧处理半导体晶片表面的设备和方法
公开(公告)号：US20050056306A1
公开(公告)日：2005-03-17
申请号：US10902643
申请日：2004-07-29
申请人： In Jeong , Yong Kim , Jungyup Kim
发明人： In Jeong , Yong Kim , Jungyup Kim
IPC分类号： B08B3/00 , B08B3/02 , B08B3/08 , B08B3/12 , B08B7/04 , H01L20060101 , H01L21/00 , H01L21/302 , H01L21/306 , H01L21/31 , H01L21/316 , H01L21/461 , H01L21/469
CPC分类号： H01L21/02046 , B08B3/02 , B08B3/08 , B08B2203/005 , H01L21/02238 , H01L21/31662 , H01L21/67051
摘要： An apparatus and method for treating surfaces of semiconductor wafers with a reactive gas, such as ozone, utilizes streams of gaseous material ejected from a gas nozzle structure to create depressions on or holes through a boundary layer of processing fluid formed on a semiconductor wafer surface to increase the amount of reactive gas that reaches the wafer surface through the boundary layer. The apparatus and method may be used to clean a semiconductor wafer surface and/or grow an oxide layer on the wafer surface by oxidation.
摘要翻译：用诸如臭氧的反应性气体处理半导体晶片的表面的设备和方法利用从气体喷嘴结构喷出的气态物流，以在半导体晶片表面上形成的处理流体的边界层上形成凹坑，增加通过边界层到达晶片表面的反应气体的量。该设备和方法可用于通过氧化来清洁半导体晶片表面和/或在晶片表面上生长氧化物层。

55. 发明申请

US20050024566A1 Apparatus and method for maintaining uniform contrast in liquid crystal displays 审中-公开
标题翻译：用于在液晶显示器中保持均匀对比度的装置和方法
公开(公告)号：US20050024566A1
公开(公告)日：2005-02-03
申请号：US10902354
申请日：2004-07-28
申请人： Donald MacIntyre , John MacIntyre , Yong Kim
发明人： Donald MacIntyre , John MacIntyre , Yong Kim
IPC分类号： G02F1/1333 , G02F1/1335
CPC分类号： G02F1/133528 , G02F1/1333
摘要： A liquid crystal display assembly contains a liquid crystal in a chamber formed between two plates and enclosed by a surrounding seal. Polarizer layers are attached to one or both plates, wherein the polarizer layers extend to the edges of the one or both plates. A uniform thickness adhesive layer is applied to the polarizer layers and additional layers are fixed by the adhesive to the assembly as required by the end purpose of the display. Curing of the uniform thickness adhesive layer results in uniform stress throughout the adhesive layer with resulting reduction of display assembly distortion.
摘要翻译：液晶显示组件包含在两个板之间形成并由周围密封封闭的室中的液晶。偏振器层附接到一个或两个板，其中偏振器层延伸到一个或两个板的边缘。将均匀的厚度粘合剂层施加到偏振器层，并且根据显示器的最终目的，附加层通过粘合剂固定到组件上。均匀厚度粘合剂层的固化导致整个粘合剂层的均匀应力，导致显示组件变形的减少。

56. 发明授权

US06351420B1 Voltage boost level clamping circuit for a flash memory 有权
标题翻译：用于闪存的电压升压电平钳位电路
公开(公告)号：US06351420B1
公开(公告)日：2002-02-26
申请号：US09595519
申请日：2000-06-16
申请人： Takao Akaogi , Ali K. Al-Shamma , Lee Edward Cleveland , Yong Kim , Jin-Lien Lin , Boon Tang Teh , Kendra Nguyen
发明人： Takao Akaogi , Ali K. Al-Shamma , Lee Edward Cleveland , Yong Kim , Jin-Lien Lin , Boon Tang Teh , Kendra Nguyen
IPC分类号： G11C700
CPC分类号： G11C8/08 , G11C5/145 , G11C16/12 , G11C16/30
摘要： A voltage boost circuit (111) for a flash memory (100) includes a boosting circuit (110), which is capable of boosting a portion of a power supply voltage (VCC) of the flash memory to a word line voltage level adequate for accessing a core cell in a core cell array (102) of the memory. The voltage boost circuit further includes a balancing or clamping circuit (112) for providing a nonzero adjustment voltage (VCL) to the boosting circuit to reduce the portion of the supply voltage that is available for boosting by the boosting circuit when the power supply voltage exceeds a certain value.
摘要翻译：用于闪存（100）的升压电路（111）包括升压电路（110），其能够将闪存的电源电压（VCC）的一部分升压到足以访问的字线电压电平存储器的核心单元阵列（102）中的核心单元。升压电路还包括用于向升压电路提供非零调节电压（VCL）的平衡或钳位电路（112），以在电源电压超过时减小升压电路可用于升压的电源电压部分一定的价值。

57. 外观设计

USD434852S Face rejuvenator 失效
公开(公告)号：USD434852S
公开(公告)日：2000-12-05
申请号：US111205
申请日：1999-09-24
申请人： Yong Kim
设计人： Yong Kim

58. 发明授权

US08553709B2 Method and system for an asymmetric PHY operation for ethernet A/V bridging and ethernet A/V bridging extensions 有权
标题翻译：用于以太网A / V桥接和以太网A / V桥接扩展的非对称PHY操作的方法和系统
公开(公告)号：US08553709B2
公开(公告)日：2013-10-08
申请号：US13441647
申请日：2012-04-06
申请人： Wael William Diab , Yong Kim , Scott Powell
发明人： Wael William Diab , Yong Kim , Scott Powell
IPC分类号： H04L12/56
CPC分类号： H04N21/43632 , G09G5/006 , G09G2370/10 , H04L12/2805 , H04L12/2816 , H04L2012/2849 , H04N5/85 , H04N7/106 , H04N9/8042 , H04N19/172 , H04N19/176 , H04N19/61 , H04N21/43615 , H04N21/6373 , H04N21/64322 , Y02D30/32
摘要： Signals may be communicated with A/V Bridging services between an upstream link partner and a down stream link partner, each comprising an asymmetric multi-rate Ethernet physical layer (PHY). High bandwidth A/V signals may be transmitted from the upstream link partner and low bandwidth signals may be transmitted from the downstream link partner. One or more of a time stamp, a traffic class and/or a destination address may be utilized in generating PDUs as well as data rate request and a resource reservation messages via the asymmetric Ethernet PHY. The receiving link partner may register for deliver of the PDUs. An aggregate communication rate may be distributed evenly or unevenly among one or more links for transmission and aggregated upon reception via asymmetric multi-rate Ethernet PHY operations. Compressed, uncompressed, encrypted and/or unencrypted signals may be handled. Signal processing may comprise echo cancellation, cross talk cancellation, forward error checking and equalization.
摘要翻译：信号可以与上游链路伙伴和下行链路伙伴之间的A / V桥接服务进行通信，每个链路伙伴包括非对称多速率以太网物理层（PHY）。可以从上游链路伙伴发送高带宽A / V信号，并且可以从下游链路伙伴发送低带宽信号。时间戳，流量类别和/或目的地地址中的一个或多个可以用于经由非对称以太网PHY产生PDU以及数据速率请求和资源预留消息。接收链路伙伴可以注册传送PDU。聚合通信速率可以在一个或多个链路中均匀或不均匀地分布以进行传输，并且在通过非对称多速率以太网PHY操作接收时聚合。可以处理压缩，未压缩，加密和/或未加密的信号。信号处理可以包括回波消除，串扰消除，前向纠错和均衡。

59. 发明授权

US08179910B2 Method and system for an asymmetric PHY operation for ethernet A/V bridging and ethernet A/V bridging extensions 有权
标题翻译：用于以太网A / V桥接和以太网A / V桥接扩展的非对称PHY操作的方法和系统
公开(公告)号：US08179910B2
公开(公告)日：2012-05-15
申请号：US12942188
申请日：2010-11-09
申请人： Wael William Diab , Yong Kim , Scott Powell
发明人： Wael William Diab , Yong Kim , Scott Powell
IPC分类号： H04L12/56
CPC分类号： H04N21/43632 , G09G5/006 , G09G2370/10 , H04L12/2805 , H04L12/2816 , H04L2012/2849 , H04N5/85 , H04N7/106 , H04N9/8042 , H04N19/172 , H04N19/176 , H04N19/61 , H04N21/43615 , H04N21/6373 , H04N21/64322 , Y02D30/32
摘要： A network device comprising asymmetric, multi-rate, Ethernet MAC and asymmetric, multi-rate, Ethernet PHY communicates signals via a network utilizing A/V bridging services. Higher bandwidth A/V signals are communicated and lower bandwidth signals are received or vice versa. Signals are communicated based on a plurality of different Ethernet protocols and/or data rates. Signals may be communicated based on 10GBASE-T in a first direction and based on a lower rate Ethernet protocol in a second direction. Extended range mode may be utilized. PDUs comprise time stamps, traffic class designations and/or destination addresses. Data rate requests, resource reservation messages and/or registration for delivery of PDUs may be communicated. Time stamps enable end to end transport within a specified latency target. Video signals may be compressed, uncompressed, encrypted, unencrypted and/or formatted for a video display interface.
摘要翻译：包括不对称，多速率以太网MAC和非对称，多速率以太网PHY的网络设备通过使用A / V桥接服务的网络来传送信号。传送更高带宽的A / V信号，接收较低带宽信号，反之亦然。基于多个不同的以太网协议和/或数据速率来传送信号。信号可以在第一方向上基于10GBASE-T传送，并且在第二方向上基于较低速率的以太网协议。可以使用扩展范围模式。 PDU包括时间戳，流量类别名称和/或目的地址。可以传送数据速率请求，资源预留消息和/或用于传送PDU的注册。时间戳可以在指定的延迟目标内实现端到端传输。视频信号可以被压缩，未压缩，加密，未加密和/或格式化用于视频显示接口。

60. 发明授权

US08068479B2 System and method for hardware acceleration in a hybrid wired/wireless local area network 有权
标题翻译：混合有线/无线局域网硬件加速的系统和方法
公开(公告)号：US08068479B2
公开(公告)日：2011-11-29
申请号：US10657942
申请日：2003-09-09
申请人： Richard Martin , Yong Kim
发明人： Richard Martin , Yong Kim
IPC分类号： H04L12/28 , H04W4/00
CPC分类号： H04W24/02 , G01S5/0252 , H04L1/1607 , H04L12/2856 , H04L12/2872 , H04L41/08 , H04L47/125 , H04L47/14 , H04L47/15 , H04L47/24 , H04L47/2408 , H04L47/70 , H04L47/767 , H04L47/785 , H04L47/805 , H04L47/824 , H04L47/825 , H04L47/828 , H04L49/205 , H04L49/351 , H04L49/602 , H04L63/0272 , H04L63/08 , H04L63/0838 , H04L63/102 , H04L63/104 , H04L67/14 , H04L67/18 , H04L67/327 , H04L69/14 , H04L69/18 , H04L69/32 , H04L69/324 , H04L69/329 , H04L69/40 , H04W16/16
摘要： Aspects of the invention may be found in a system and method for hardware acceleration in a hybrid wired/wireless local area network. In according with various embodiments of the invention, hardware acceleration may comprise creating at least one policy to be distributed among one or more of a plurality of access point groups. At least one policy may be associated with a particular one of the access point groups. The associated policy may be identified and distributed to one or more access points in an access point group. The distribution of the policy may be conditioned on the occurrence of an event. An identified policy may be distributed to a particular access point group upon occurrence of the event.
摘要翻译：可以在用于混合有线/无线局域网中的硬件加速的系统和方法中找到本发明的方面。根据本发明的各种实施例，硬件加速可以包括创建要分布在多个接入点组中的一个或多个中的至少一个策略。至少一个策略可以与特定的一个接入点组相关联。相关联的策略可以被识别并分发到接入点组中的一个或多个接入点。政策的分配可能是事件发生的条件。在发生事件时，识别的策略可以被分发到特定接入点组。

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