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51. 发明授权

US06856548B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US06856548B2
公开(公告)日：2005-02-15
申请号：US10756267
申请日：2004-01-14
申请人： Toru Tanzawa , Tadayuki Taura , Masao Kuriyama
发明人： Toru Tanzawa , Tadayuki Taura , Masao Kuriyama
IPC分类号： G11C16/00 , G11C16/30 , G11C16/34 , G11C11/40
CPC分类号： G11C16/107 , G11C16/30 , G11C16/3409 , G11C16/344 , G11C16/3445 , G11C16/3459 , G11C16/3477
摘要： A potential generating circuit generates two types of erase verify threshold values EVT1 and EVT2. These values satisfy the relationship of EVT2=EVT1+(OEVT−EVTL). OEVT is an over-erase verify threshold value. While the erase verify threshold value is set at EVT2, the lower limit of a threshold voltage distribution after data erase is higher than OEVT. EVTL is the lower limit of the threshold voltage distribution after data erase while the erase verify threshold value is set at EVT1 and is lower than OEVT. The erase verify threshold values EVT1 and EVT2 are switched according to an operation mode. During a write/erase test, for example, the erase verify threshold value is set at EVT2. On the other hand, during the normal operation, the erase verify threshold value is set at EVT1.
摘要翻译：电位产生电路产生两种类型的擦除验证阈值EVT1和EVT2。这些值满足EVT2 = EVT1 +（OEVT-EVTL）的关系。 OEVT是过擦除验证阈值。当擦除验证阈值设定为EVT2时，数据擦除后阈值电压分布的下限高于OEVT。 EVTL是数据擦除后的阈值电压分布的下限，擦除验证阈值设定为EVT1，低于OEVT。根据操作模式切换擦除验证阈值EVT1和EVT2。在写入/擦除测试期间，例如，擦除验证阈值被设置为EVT2。另一方面，在正常操作期间，将擦除验证阈值设置为EVT1。

52. 发明授权

US06700817B2 Semiconductor integrated circuit device with operation/function setting information memory 失效
标题翻译：具有操作/功能设定信息存储器的半导体集成电路器件
公开(公告)号：US06700817B2
公开(公告)日：2004-03-02
申请号：US10265728
申请日：2002-10-08
申请人： Shigeru Atsumi , Masao Kuriyama , Akira Umezawa , Hironori Banba , Tadayuki Taura , Hidetoshi Saito
发明人： Shigeru Atsumi , Masao Kuriyama , Akira Umezawa , Hironori Banba , Tadayuki Taura , Hidetoshi Saito
IPC分类号： G11C1604
CPC分类号： G11C5/143 , G11C5/14 , G11C7/1045 , G11C16/26 , G11C16/30
摘要： A semiconductor integrated circuit device includes a nonvolatile memory cell, a source of the cell receiving a ground potential, and a gate of the cell receiving a first control signal; a transistor, a source of the transistor receiving a drain potential of the cell, and a gate of the transistor receiving a second control signal; and a controller. The controller receives a third control signal generated upon detection of power-on and outputs the first and second control signals. A potential of the first control signal changes from the ground potential to a potential different from the ground potential, which is maintained during a first period of time, and a potential of the second control signal changes from the ground potential to a potential different from the ground potential, which is maintained during a second period of time.
摘要翻译：半导体集成电路装置包括：非易失性存储单元，接收地电位的单元的源极和接收第一控制信号的单元的栅极; 晶体管，晶体管的源极，接收所述单元的漏极电位，以及所述晶体管的栅极接收第二控制信号; 和控制器。控制器接收在检测到电源接通时产生的第三控制信号，并输出第一和第二控制信号。第一控制信号的电位从接地电位变化到在第一时间段期间保持的接地电位不同的电位，并且第二控制信号的电位从地电势变为不同于地电位，在第二段时间内保持。

53. 发明授权

US06373325B1 Semiconductor device with a charge pumping circuit 失效
标题翻译：具有电荷泵电路的半导体器件
公开(公告)号：US06373325B1
公开(公告)日：2002-04-16
申请号：US09523729
申请日：2000-03-13
申请人： Masao Kuriyama
发明人： Masao Kuriyama
IPC分类号： B05F316
CPC分类号： G11C5/145 , G11C16/30
摘要： A semiconductor device comprises a charge pumping circuit including plural stages of circuit portions connected in series. Each circuit portion has a transistor having a drain and gate connected to each other and a capacitor having a connection node at which one electrode of the capacitor is connected to the drain of the transistor in such a way that potentials to be applied to adjoining connection nodes of individual capacitors alternately attain a high level and a low level when the charge-pumping circuit is operating. When the charge-pumping circuit stops operating, each of the potentials of the connection nodes of the individual capacitors is fixed at a high level if an output voltage of the charge-pumping circuit is positive.
摘要翻译：半导体器件包括电荷泵浦电路，其包括串联连接的多级电路部分。每个电路部分具有一个具有彼此连接的漏极和栅极的晶体管，以及具有连接节点的电容器，电容器的一个电极以这样的方式连接到晶体管的漏极，使得施加到相邻连接节点的电位的单个电容器在电荷泵电路工作时交替地达到高电平和低电平。当电荷泵浦电路停止工作时，如果电荷泵浦电路的输出电压为正，各个电容器的连接节点的每个电位固定在高电平。

54. 发明授权

US06320428B1 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US06320428B1
公开(公告)日：2001-11-20
申请号：US09527582
申请日：2000-03-17
申请人： Shigeru Atsumi , Masao Kuriyama , Akira Umezawa , Hironori Banba , Tadayuki Taura , Hidetoshi Saito
发明人： Shigeru Atsumi , Masao Kuriyama , Akira Umezawa , Hironori Banba , Tadayuki Taura , Hidetoshi Saito
IPC分类号： H03K522
CPC分类号： G11C5/143 , G11C5/14 , G11C7/1045 , G11C16/26 , G11C16/30
摘要： A semiconductor integrated circuit device has a data storage section for storing mode setting data corresponding to products of a plurality of types, redundancy data, and so on. The redundancy storage section is made up of a nonvolatile transistor for storing the mode setting data corresponding to the products, the redundancy data, etc., a latch circuit for latching data read out from the nonvolatile transistor and generating a mode signal, and a transmission gate for transmitting the data from read out from the nonvolatile transistor to the latch circuit. The semiconductor integrated circuit device also has an internal voltage generator for generating an internal voltage. This internal voltage is used as the power supply voltage of the data storage section.
摘要翻译：半导体集成电路装置具有用于存储对应于多种类型，冗余数据等的产品的模式设置数据的数据存储部分。冗余存储部分由用于存储对应于产品，冗余数据等的模式设置数据的非易失性晶体管，用于锁存从非易失性晶体管读出的数据并产生模式信号的锁存电路，以及传输用于将从非易失性晶体管读出的数据发送到锁存电路。半导体集成电路器件还具有用于产生内部电压的内部电压发生器。该内部电压用作数据存储部分的电源电压。

55. 发明授权

US06160738A Nonvolatile semiconductor memory system 失效
标题翻译：非易失性半导体存储器系统
公开(公告)号：US06160738A
公开(公告)日：2000-12-12
申请号：US181404
申请日：1994-01-13
申请人： Shigeru Atsumi , Hironori Banba , Masao Kuriyama
发明人： Shigeru Atsumi , Hironori Banba , Masao Kuriyama
IPC分类号： G11C17/00 , G11C16/02 , G11C16/34 , G11C16/06
CPC分类号： G11C16/3431 , G11C16/3418
摘要： A nonvolatile semiconductor memory system is provided with a nonvolatile memory cell array divided into erase blocks data and refresh blocks, and a flag cell array including a plurality of nonvolatile flag cells each of which corresponds to one of the refresh blocks and stores data representing the refresh status of the corresponding refresh block.
摘要翻译：非易失性半导体存储器系统设置有被划分为擦除块数据和刷新块的非易失性存储单元阵列，以及包括多个非易失性标志单元的标志单元阵列，每个非易失性标志单元对应于一个刷新块，并存储表示刷新的数据相应刷新块的状态。

56. 发明授权

US6052313A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US6052313A
公开(公告)日：2000-04-18
申请号：US030915
申请日：1998-02-26
申请人： Shigeru Atsumi , Masao Kuriyama , Akira Umezawa , Hironori Banba , Tadayuki Taura , Hidetoshi Saito
发明人： Shigeru Atsumi , Masao Kuriyama , Akira Umezawa , Hironori Banba , Tadayuki Taura , Hidetoshi Saito
IPC分类号： G11C5/00 , G11C5/14 , G11C16/04 , H01L29/78 , H03K5/153 , H03K5/22
CPC分类号： G11C5/143 , G11C16/30 , G11C7/1045 , G11C16/26 , G11C5/14
摘要： A semiconductor integrated circuit device has a data storage section for storing mode setting data corresponding to products of a plurality of types, redundancy data, and so on. The redundancy storage section is made up of a nonvolatile transistor for storing the mode setting data corresponding to the products, the redundancy data, etc., a latch circuit for latching data read out from the nonvolatile transistor and generating a mode signal, and a transmission gate for transmitting the data from read out from the nonvolatile transistor to the latch circuit. The semiconductor integrated circuit device also has an internal voltage generator for generating an internal voltage. This internal voltage is used as the power supply voltage of the data storage section.
摘要翻译：半导体集成电路装置具有用于存储对应于多种类型，冗余数据等的产品的模式设置数据的数据存储部分。冗余存储部分由用于存储对应于产品，冗余数据等的模式设置数据的非易失性晶体管，用于锁存从非易失性晶体管读出的数据并产生模式信号的锁存电路，以及传输用于将从非易失性晶体管读出的数据发送到锁存电路。半导体集成电路器件还具有用于产生内部电压的内部电压发生器。该内部电压用作数据存储部分的电源电压。

57. 发明授权

US5559737A Nonvolatile semiconductor memory capable of simultaneously equalizing bit lines and sense lines 失效
标题翻译：非易失性半导体存储器能够同时均衡位线和感测线
公开(公告)号：US5559737A
公开(公告)日：1996-09-24
申请号：US338827
申请日：1994-11-10
申请人： Sumio Tanaka , Shigeru Atsumi , Masao Kuriyama
发明人： Sumio Tanaka , Shigeru Atsumi , Masao Kuriyama
IPC分类号： G11C17/00 , G11C7/12 , G11C16/06 , G11C16/28
CPC分类号： G11C7/12 , G11C16/28
摘要： In a nonvolatile semiconductor memory having a two-stage sense read circuit using a level shift circuit and a single-end sense amplifier, relationships of sizes of a main memory cell bit line charge transistor, a main memory cell bit line transfer gate transistor, a main memory cell bit line load transistor, a dummy cell bit line charge transistor, a dummy cell bit line transfer gate transistor, and a dummy cell bit line load transistor are set to simultaneously satisfy conditions for equalizing a bit line and a dummy cell bit line and conditions for equalizing a sense line and a dummy cell sense line. Therefore, the potentials of the bit line and the dummy cell bit line and the potentials of the sense line and the dummy cell sense line can be simultaneously equalized, and a high-speed read operation can be achieved.
摘要翻译：在具有使用电平移位电路和单端读出放大器的两级读出电路的非易失性半导体存储器中，主存储单元位线电荷晶体管，主存储单元位线传输栅极晶体管，主存储单元位线负载晶体管，虚设单元位线充电晶体管，虚设单元位线传输门晶体管和虚设单元位线负载晶体管被设置为同时满足用于对位线和虚设单元位线进行均衡的条件以及用于均衡感测线和虚拟细胞感测线的条件。因此，可以同时均衡位线和虚设单元位线的电位和感测线和虚设单元感测线的电位，并且可以实现高速读取操作。

58. 发明授权

US5296801A Bias voltage generating circuit 失效
标题翻译：偏置电压发生电路
公开(公告)号：US5296801A
公开(公告)日：1994-03-22
申请号：US921098
申请日：1992-07-29
申请人： Nobuaki Ohtsuka , Sumio Tanaka , Masao Kuriyama
发明人： Nobuaki Ohtsuka , Sumio Tanaka , Masao Kuriyama
IPC分类号： G11C16/30 , G05F3/16
CPC分类号： G11C16/30
摘要： A bias voltage generating circuit supplies a bias voltage to a memory's bit lines. One end of a first transistor is connected to a first power supply. The first transistor conducts in response to a control signal. A second transistor is connected to another end of the first transistor. Another end of the second transistor and a gate of the second transistor are connected to an output node. One end of a third transistor and a gate connected to the output node. One end of a fourth transistor and a gate are connected to a second end of the third transistor. A second end of the fourth transistor is connected to a second power supply. One end of a fifth transistor is connected to the first power supply. The fifth transistor also conducts in response to the control signal. A sixth transistor is connected to a second end of the fifth transistor. A second end of the sixth transistor is connected to the output node and the gate of the sixth transistor is connected to a potential source. A seventh transistor is connected to the output node. A second end of the seventh transistor is connected to a ground potential. The seventh transistor also conducts in response to the control signal. The output node outputs a bias voltage to the bit lines when the control signal is activated, and is grounded through the seventh transistor when the control signal is non-activated.
摘要翻译：偏置电压产生电路将偏置电压提供给存储器的位线。第一晶体管的一端连接到第一电源。第一晶体管响应于控制信号而导通。第二晶体管连接到第一晶体管的另一端。第二晶体管的另一端和第二晶体管的栅极连接到输出节点。第三晶体管的一端和连接到输出节点的栅极。第四晶体管和栅极的一端连接到第三晶体管的第二端。第四晶体管的第二端连接到第二电源。第五晶体管的一端连接到第一电源。第五晶体管也响应于控制信号而导通。第六晶体管连接到第五晶体管的第二端。第六晶体管的第二端连接到输出节点，第六晶体管的栅极连接到电位源。第七晶体管连接到输出节点。第七晶体管的第二端连接到地电位。第七晶体管也响应于控制信号而导通。当控制信号被激活时，输出节点向位线输出偏置电压，并且当控制信号不被激活时，输出节点通过第七晶体管接地。

59. 发明授权

US5262919A Semiconductor memory device including programming circuitry 失效
标题翻译：半导体存储器件包括编程电路
公开(公告)号：US5262919A
公开(公告)日：1993-11-16
申请号：US709825
申请日：1991-06-04
申请人： Masao Kuriyama , Shigeru Atsumi , Junichi Miyamoto
发明人： Masao Kuriyama , Shigeru Atsumi , Junichi Miyamoto
IPC分类号： G11C17/00 , G11C16/02 , G11C16/10 , G11C16/32 , H01L21/8247 , H01L27/10 , H01L29/788 , H01L29/792 , G11C7/00
CPC分类号： G11C16/32 , G11C16/10
摘要： A data input circuit outputs input data in accordance with a write enable signal. A program control circuit generates different data items on the basis of the input data output from the data input circuit and the write enable signal, and turns programming transistors on/off in accordance with the different data items as generated. The programming transistors are connected to a pair of cell transistors forming an EPROM cells, and program into these cell transistors the different data items generated by the write control circuit. A timing circuit delays the timing at which the write enable signal is supplied to the write control circuit, until the input data is established within the data input circuit.

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