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51. 发明授权

US07366881B2 Method and apparatus for staggering execution of an instruction 有权
标题翻译：用于交错执行指令的方法和装置
公开(公告)号：US07366881B2
公开(公告)日：2008-04-29
申请号：US11103702
申请日：2005-04-11
申请人： Patrice Roussel , Glenn J. Hinton , Shreekant S. Thakkar , Brent R. Boswell , Karol F. Menezes
发明人： Patrice Roussel , Glenn J. Hinton , Shreekant S. Thakkar , Brent R. Boswell , Karol F. Menezes
IPC分类号： G06F9/30
CPC分类号： G06F9/30014 , G06F9/30036 , G06F9/3826 , G06F9/3828 , G06F9/3875 , G06F9/3885
摘要： A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.
摘要翻译：公开了一种用于交错执行指令的方法和装置。根据本发明的一个实施例，接收单个宏指令，其中单个宏指令指定至少两个逻辑寄存器，并且其中两个逻辑寄存器分别存储具有相应数据元素的第一和第二压缩数据操作数。然后，使用相同电路，在来自所述第一和第二打包数据操作数的第一和第二多个相应数据元素上独立地执行由单个宏指令指定的操作，以独立地生成第一和第二多个结果数据元素。第一和第二多个结果数据元素作为第三打包数据操作数存储在单个逻辑寄存器中。

52. 发明授权

US06925553B2 Staggering execution of a single packed data instruction using the same circuit 失效
标题翻译：使用相同电路的单个打包数据指令的交错执行
公开(公告)号：US06925553B2
公开(公告)日：2005-08-02
申请号：US10689291
申请日：2003-10-20
申请人： Patrice Roussel , Glenn J. Hinton , Shreekant S. Thakkar , Brent R. Boswell , Karol F. Menezes
发明人： Patrice Roussel , Glenn J. Hinton , Shreekant S. Thakkar , Brent R. Boswell , Karol F. Menezes
IPC分类号： G06F9/302 , G06F15/00
CPC分类号： G06F9/30014 , G06F9/30036 , G06F9/3826 , G06F9/3828 , G06F9/3875 , G06F9/3885
摘要： A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a macro instruction specifying an operation, and specifying a first and a second data operand in first and second registers, respectively, is received. The macro instruction is then split into a first micro instruction and a second micro instruction, the first micro instruction specifying the operation on a first corresponding segment including a first portion of the first data operand and a first portion of the second data operand, and the second micro instruction specifying the operation on a second corresponding segment including a second portion of the first data operand and a second portion of the second data operand. The first and second micro instructions are then executed.
摘要翻译：公开了一种用于交错执行指令的方法和装置。根据本发明的一个实施例，接收指定操作并分别在第一和第二寄存器中指定第一和第二数据操作数的宏指令。然后，宏指令被分割成第一微指令和第二微指令，第一微指令指定在包括第一数据操作数的第一部分和第二数据操作数的第一部分的第一对应段上的操作，以及指定在包括第一数据操作数的第二部分和第二数据操作数的第二部分的第二对应段上的操作的第二微指令。然后执行第一和第二微指令。

53. 发明授权

US06721866B2 Unaligned memory operands 有权
标题翻译：未对齐的内存操作数
公开(公告)号：US06721866B2
公开(公告)日：2004-04-13
申请号：US10029367
申请日：2001-12-21
申请人： Patrice Roussel , Eric Sprangle , Glenn J. Hinton
发明人： Patrice Roussel , Eric Sprangle , Glenn J. Hinton
IPC分类号： G06F1204
CPC分类号： G06F9/30043
摘要： A method of obtaining an operand from a memory device includes reading a first operand from a first location in a memory device, the first operand including part of the operand specified by an instruction, shifting the first operand by a first shift amount, reading a second data operand from the memory device, the second operand having part of the operand specified by the instruction, shifting the second operand by a second shift amount, and combining the first shifted data entry and the second shifted data entry to produce an aligned operand, wherein shifting the first operand and shifting the second operand is performed by a shifter also used for floating point functions.
摘要翻译：从存储装置获取操作数的方法包括从存储装置中的第一位置读取第一操作数，第一操作数包括由指令指定的操作数的一部分，将第一操作数移位第一移位量，读第二操作数来自存储器件的数据操作数，第二操作数具有由指令指定的操作数的一部分，将第二操作数移位第二移位量，并组合第一移位数据条目和第二移位数据条目以产生对准的操作数，其中移动第一操作数并移动第二操作数由也用于浮点函数的移位器执行。

54. 发明授权

US06425055B1 Way-predicting cache memory 有权
标题翻译：预测缓存的方式
公开(公告)号：US06425055B1
公开(公告)日：2002-07-23
申请号：US09256846
申请日：1999-02-24
申请人： David J. Sager , Glenn J. Hinton
发明人： David J. Sager , Glenn J. Hinton
IPC分类号： G06F1200
CPC分类号： G06F12/0864 , G06F2212/6082
摘要： An apparatus and method for accessing a cache memory. In a cache memory, an address is received that includes a set field and a partial tag field, the set field and the partial tag field together including fewer bits than necessary to uniquely identify a region of memory equal in size to a cache line of the cache memory. The set field is decoded to select one of a plurality of storage units within the cache memory, each of the plurality of storage units including a plurality of cache lines of the cache memory. The partial tag field is compared to a plurality of previously stored partial tags that correspond to the plurality of cache lines within the selected one of the plurality of storage units to determine if the partial tag field matches one of the plurality of previously stored partial tags. If the one of the previously stored partial tags matches the partial tag field, one of the plurality of cache lines that corresponds to the one of the plurality of previously stored partial tags is output.
摘要翻译：一种用于访问高速缓冲存储器的装置和方法。在高速缓冲存储器中，接收到包括设置字段和部分标签字段的地址，所述设置字段和部分标签字段一起包括比唯一标识尺寸相等于所述存储器的高速缓存行大小的存储区域所需的位数高速缓存存储器。解码设置字段以选择高速缓冲存储器内的多个存储单元中的一个，多个存储单元中的每一个包括高速缓存存储器的多个高速缓存行。将部分标签字段与多个先前存储的部分标签进行比较，所述部分标签对应于多个存储单元中所选择的一个存储单元内的多个高速缓存行，以确定部分标签字段是否匹配多个先前存储的部分标签之一。如果先前存储的部分标签之一与部分标签字段匹配，则输出与多个先前存储的部分标签之一对应的多条高速缓存行之一。

55. 发明授权

US06378062B1 Method and apparatus for performing a store operation 失效
标题翻译：用于执行存储操作的方法和装置
公开(公告)号：US06378062B1
公开(公告)日：2002-04-23
申请号：US08825427
申请日：1997-03-28
申请人： Jeffery M. Abramson , Haitham Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland
发明人： Jeffery M. Abramson , Haitham Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland
IPC分类号： G06F930
CPC分类号： G06F9/3855 , G06F9/30043 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3857
摘要： The present invention provides for executing store instructions with a processor. The present invention executes each of the store instructions by producing the data that is to be stored and by calculating the destination address to which the data is to be stored. In the present invention, the store instructions are executed to produce the destination address of the store instruction earlier than the prior art.
摘要翻译：本发明提供用处理器执行存储指令。本发明通过产生要存储的数据并通过计算要存储数据的目的地地址来执行每个存储指令。在本发明中，执行存储指令以比现有技术更早地产生存储指令的目的地地址。

56. 发明授权

US06378061B1 Apparatus for issuing instructions and reissuing a previous instructions by recirculating using the delay circuit 失效
标题翻译：用于通过使用延迟电路再循环来发出指令并再次发出先前指令的装置
公开(公告)号：US06378061B1
公开(公告)日：2002-04-23
申请号：US08150784
申请日：1993-11-12
申请人： Adrian Carbine , Glenn J. Hinton , Frank S. Smith
发明人： Adrian Carbine , Glenn J. Hinton , Frank S. Smith
IPC分类号： G06F930
CPC分类号： G06F9/3808 , G06F9/30054 , G06F9/3017 , G06F9/3836 , G06F9/3838 , G06F9/3857
摘要： An instruction decoder that issues new instructions by driving a machine bus (110) with the correct information during each clock cycle. This information is either extracted from the current instruction to be executed, or is recycled from the previous contents (106) of the machine bus when a scoreboarding operation has been performed. Mousetrap multiplexer (104) chooses between several sources of opcode and operand fields and routes them to the machine bus (110) through several translation stages and multiplexers. The decision of which source to use is based on what kind of instruction is currently being looked at by the instruction queue in the instruction fetch unit. The instruction queue notifies the instruction decoder that the next instruction is to be either a RISC operation (including register, memory, and/or branch instructions) or an instruction which is part of a microcode flow. If a complex macroinstruction flow is in progress, its operands can be accessed through alias registers. This allows indirect access to a source or destination register specified by the operands of the macrocode instruction or the opcode of the macroinstruction while executing a sequence of microinstructions. These aliased operands are maintained by the macroinstruction aliasing logic (100).
摘要翻译：一种指令解码器，其通过在每个时钟周期期间以正确的信息驱动机器总线（110）来发布新的指令。当执行记分操作时，该信息是从当前要执行的指令中提取的，或者从机器总线的先前内容（106）中循环回收的。捕鼠器多路复用器（104）在操作码和操作数字段的几个来源之间进行选择，并通过多个转换级和多路复用器将它们路由到机器总线（110）。使用哪个源的决定是基于指令提取单元中的指令队列当前正在查看什么样的指令。指令队列通知指令解码器下一条指令是RISC操作（包括寄存器，存储器和/或分支指令）或作为微代码流的一部分的指令。如果复杂的宏指令流正在进行，则可以通过别名寄存器访问其操作数。这允许在执行一个微指令序列时，间接访问由宏代码指令的操作数指定的源或目标寄存器或宏指令的操作码。这些混叠的操作数由宏指令混叠逻辑（100）维护。

57. 发明授权

US06230257B1 Method and apparatus for staggering execution of a single packed data instruction using the same circuit 失效
标题翻译：用于使用相同电路交错执行单个打包数据指令的方法和装置
公开(公告)号：US06230257B1
公开(公告)日：2001-05-08
申请号：US09053004
申请日：1998-03-31
申请人： Patrice Roussel , Glenn J. Hinton , Shreekant S. Thakkar , Brent R. Boswell , Karol F. Menezes
发明人： Patrice Roussel , Glenn J. Hinton , Shreekant S. Thakkar , Brent R. Boswell , Karol F. Menezes
IPC分类号： G06F738
CPC分类号： G06F9/30014 , G06F9/30036 , G06F9/3826 , G06F9/3828 , G06F9/3875 , G06F9/3885
摘要： A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.
摘要翻译：公开了一种用于交错执行指令的方法和装置。根据本发明的一个实施例，接收单个宏指令，其中单个宏指令指定至少两个逻辑寄存器，并且其中两个逻辑寄存器分别存储具有相应数据元素的第一和第二压缩数据操作数。然后，使用相同电路，在来自所述第一和第二打包数据操作数的第一和第二多个相应数据元素上独立地执行由单个宏指令指定的操作，以独立地生成第一和第二多个结果数据元素。第一和第二多个结果数据元素作为第三打包数据操作数存储在单个逻辑寄存器中。

58. 发明授权

US5913050A Method and apparatus for providing address-size backward compatibility in a processor using segmented memory 失效
标题翻译：在使用分段存储器的处理器中提供地址大小向后兼容性的方法和装置
公开(公告)号：US5913050A
公开(公告)日：1999-06-15
申请号：US735048
申请日：1996-10-22
申请人： Darrell D. Boggs , Robert P. Colwell , Michael A. Fetterman , Andrew F. Glew , Glenn J. Hinton , David B. Papworth
发明人： Darrell D. Boggs , Robert P. Colwell , Michael A. Fetterman , Andrew F. Glew , Glenn J. Hinton , David B. Papworth
IPC分类号： G06F9/32 , G06F9/38 , G06F12/06 , G06F9/26
CPC分类号： G06F9/3804 , G06F9/30054
摘要： This invention overcomes the address size backward compatibility problem by first subtracting the segment base address from the linear destination address of a branch instruction to generate a virtual destination address. It is assumed that the branch instruction destination address is n bits long with m most significant bits. It is desired to provide backward compatibility in the n-bit processor for branch instruction code written for processors utilizing instruction address fields of size (n-m) bits. After obtaining the virtual address, if any of the m most significant bits are non-zero, then those m bits are set to zero to thereby generate a corrected virtual address. If such a compatibility correction is necessary, then a clear signal is asserted to flush all state of the processor that resulted from instructions being fetched after the branch instruction was fetched. The corrected virtual address is added back to the segment base address to generate a corrected linear address. The next instruction is fetched at the corrected linear address.
摘要翻译：本发明通过首先从分支指令的线性目的地地址中减去分段基地址来生成虚拟目的地地址来克服地址大小向后兼容性问题。假设分支指令目标地址是n位长，m个最高有效位。期望在n比特处理器中为使用大小（n-m）比特的指令地址字段为处理器编写的分支指令代码提供向后兼容性。在获得虚拟地址之后，如果m个最高有效位中的任何一个非零，则将这些m位设置为零，从而生成校正的虚拟地址。如果需要这种兼容性校正，则清除信号被断言以清除在分支指令被取出之后被取出的指令导致的处理器的所有状态。校正的虚拟地址被加回到段基地址以产生校正的线性地址。下一条指令是在校正的线性地址处获取的。

59. 发明授权

US5881262A Method and apparatus for blocking execution of and storing load operations during their execution 失效
标题翻译：用于在其执行期间阻止执行和存储加载操作的方法和装置
公开(公告)号：US5881262A
公开(公告)日：1999-03-09
申请号：US928924
申请日：1997-09-12
申请人： Jeffery M. Abramson , Haitham Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland
发明人： Jeffery M. Abramson , Haitham Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland
IPC分类号： G06F9/312 , G06F9/38 , G06F13/00
CPC分类号： G06F9/3017 , G06F9/30043 , G06F9/3816 , G06F9/3824 , G06F9/3834 , G06F9/3836 , G06F9/3842
摘要： A method and apparatus for performing load operations in a computer system. The present invention includes a method and apparatus for dispatching the load operation to be executed. The present invention halts the execution of the load operation when a dependency exists between the load operation and another memory operation currently pending in the system. When the dependency no longer exists, the present invention redispatches the load operation so that it completes.
摘要翻译：一种用于在计算机系统中执行加载操作的方法和装置。本发明包括一种用于调度要执行的加载操作的方法和装置。本发明在加载操作和系统中当前待处理的另一个存储器操作之间存在依赖关系时，停止加载操作的执行。当依赖关系不再存在时，本发明重新分派加载操作使其完成。

60. 发明授权

US5845100A Dual instruction buffers with a bypass bus and rotator for a decoder of multiple instructions of variable length 失效
标题翻译：具有旁路总线和旋转器的双指令缓冲器，用于可变长度的多个指令的解码器
公开(公告)号：US5845100A
公开(公告)日：1998-12-01
申请号：US806022
申请日：1997-02-24
申请人： Ashwani Kumar Gupta , Glenn J. Hinton , Chan W. Lee
发明人： Ashwani Kumar Gupta , Glenn J. Hinton , Chan W. Lee
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30152 , G06F9/3816
摘要： A circuit and method for supplying a block of instruction code to an instruction buffer for an instruction decoder. A block of instruction code is fetched and input through a buffer input. A first instruction buffer and a second instruction buffer are coupled to the buffer input to store the block of instruction code. The output of the instruction buffers and a bypass bus coupled to the buffer input are input into an instruction buffer multiplexer. The instruction buffer multiplexer selects among the three inputs and outputs two blocks of instruction code to a rotator. The rotator receives an input pointer indicative of an initial byte. The rotator outputs a block of instruction code beginning at the initial byte to an instruction decoder.
摘要翻译：一种用于向指令解码器的指令缓冲器提供指令代码块的电路和方法。指令代码块通过缓冲器输入获取和输入。第一指令缓冲器和第二指令缓冲器耦合到缓冲器输入端以存储指令代码块。指令缓冲器的输出和耦合到缓冲器输入的旁路总线被输入到指令缓冲多路复用器。指令缓冲多路复用器在三个输入端之间进行选择，并向转子输出两个指令代码块。旋转器接收指示初始字节的输入指针。旋转器将从初始字节开始的指令代码块输出到指令解码器。

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