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1. 发明授权

US06721866B2 Unaligned memory operands 有权
标题翻译：未对齐的内存操作数
公开(公告)号：US06721866B2
公开(公告)日：2004-04-13
申请号：US10029367
申请日：2001-12-21
申请人： Patrice Roussel , Eric Sprangle , Glenn J. Hinton
发明人： Patrice Roussel , Eric Sprangle , Glenn J. Hinton
IPC分类号： G06F1204
CPC分类号： G06F9/30043
摘要： A method of obtaining an operand from a memory device includes reading a first operand from a first location in a memory device, the first operand including part of the operand specified by an instruction, shifting the first operand by a first shift amount, reading a second data operand from the memory device, the second operand having part of the operand specified by the instruction, shifting the second operand by a second shift amount, and combining the first shifted data entry and the second shifted data entry to produce an aligned operand, wherein shifting the first operand and shifting the second operand is performed by a shifter also used for floating point functions.
摘要翻译：从存储装置获取操作数的方法包括从存储装置中的第一位置读取第一操作数，第一操作数包括由指令指定的操作数的一部分，将第一操作数移位第一移位量，读第二操作数来自存储器件的数据操作数，第二操作数具有由指令指定的操作数的一部分，将第二操作数移位第二移位量，并组合第一移位数据条目和第二移位数据条目以产生对准的操作数，其中移动第一操作数并移动第二操作数由也用于浮点函数的移位器执行。

2. 发明授权

US08892848B2 Processor and system using a mask register to track progress of gathering and prefetching elements from memory 有权
标题翻译：处理器和系统使用掩码寄存器跟踪从内存中采集和预取元素的进度
公开(公告)号：US08892848B2
公开(公告)日：2014-11-18
申请号：US13175953
申请日：2011-07-05
申请人： Eric Sprangle , Anwar Rohillah , Robert Cavin , Tom Forsyth , Michael Abrash
发明人： Eric Sprangle , Anwar Rohillah , Robert Cavin , Tom Forsyth , Michael Abrash
IPC分类号： G06F9/312 , G06F9/30 , G06F12/02 , G06F9/345 , G06F9/38 , G06F15/80
CPC分类号： G06F15/8069 , G06F9/30043 , G06F9/30047 , G06F9/30098 , G06F9/30101 , G06F9/345 , G06F9/383 , G06F12/02 , G06F12/0875 , G06F2212/452 , G06F2212/602 , G06F2212/6028
摘要： A device, system and method for assigning values to elements in a first register, where each data field in a first register corresponds to a data element to be written into a second register, and where for each data field in the first register, a first value may indicate that the corresponding data element has not been written into the second register and a second value indicates that the corresponding data element has been written into the second register, reading the values of each of the data fields in the first register, and for each data field in the first register having the first value, gathering the corresponding data element and writing the corresponding data element into the second register, and changing the value of the data field in the first register from the first value to the second value. Other embodiments are described and claimed.
摘要翻译：一种用于将值分配给第一寄存器中的元件的装置，系统和方法，其中第一寄存器中的每个数据字段对应于要写入第二寄存器的数据元素，并且对于第一寄存器中的每个数据字段，值可以指示相应的数据元素尚未被写入第二寄存器，第二值指示对应的数据元素已被写入第二寄存器，读取第一寄存器中每个数据域的值，并且为第一寄存器中的每个数据字段具有第一值，收集对应的数据元素并将相应的数据元素写入第二寄存器，并将第一寄存器中的数据字段的值从第一值改变为第二值。描述和要求保护其他实施例。

3. 发明申请

US20140052969A1 SUPER MULTIPLY ADD (SUPER MADD) INSTRUCTIONS WITH THREE SCALAR TERMS 有权
标题翻译：超级增加（超级）指令与三个标准条款
公开(公告)号：US20140052969A1
公开(公告)日：2014-02-20
申请号：US13976997
申请日：2011-12-23
申请人： Jesus Corbal , Andrew T. Forsyth , Thomas D. Fletcher , Lisa K. Wu , Eric Sprangle
发明人： Jesus Corbal , Andrew T. Forsyth , Thomas D. Fletcher , Lisa K. Wu , Eric Sprangle
IPC分类号： G06F9/30
CPC分类号： G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30036 , G06F9/30145 , G06F9/3893
摘要： A processing core is described having execution unit logic circuitry having a first register to store a first vector input operand, a second register to a store a second vector input operand and a third register to store a packed data structure containing scalar input operands a, b, c. The execution unit logic circuitry further include a multiplier to perform the operation (a*(first vector input operand))+(b*(second vector operand))+c.
摘要翻译：描述处理核心，其具有执行单元逻辑电路，其具有第一寄存器以存储第一向量输入操作数，第二寄存器存储第二向量输入操作数和第三寄存器以存储包含标量输入操作数a，b的打包数据结构， C。执行单元逻辑电路还包括执行操作的乘法器（a *（第一向量输入操作数））+（b *（第二向量操作数））+ c。

4. 发明申请

US20140019656A1 DISTRIBUTION OF TASKS AMONG ASYMMETRIC PROCESSING ELEMENTS 有权
标题翻译：在非对称加工元素中分配任务
公开(公告)号：US20140019656A1
公开(公告)日：2014-01-16
申请号：US14033008
申请日：2013-09-20
申请人： Herbert Hum , Eric Sprangle , Doug Carmean , Rajesh Kumar
发明人： Herbert Hum , Eric Sprangle , Doug Carmean , Rajesh Kumar
IPC分类号： G06F13/24
CPC分类号： G06F1/3293 , G06F1/206 , G06F1/3203 , G06F1/3206 , G06F1/3228 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F9/3869 , G06F9/461 , G06F9/5088 , G06F9/5094 , G06F12/0875 , G06F13/24 , G06F2209/5017 , G06F2212/452 , G06T1/20 , Y02B70/10 , Y02B70/1425 , Y02B70/30 , Y02B70/32 , Y02D10/122 , Y02D10/126 , Y02D10/172 , Y02D50/20
摘要： Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system
摘要翻译：控制多个不对称核心之间的功率和处理的技术。在一个实施例中，根据系统的性能和功率需求，一个或多个非对称核被功率管理以在多个核之间迁移进程或线程

5. 发明申请

US20130318373A1 DISTRIBUTION OF TASKS AMONG ASYMMETRIC PROCESSING ELEMENTS 审中-公开
公开(公告)号：US20130318373A1
公开(公告)日：2013-11-28
申请号：US13954977
申请日：2013-07-31
申请人： Herbert Hum , Eric Sprangle , Doug Carmean , Rajesh Kumar
发明人： Herbert Hum , Eric Sprangle , Doug Carmean , Rajesh Kumar
IPC分类号： G06F1/32 , G06F9/50
CPC分类号： G06F1/3293 , G06F1/206 , G06F1/3203 , G06F1/3206 , G06F1/3228 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F9/3869 , G06F9/461 , G06F9/5088 , G06F9/5094 , G06F12/0875 , G06F13/24 , G06F2209/5017 , G06F2212/452 , G06T1/20 , Y02B70/10 , Y02B70/1425 , Y02B70/30 , Y02B70/32 , Y02D10/122 , Y02D10/126 , Y02D10/172 , Y02D50/20
摘要： Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system

6. 发明申请

US20110157195A1 Sharing resources between a CPU and GPU 有权
标题翻译：在CPU和GPU之间共享资源
公开(公告)号：US20110157195A1
公开(公告)日：2011-06-30
申请号：US12655577
申请日：2009-12-31
申请人： Eric Sprangle , Matthew Craighead , Chris Goodman , Belliappa Kuttanna
发明人： Eric Sprangle , Matthew Craighead , Chris Goodman , Belliappa Kuttanna
IPC分类号： G06T15/00
CPC分类号： G06T1/20
摘要： A technique to share execution resources. In one embodiment, a CPU and a GPU share resources according to workload, power considerations, or available resources by scheduling or transferring instructions and information between the CPU and GPU.
摘要翻译：一种共享执行资源的技术。在一个实施例中，CPU和GPU根据工作负载，功率注意事项或可用资源通过在CPU和GPU之间调度或传送指令和信息来共享资源。

7. 发明申请

US20060047915A1 Method and apparatus for prefetching data to a lower level cache memory 有权
标题翻译：用于将数据预取到较低级高速缓冲存储器的方法和装置
公开(公告)号：US20060047915A1
公开(公告)日：2006-03-02
申请号：US10933188
申请日：2004-09-01
申请人： Kenneth Janik , K.S. Venkatraman , Anwar Rohillah , Eric Sprangle , Ronak Singhal
发明人： Kenneth Janik , K.S. Venkatraman , Anwar Rohillah , Eric Sprangle , Ronak Singhal
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0862 , G06F2212/6024
摘要： A prefetching scheme to detect when a load misses the lower level cache and hits the next level cache. Consequently, the prefetching scheme utilizes the previous information for the cache miss to the lower level cache and hit to the next higher level of cache memory that may result in initiating a sidedoor prefetch load for fetching the previous or next cache line into the lower level cache. In order to generate an address for the sidedoor prefetch, a history of cache access is maintained in a queue.
摘要翻译：一种预取方案，用于检测何时加载错过较低级别的缓存，并触发下一级缓存。因此，预取方案利用先前的信息将高速缓存未命中用于较低级别的高速缓存并且命中到下一个较高级别的高速缓冲存储器，这可能导致发起侧面预取负载，以将先前或下一个高速缓存行提取到下一级高速缓存。为了生成二进制预取的地址，在队列中保持高速缓存访问的历史。

8. 发明授权

US08933946B2 Mechanism for effectively handling texture sampling 有权
标题翻译：有效处理纹理采样的机制
公开(公告)号：US08933946B2
公开(公告)日：2015-01-13
申请号：US11967408
申请日：2007-12-31
申请人： Eric Sprangle
发明人： Eric Sprangle
IPC分类号： G06T1/00 , G06T15/00 , G09G5/00 , G06F9/45 , G06T15/04 , G09G5/02
CPC分类号： G09G5/00 , G06F8/41 , G06T15/005 , G06T15/04 , G06T2200/28 , G09G5/026 , G09G2340/10 , G09G2360/121
摘要： A method and apparatus for efficiently handling texture sampling is described herein. A compiler or other software is capable of breaking a texture sampling operation for a pixel into a pre-fetch operation and a use operation. A processing element, in response to executing the pre-fetch operation, delegates computation of the texture sample of the pixel to a hardware texture sample unit. In parallel to the hardware texture sample unit performing a texture sample for the pixel and providing the result, i.e. a textured pixel (texel), to a destination address, the processing element is capable of executing other independent code. After an amount of time, the processing element executes the use operation, such as a load operation to load the texel from the destination address.
摘要翻译：本文描述了一种用于有效处理纹理采样的方法和装置。编译器或其他软件能够将像素的纹理采样操作分解成预取操作和使用操作。响应于执行预取操作，处理元件将像素的纹理样本的计算委托给硬件纹理采样单元。与硬件纹理采样单元平行地执行像素的纹理样本并将结果（即，纹理像素（纹素））提供给目的地址，处理元件能够执行其他独立代码。在一段时间之后，处理元件执行使用操作，例如从目的地地址加载纹素的加载操作。

9. 发明申请

US20140149651A1 Providing Extended Cache Replacement State Information 有权
标题翻译：提供扩展缓存替换状态信息
公开(公告)号：US20140149651A1
公开(公告)日：2014-05-29
申请号：US13685991
申请日：2012-11-27
申请人： Andrew T. Forsyth , Ramacharan Sundararaman , Eric Sprangle , John C. Mejia , Douglas M. Carmean , Mark C. Davis , Edward T. Grochowski , Robert D. Cavin
发明人： Andrew T. Forsyth , Ramacharan Sundararaman , Eric Sprangle , John C. Mejia , Douglas M. Carmean , Mark C. Davis , Edward T. Grochowski , Robert D. Cavin
IPC分类号： G06F12/08
CPC分类号： G06F12/126 , G06F12/123 , Y02D10/13
摘要： In an embodiment, a processor includes a decode logic to receive and decode a first memory access instruction to store data in a cache memory with a replacement state indicator of a first level, and to send the decoded first memory access instruction to a control logic. In turn, the control logic is to store the data in a first way of a first set of the cache memory and to store the replacement state indicator of the first level in a metadata field of the first way responsive to the decoded first memory access instruction. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括解码逻辑，用于接收和解码第一存储器访问指令以将数据存储在具有第一级的替换状态指示符的高速缓冲存储器中，并将解码的第一存储器访问指令发送到控制逻辑。反过来，控制逻辑是以第一组高速缓冲存储器的第一种方式存储数据，并且响应于解码的第一存储器访问指令将第一级的替换状态指示符存储在第一方式的元数据字段中。描述和要求保护其他实施例。

10. 发明申请

US20140130058A1 DISTRIBUTION OF TASKS AMONG ASYMMETRIC PROCESSING ELEMENTS 审中-公开
标题翻译：在非对称加工元素中分配任务
公开(公告)号：US20140130058A1
公开(公告)日：2014-05-08
申请号：US14154517
申请日：2014-01-14
申请人： Herbert Hum , Eric Sprangle , Doug Carmean , Rajesh Kumar
发明人： Herbert Hum , Eric Sprangle , Doug Carmean , Rajesh Kumar
IPC分类号： G06F9/50
CPC分类号： G06F1/3293 , G06F1/206 , G06F1/3203 , G06F1/3206 , G06F1/3228 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F9/3869 , G06F9/461 , G06F9/5088 , G06F9/5094 , G06F12/0875 , G06F13/24 , G06F2209/5017 , G06F2212/452 , G06T1/20 , Y02B70/10 , Y02B70/1425 , Y02B70/30 , Y02B70/32 , Y02D10/122 , Y02D10/126 , Y02D10/172 , Y02D50/20
摘要： Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.
摘要翻译：控制多个不对称核心之间的功率和处理的技术。在一个实施例中，根据系统的性能和功率需求，一个或多个非对称核被功率管理以在多个核之间迁移进程或线程。

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