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1. 发明授权

US5845100A Dual instruction buffers with a bypass bus and rotator for a decoder of multiple instructions of variable length 失效
标题翻译：具有旁路总线和旋转器的双指令缓冲器，用于可变长度的多个指令的解码器
公开(公告)号：US5845100A
公开(公告)日：1998-12-01
申请号：US806022
申请日：1997-02-24
申请人： Ashwani Kumar Gupta , Glenn J. Hinton , Chan W. Lee
发明人： Ashwani Kumar Gupta , Glenn J. Hinton , Chan W. Lee
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30152 , G06F9/3816
摘要： A circuit and method for supplying a block of instruction code to an instruction buffer for an instruction decoder. A block of instruction code is fetched and input through a buffer input. A first instruction buffer and a second instruction buffer are coupled to the buffer input to store the block of instruction code. The output of the instruction buffers and a bypass bus coupled to the buffer input are input into an instruction buffer multiplexer. The instruction buffer multiplexer selects among the three inputs and outputs two blocks of instruction code to a rotator. The rotator receives an input pointer indicative of an initial byte. The rotator outputs a block of instruction code beginning at the initial byte to an instruction decoder.
摘要翻译：一种用于向指令解码器的指令缓冲器提供指令代码块的电路和方法。指令代码块通过缓冲器输入获取和输入。第一指令缓冲器和第二指令缓冲器耦合到缓冲器输入端以存储指令代码块。指令缓冲器的输出和耦合到缓冲器输入的旁路总线被输入到指令缓冲多路复用器。指令缓冲多路复用器在三个输入端之间进行选择，并向转子输出两个指令代码块。旋转器接收指示初始字节的输入指针。旋转器将从初始字节开始的指令代码块输出到指令解码器。

2. 发明授权

US5812839A Dual prediction branch system having two step of branch recovery process which activated only when mispredicted branch is the oldest instruction in the out-of-order unit 失效
标题翻译：双预测分支系统具有分支恢复过程的两个步骤，仅在错误预测分支是无序单元中最旧的指令时激活
公开(公告)号：US5812839A
公开(公告)日：1998-09-22
申请号：US851141
申请日：1997-05-05
申请人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Ashwani Kumar Gupta , Michael Alan Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
发明人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Ashwani Kumar Gupta , Michael Alan Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/322 , G06F9/3844 , G06F9/3863 , G06F9/3885
摘要： A four stage branch instruction resolution system for a pipelined processor is disclosed. A first stage of the branch instruction resolution system predicts the existence and outcome of branch instructions within an instruction stream such that an instruction fetch unit can continually fetch instructions. A second stage decodes all the instructions fetched. If the decode stage determines that a branch instruction predicted by the first stage is not a branch instruction, the decode stage flushes the pipeline and restarts the processor at a corrected address. The decode stage verifies all branch predictions made by the branch prediction stage. Finally, the decode stage makes branch predictions for branches not predicted by the branch prediction stage. A third stage executes all the branch instructions to determine a final branch outcome and a final branch target address. The branch execution stage compares the final branch outcome and final branch target address with the predicted branch outcome and predicted branch target address to determine if the processor must flush the front-end of the microprocessor pipeline and restart at a corrected address. A final branch resolution stage retires all branch instructions. The retirement stage ensures that any instructions fetched after a mispredicted branch are not committed into permanent state.
摘要翻译：公开了一种用于流水线处理器的四级分支指令解析系统。分支指令解析系统的第一阶段预测指令流内分支指令的存在和结果，使得指令获取单元可以连续地获取指令。第二阶段解码所有提取的指令。如果解码级确定由第一级预测的分支指令不是分支指令，则解码级别刷新流水线并以校正的地址重新启动处理器。解码阶段验证分支预测阶段所做的所有分支预测。最后，解码阶段对分支预测阶段未预测的分支进行分支预测。第三阶段执行所有分支指令以确定最终分支结果和最终分支目标地址。分支执行阶段将最终分支结果和最终分支目标地址与预测的分支结果和预测分支目标地址进行比较，以确定处理器是否必须冲洗微处理器流水线的前端并以修正的地址重新启动。最终的分支解决阶段退出所有分支指令。退休阶段确保在错误预测的分支之后提取的任何指令不会被永久保留。

3. 发明授权

US5903751A Method and apparatus for implementing a branch target buffer in CISC processor 失效
标题翻译：在CISC处理器中实现分支目标缓冲器的方法和装置
公开(公告)号：US5903751A
公开(公告)日：1999-05-11
申请号：US931807
申请日：1997-09-16
申请人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Ashwani Kumar Gupta , Michael Alan Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
发明人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Ashwani Kumar Gupta , Michael Alan Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/30054
摘要： A Branch Target Buffer Circuit in a computer processor that predicts branch instructions with a stream of computer instructions is disclosed. The Branch Target Buffer Circuit uses a Branch Target Buffer Cache that stores branch information about previously executed branch instructions. The branch information stored in the Branch Target Buffer Cache is addressed by the last byte of each branch instruction. When an Instruction Fetch Unit in the computer processor fetches a block of instructions it sends the Branch Target Buffer Circuit an instruction pointer. Based on the instruction pointer, the Branch Target Buffer Circuit looks in the Branch Target Buffer Cache to see if any of the instructions in the block being fetched is a branch instruction. When the Branch Target Buffer Circuit finds an upcoming branch instruction in the Branch Target Buffer Cache, the Branch Target Buffer Circuit informs an Instruction Fetch Unit about the upcoming branch instruction.
摘要翻译：公开了一种使用计算机指令流预测分支指令的计算机处理器中的分支目标缓冲器电路。分支目标缓冲器电路使用分支目标缓冲器高速缓存，其存储关于先前执行的分支指令的分支信息。存储在分支目标缓冲区高速缓存中的分支信息由每个分支指令的最后一个字节寻址。当计算机处理器中的指令获取单元获取指令块时，它向分支目标缓冲器电路发送指令指针。基于指令指针，分支目标缓冲器电路查找分支目标缓冲区高速缓存以查看正在获取的块中的任何指令是否是分支指令。当分支目标缓冲器电路在分支目标缓冲器高速缓存中找到即将到来的分支指令时，分支目标缓冲器电路通知指令获取单元关于即将到来的分支指令。

4. 发明授权

US5768576A Method and apparatus for predicting and handling resolving return from subroutine instructions in a computer processor 失效
标题翻译：用于预测和处理计算机处理器中的子程序指令的解析返回的方法和装置
公开(公告)号：US5768576A
公开(公告)日：1998-06-16
申请号：US739743
申请日：1996-10-29
申请人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Ashwani Kumar Gupta , Michael Alan Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
发明人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Ashwani Kumar Gupta , Michael Alan Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
IPC分类号： G06F9/38 , G06F9/42
CPC分类号： G06F9/3806 , G06F9/30054 , G06F9/4426
摘要： A method and apparatus for resolving Return From Subroutine instructions in a computer processor are disclosed. The method and apparatus resolve Return From Subroutine instructions in four stages. A first stage predicts Call Subroutine instructions and Return From Subroutine instructions within the instruction stream. The first stage stores a return address in a return register when a Call Subroutine instruction is predicted. The first stage predicts a return to the return address in the return register when a Return From Subroutine instruction is predicted. A second stage decodes each Call Subroutine and Return From Subroutine instruction in order to maintain a Return Stack Buffer that stores a stack of return addresses. Each time the second stage decodes a Call Subroutine instruction, a return address is pushed onto the Return Stack Buffer. Correspondingly, each time the second stage decodes a Return From Subroutine instruction, a return address is popped off of the Return Stack Buffer. The second stage verifies predictions made by the first stage and predicts return addresses for Return From Subroutine instructions that were not predicted by the first stage. A third stage executes Return From Subroutine instructions such that the predictions are verified. Finally, a fourth stage retires Return From Subroutine instructions and ensures that no instructions fetch after a mispredicted return address are committed into permanent state.
摘要翻译：公开了一种用于解决计算机处理器中的子程序返回指令的方法和装置。该方法和设备分四个阶段解析子程序指令。第一阶段预测指令流中的调用子程序指令和子程序返回指令。当预测一个调用子程序指令时，第一阶段将返回地址存储在一个返回寄存器中。第一阶段预测当返回从子程序指令被预测时返回寄存器中的返回地址。第二阶段解码每个调用子程序和从子程序返回指令，以便维护一个存储一堆返回地址的返回栈缓冲区。每次第二阶段解码一个调用子程序指令时，一个返回地址被推到返回栈缓冲区上。相应地，每次第二级解码从子程序返回指令时，返回地址从返回堆栈缓冲区中弹出。第二阶段验证第一阶段做出的预测，并预测第一阶段未预测的返回从子程序指令的返回地址。第三阶段执行从子程序返回指令，使得预测得到验证。最后，第四阶段退出从子程序返回指令，并确保在错误预测的返回地址之后没有指令提取到永久状态。

5. 发明授权

US6018786A Trace based instruction caching 失效
标题翻译：基于跟踪的指令缓存
公开(公告)号：US6018786A
公开(公告)日：2000-01-25
申请号：US956375
申请日：1997-10-23
申请人： Robert F. Krick , Glenn J. Hinton , Michael D. Upton , David J. Sager , Chan W. Lee
发明人： Robert F. Krick , Glenn J. Hinton , Michael D. Upton , David J. Sager , Chan W. Lee
IPC分类号： G06F9/32 , G06F9/38 , G06F12/08 , G06F9/26 , G06F12/00
CPC分类号： G06F9/3808 , G06F12/0875 , G06F9/3802 , G06F9/3836
摘要： A cache memory is constituted with a data array and control logic. The data array includes a number of data lines, and the control logic operates to store a number of trace segments of instructions in the data lines, including trace segments that span multiple data lines. In one embodiment, each trace segment includes one or more trace segment members having one or more instructions, with each trace segment member occupying one data line, and the data lines of a multi-line trace segment being sequentially associated (logically). Retrieval of the trace segment members of a multi-line trace segment is accomplished by first locating the data line storing the first trace segment member of the trace segment, and then successively locating the remaining data lines storing the remaining trace segment members based on the data lines' logical sequential associations.
摘要翻译：高速缓冲存储器由数据阵列和控制逻辑构成。数据阵列包括许多数据线，并且控制逻辑操作以在数据线中存储多条迹线段，包括跨越多个数据线的迹线段。在一个实施例中，每个跟踪段包括具有一个或多个指令的一个或多个跟踪段成员，每个跟踪段成员占据一个数据线，并且多行跟踪段的数据线被顺序地相关联（逻辑地）。通过首先定位存储跟踪段的第一跟踪段成员的数据线，然后基于数据连续定位存储剩余跟踪段成员的剩余数据线，来检索多行跟踪段的跟踪段成员行的逻辑顺序关联。

6. 发明授权

US5608885A Method for handling instructions from a branch prior to instruction decoding in a computer which executes variable-length instructions 失效
标题翻译：用于在执行可变长度指令的计算机中的指令解码之前从分支处理指令的方法
公开(公告)号：US5608885A
公开(公告)日：1997-03-04
申请号：US205022
申请日：1994-03-01
申请人： Ashwani K. Gupta , Glenn J. Hinton , Chan W. Lee
发明人： Ashwani K. Gupta , Glenn J. Hinton , Chan W. Lee
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30152 , G06F9/3816
摘要： A circuit and method for supplying a block of instruction code to an instruction buffer for an instruction decoder. A block of instruction code is fetched and input through a buffer input. A first instruction buffer and a second instruction buffer are coupled to the buffer input to store the block of instruction code. The output of the instruction buffers and a bypass bus coupled to the buffer input are input into an instruction buffer multiplexer. The instruction buffer multiplexer selects among the three inputs and outputs two blocks of instruction code to a rotator. The rotator receives an input pointer indicative of an initial byte. The rotator outputs a block of instruction code beginning at the initial byte to an instruction decoder.
摘要翻译：一种用于向指令解码器的指令缓冲器提供指令代码块的电路和方法。指令代码块通过缓冲器输入获取和输入。第一指令缓冲器和第二指令缓冲器耦合到缓冲器输入端以存储指令代码块。指令缓冲器的输出和耦合到缓冲器输入的旁路总线被输入到指令缓冲多路复用器。指令缓冲多路复用器在三个输入端之间进行选择，并向转子输出两个指令代码块。旋转器接收指示初始字节的输入指针。旋转器将从初始字节开始的指令代码块输出到指令解码器。

7. 发明授权

US06170038A Trace based instruction caching 有权
标题翻译：基于跟踪的指令缓存
公开(公告)号：US06170038A
公开(公告)日：2001-01-02
申请号：US09447078
申请日：1999-11-22
申请人： Robert F. Krick , Glenn J. Hinton , Michael D. Upton , David J. Sager , Chan W. Lee
发明人： Robert F. Krick , Glenn J. Hinton , Michael D. Upton , David J. Sager , Chan W. Lee
IPC分类号： G06F926
CPC分类号： G06F12/0875
摘要： A cache memory is constituted with a data array and control logic. The data array includes a number of data lines, and the control logic operates to store a number of trace segments of instructions in the data lines, including trace segments that span multiple data lines. In one embodiment, each trace segment includes one or more trace segment members having one or more instructions, with each trace segment member occupying one data line, and the data lines of a multi-line trace segment being sequentially associated (logically). Retrieval of the trace segment members of a multi-line trace segment is accomplished by first locating the data line storing the first trace segment member of the trace segment, and then successively locating the remaining data lines storing the remaining trace segment members based on the data lines' logical sequential associations.
摘要翻译：高速缓冲存储器由数据阵列和控制逻辑构成。数据阵列包括许多数据线，并且控制逻辑操作以在数据线中存储多条迹线段，包括跨越多个数据线的迹线段。在一个实施例中，每个跟踪段包括具有一个或多个指令的一个或多个跟踪段成员，每个跟踪段成员占据一个数据线，并且多行跟踪段的数据线被顺序地相关联（逻辑地）。通过首先定位存储跟踪段的第一跟踪段成员的数据线，然后基于数据连续定位存储剩余跟踪段成员的剩余数据线，来检索多行跟踪段的跟踪段成员行的逻辑顺序关联。

8. 发明授权

US09594648B2 Controlling non-redundant execution in a redundant multithreading (RMT) processor 有权
标题翻译：控制冗余多线程（RMT）处理器中的非冗余执行
公开(公告)号：US09594648B2
公开(公告)日：2017-03-14
申请号：US12317802
申请日：2008-12-30
申请人： Glenn J. Hinton , Steven E. Raasch , Sebastien Hily , John G. Holm , Ronak Singhal , Avinash Sodani , Deborah T. Marr
发明人： Glenn J. Hinton , Steven E. Raasch , Sebastien Hily , John G. Holm , Ronak Singhal , Avinash Sodani , Deborah T. Marr
IPC分类号： G06F9/38 , G06F11/16 , G06F9/30
CPC分类号： G06F11/1683 , G06F9/30189 , G06F9/3851 , G06F9/3857 , G06F9/3861 , G06F9/3891 , G06F11/1641 , G06F11/1658
摘要： In one embodiment, the present invention includes a method for controlling redundant execution such that if an exceptional event occurs, the redundant execution is stopped, non-redundant execution is performed in one of the threads until the exceptional event has been-resolved, after which a state of the threads is synchronized, and redundant execution is continued. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于控制冗余执行的方法，使得如果出现异常事件，则停止冗余执行，在其中一个线程中执行非冗余执行，直到异常事件被解析为止线程的状态被同步，并且继续冗余执行。描述和要求保护其他实施例。

9. 发明授权

US09141461B2 Machine check architecture execution environment for non-microcoded processor 有权
标题翻译：非微处理器的机器检查体系结构执行环境
公开(公告)号：US09141461B2
公开(公告)日：2015-09-22
申请号：US13924585
申请日：2013-06-23
申请人： Willam C. Rash , Scott D. Hanh , Glenn J. Hinton
发明人： Willam C. Rash , Scott D. Hanh , Glenn J. Hinton
IPC分类号： G06F11/00 , G06F11/07 , G06F11/14
CPC分类号： G06F11/0772 , G06F11/0724 , G06F11/1415 , G06F11/142 , G06F11/1443 , G06F2201/815
摘要： A technology for implementing a method for a machine check architecture environment. A method of the disclosure includes obtaining an occurrence of an error. The occurrence of the error causes a non-microcoded processing device to enter an error monitoring state. The method further processes the error using a dedicated memory portion for the error monitoring state while the non-microcoded processing device is in the error monitoring state. The error monitoring state is dedicated to error processing. The method further determines information associated with the error. The information associated with the error is in a predefined format.
摘要翻译：一种用于实现机器检查架构环境的方法的技术。本公开的方法包括获得错误的发生。错误的发生导致非微编码处理设备进入错误监视状态。该方法使用专用存储器部分处理错误，用于错误监视状态，而非微编码处理设备处于错误监视状态。错误监控状态专用于错误处理。该方法进一步确定与错误相关联的信息。与错误相关联的信息是预定义的格式。

10. 发明申请

US20130268728A1 APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCHY HAVING DIFFERENT OPERATING MODES 有权
标题翻译：用于实现具有不同操作模式的多级记忆层次的装置和方法
公开(公告)号：US20130268728A1
公开(公告)日：2013-10-10
申请号：US13994731
申请日：2011-09-30
申请人： Raj K. Ramanujan , Rajat Agarwal , Glenn J. Hinton
发明人： Raj K. Ramanujan , Rajat Agarwal , Glenn J. Hinton
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0246 , G06F12/0806 , G06F12/0808 , G06F12/0815 , G06F12/0888 , G06F12/0893 , G06F2212/205 , G06F2212/283 , G06F2212/6046 , G06F2212/621 , G06F2212/7201 , G11C7/1045 , G11C7/1072 , G11C13/0004 , G11C14/0045
摘要： A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.” In one embodiment, the “near memory” is configured to operate in a plurality of different modes of operation including (but not limited to) a first mode in which the near memory operates as a memory cache for the far memory and a second mode in which the near memory is allocated a first address range of a system address space with the far memory being allocated a second address range of the system address space, wherein the first range and second range represent the entire system address space.
摘要翻译：描述了用于集成包括计算机系统内的非易失性存储器层的存储器和存储层级的系统和方法。在一个实施例中，PCMS存储器件被用作层次结构中的一个层，有时被称为“远存储器”。更高性能的存储器件，例如放置在远存储器之前的DRAM，并用于掩盖远存储器的一些性能限制。这些更高性能的存储器件被称为“接近存储器”。在一个实施例中，“近存储器”被配置为以多种不同的操作模式操作，包括（但不限于）其中近端存储器作为远存储器的存储器高速缓存操作的第一模式，以及第二模式其中所述近存储器被分配有系统地址空间的第一地址范围，所述远存储器被分配了所述系统地址空间的第二地址范围，其中所述第一范围和第二范围表示整个系统地址空间。

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