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51. 发明申请

US20080124953A1 CIRCUIT PROTECTING STRUCTURE OF ELECTRONIC DEVICE 有权
标题翻译：电子设备电路保护结构
公开(公告)号：US20080124953A1
公开(公告)日：2008-05-29
申请号：US11737583
申请日：2007-04-19
申请人： Hung-Chang Hsieh , Ming-Ling Huang
发明人： Hung-Chang Hsieh , Ming-Ling Huang
IPC分类号： H05K1/00
CPC分类号： H05K9/0032 , G06F1/181 , G06F1/188
摘要： A circuit protecting structure of an electronic device includes a circuit carrier and a shielding member. The circuit carrier includes a first surface and a second surface. The second surface includes a specific region thereon. The shielding member includes a shielding frame and a shielding plate. The shielding frame is arranged on the second surface of the circuit carrier and encloses the specific region. The shielding plate is fixed onto the shielding frame. The shielding frame and the shielding plate cooperatively define a closed space for accommodating and shielding the specific region of the circuit carrier
摘要翻译：电子设备的电路保护结构包括电路载体和屏蔽构件。电路载体包括第一表面和第二表面。第二表面包括其上的特定区域。屏蔽构件包括屏蔽框架和屏蔽板。屏蔽框架布置在电路载体的第二表面上并且包围特定区域。屏蔽板固定在屏蔽框架上。屏蔽框架和屏蔽板协作地限定用于容纳和屏蔽电路载体的特定区域的封闭空间

52. 发明申请

US20080102379A1 Method for forming a robust mask with reduced light scattering 有权
标题翻译：用于形成具有减少的光散射的鲁棒掩模的方法
公开(公告)号：US20080102379A1
公开(公告)日：2008-05-01
申请号：US11590257
申请日：2006-10-31
申请人： Ken Wu , Hung-Chang Hsieh , Chang-Cheng Hung , Luke Hsu , Ren-Guey Hsieh , Hsin-Chang Lee , Chia-Jen Chen
发明人： Ken Wu , Hung-Chang Hsieh , Chang-Cheng Hung , Luke Hsu , Ren-Guey Hsieh , Hsin-Chang Lee , Chia-Jen Chen
IPC分类号： H01L21/00
CPC分类号： G03F7/70941 , G03F1/26 , G03F1/46 , G03F7/70433
摘要： A mask and method for forming the same including carrying out a photolithographic patterning process the method including providing a substantially light transparent portion; forming a substantially light shielding layer disposed over the substantially light transparent portion; forming at least one barrier layer disposed over the substantially light shielding layer; forming a resist layer disposed over the at least one barrier layer; patterning the resist layer for producing a circuitry pattern; and, carrying out an etching process according to the circuitry pattern to expose a portion of the substantially light transparent portion to form a mask.
摘要翻译：一种掩模及其形成方法，包括进行光刻图案处理，该方法包括提供基本上透明的部分; 形成设置在所述基本上透明部分上的基本上遮光层; 形成设置在所述基本上遮光层上的至少一个阻挡层; 形成设置在所述至少一个阻挡层上的抗蚀剂层; 图案化抗蚀剂层以产生电路图案; 并且根据电路图案进行蚀刻处理以暴露基本上光透明部分的一部分以形成掩模。

53. 发明申请

US20050195397A1 In-situ overlay alignment 有权
标题翻译：原位重叠对齐
公开(公告)号：US20050195397A1
公开(公告)日：2005-09-08
申请号：US10792147
申请日：2004-03-03
申请人： Grace Ho , Ming-Che Wu , Li-Heng Chou , Hung-Chang Hsieh , Jung Chen , Yao-Ching Ku
发明人： Grace Ho , Ming-Che Wu , Li-Heng Chou , Hung-Chang Hsieh , Jung Chen , Yao-Ching Ku
IPC分类号： G01B11/00 , G03F9/00
CPC分类号： G03F9/7084 , G03F7/70633
摘要： A semiconductor wafer is disclosed that includes a plurality of fields, including a plurality of alignment fields. Each alignment field includes a plurality of intra-field small scribe lane primary mark (SSPM) overlay mark pairs there around. The SSPM mark pairs allow for in-situ, non-passive intra-field alignment correction. In one embodiment, there may be between two and four alignment fields, and between two and four SSPM mark pairs around each alignment field. The SSPM marks of each mark pair may be extra scribe-lane marks.
摘要翻译：公开了一种半导体晶片，其包括多个场，包括多个对准场。每个对准场包括在其周围的多个场内小划线通道主标记（SSPM）覆盖标记对。 SSPM标记对允许原位，非被动场内对准校正。在一个实施例中，可以在两个和四个对准场之间以及围绕每个对准场的两个和四个SSPM标记对之间。每个标记对的SSPM标记可能是额外的划线标记。

54. 发明授权

US06858354B1 Method to prevent side lobe on seal ring 失效
标题翻译：防止旁瓣在密封圈上的方法
公开(公告)号：US06858354B1
公开(公告)日：2005-02-22
申请号：US10255482
申请日：2002-09-26
申请人： Hung-Chang Hsieh , Chang-Cheng Hung
发明人： Hung-Chang Hsieh , Chang-Cheng Hung
IPC分类号： G03F1/00 , G03F9/00 , H01L21/027
CPC分类号： G03F1/32 , G03F1/36
摘要： A new method is provided for the creation of a seal ring or fuse ring over the surface of a Phase Shift Mask. A seal ring pattern is created over the surface of a phase shift mask through a layer of phase shift material and a layer of opaque material. The seal ring is surrounded by a layer of opaque material by etching the layer of opaque material.
摘要翻译：提供了一种新的方法，用于在相移掩模的表面上创建密封圈或熔断环。通过相移材料层和不透明材料层在相移掩模的表面上形成密封圈图案。通过蚀刻不透明材料层，密封环被不透明材料层包围。

55. 发明授权

US06362093B1 Dual damascene method employing sacrificial via fill layer 有权
公开(公告)号：US06362093B1
公开(公告)日：2002-03-26
申请号：US09378459
申请日：1999-08-20
申请人： Syun-Ming Jang , Anthony Yen , Hung-Chang Hsieh
发明人： Syun-Ming Jang , Anthony Yen , Hung-Chang Hsieh
IPC分类号： H01L214763
CPC分类号： H01L21/76808
摘要： A method for forming through a microelectronic layer a via contiguous with a trench. There is first provided a substrate. There is then formed over the substrate a first microelectronic layer. There is then formed upon the first microelectronic layer an etch stop layer. There is then formed upon the etch stop layer a second microelectronic layer. There is then formed over the second microelectronic layer a first patterned photoresist layer which defines the location of a via to be formed through the second microelectronic layer, the etch stop layer and the first microelectronic layer. There is then etched, while employing a first etch method which employs the first patterned photoresist layer as a first etch mask layer, the second microelectronic layer, the etch stop layer and the first microelectronic layer to form a corresponding patterned second microelectronic layer, patterned etch stop layer and patterned first microelectronic layer which define the via. There is then formed into at least a lower portion of the via a sacrificial via fill layer. There is then formed over the patterned second microelectronic layer a patterned second photoresist layer which defines the location of a trench to be formed through the patterned second microelectronic layer, where a first areal dimension of the via is smaller than and contained within a second areal dimension of the trench. There is then etched, while employing a second etch method which employs the second patterned photoresist layer as a second etch mask layer, the patterned second microelectronic layer to form a twice patterned second microelectronic layer which defines the trench, while not completely etching the sacrificial via fill layer within the via to form a no greater than partially etched sacrificial via fill layer within the via. Finally, there is then stripped the no greater than partially etched sacrificial via fill layer from the via to form the reduced height via contiguous with the trench.

56. 发明授权

US06174818B1 Method of patterning narrow gate electrode 有权
标题翻译：窄栅电极图案方法
公开(公告)号：US06174818B1
公开(公告)日：2001-01-16
申请号：US09443424
申请日：1999-11-19
申请人： Hun-Jan Tao , Huan-Just Lin , Hung-Chang Hsieh , Chu-Yun Fu , Ying-Ying Wang , Chia-Shiung Tsai , Fang-Cheng Chen
发明人： Hun-Jan Tao , Huan-Just Lin , Hung-Chang Hsieh , Chu-Yun Fu , Ying-Ying Wang , Chia-Shiung Tsai , Fang-Cheng Chen
IPC分类号： H01L21302
CPC分类号： H01L21/0276 , H01L21/0332 , H01L21/28123 , H01L21/32139
摘要： A process is described for forming very narrow polysilicon gate lines for use as gate electrodes in FETs. The process uses a consumable hard mask of silicon oxynitride covered by a thin layer of silicon oxide during the etching of the polysilicon. The thicknesses of the two layers that make up the hard mask are chosen so that the structure also serves as an ARC for the photoresist coating immediately above it. A relatively thin layer of the latter is used in order to improve resolution. After the photoresist has been patterned it may be trimmed or it may be removed and re-formed, since the silicon oxide layer provides protection for the underlying silicon oxynitride. After the hard mask has been formed, all photoresist is removed and the polysilicon is etched. During etching there is simultaneous removal of the silicon oxide layer and part of the silicon oxynitride as well.
摘要翻译：描述了用于形成用于FET中的栅电极的非常窄的多晶硅栅极线的工艺。该方法在蚀刻多晶硅期间使用由氧化硅薄层覆盖的氮氧化硅的消耗性硬掩模。选择构成硬掩模的两层的厚度，使得该结构也用作其上方的光致抗蚀剂涂层的ARC。为了提高分辨率，使用后者的较薄层。在光致抗蚀剂被图案化之后，可以对其进行修整或者可以将其去除并重新形成，因为氧化硅层为下面的氮氧化硅提供保护。在形成硬掩模之后，除去所有光致抗蚀剂并蚀刻多晶硅。在蚀刻期间，同时去除氧化硅层和部分氮氧化硅。

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