专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20180294234A1 MODULE AND METHOD OF A SELECTIVE ELECTRONIC-MAGNETIC INTERFERENCE SHIELDING 审中-公开
公开(公告)号：US20180294234A1
公开(公告)日：2018-10-11
申请号：US15816213
申请日：2017-11-17
申请人： Ming-Che WU
发明人： Ming-Che WU
IPC分类号： H01L23/552 , H01L23/31 , H01L21/3205
摘要： Module and method of a selective electronic-magnetic interference shielding includes a substrate, at least a first electronic element deployed on a principle surface of the substrate, an mold resin covering the first electronic element, and an electronic-magnetic interference shielding, wherein the mold resin has a mold surface relatively far above the substrate and is divided into a central area and an outer area surrounding the central area. The mold resin installs a trench between the central area and the outer area, the trench forms a closed route enfolding the first electronic element, and the electro-magnetic interference shielding distributes over the central area and the trench. Therefore the module and method of a selective electronic-magnetic interference shielding is adaptable to various required designs with lower manufacturing cost.

2. 发明授权

US08813354B2 Method of manufacturing an electromagnetic shielding structure 有权
标题翻译：制造电磁屏蔽结构的方法
公开(公告)号：US08813354B2
公开(公告)日：2014-08-26
申请号：US13195087
申请日：2011-08-01
申请人： Ming-Che Wu
发明人： Ming-Che Wu
IPC分类号： H05K3/30 , H05K9/00 , H01L23/552 , H01L25/065
CPC分类号： H05K9/003 , H01L23/552 , H01L25/0655 , H01L2924/0002 , Y10T29/49126 , Y10T29/4913 , Y10T29/49144 , Y10T29/49155 , Y10T29/49227 , H01L2924/00
摘要： An electromagnetic interference (EMI) shielding structure, which includes: a substrate, at least one chip unit, a packing layer, and an EMI shielding unit. The chip unit is disposed on the surface of the substrate and electrically coupled thereto. The packing layer is formed on the substrate and covers the chip unit. The EMI shielding unit includes: a first, second, and third shielding layer. The first shielding layer covers the outer surface of the packing layer and the lateral surface of the substrate. The second and third shielding layer respectively covers the outer surface of the first and second shielding layer. Based on the instant disclosure, the EMI shielding unit uses the methods of sputtering and electroless plating, to increase the adhesion strength of the EMI shielding unit and make the thickness of the shielding layer uniform. The instant disclosure raises the EMI shielding efficiency and lowers the manufacturing cost.
摘要翻译：一种电磁干扰（EMI）屏蔽结构，其包括：衬底，至少一个芯片单元，封装层和EMI屏蔽单元。芯片单元设置在基板的表面上并与其电耦合。填充层形成在基板上并覆盖芯片单元。 EMI屏蔽单元包括：第一，第二和第三屏蔽层。第一屏蔽层覆盖填料层的外表面和基材的侧表面。第二和第三屏蔽层分别覆盖第一和第二屏蔽层的外表面。基于本公开，EMI屏蔽单元使用溅射和化学镀的方法来增加EMI屏蔽单元的粘合强度并使屏蔽层的厚度均匀。本公开提出了EMI屏蔽效率并降低了制造成本。

3. 发明授权

US08342707B2 Multi-wavelength light-emitting module 有权
公开(公告)号：US08342707B2
公开(公告)日：2013-01-01
申请号：US12071112
申请日：2008-02-15
申请人： Ming-Che Wu
发明人： Ming-Che Wu
IPC分类号： F21V9/00
CPC分类号： B41J2/45 , H01L24/24 , H01L24/73 , H01L24/82 , H01L25/167 , H01L2224/04105 , H01L2224/24137 , H01L2224/24145 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2224/73267 , H01L2224/92244 , H01L2924/10157 , H01L2924/12041 , H01L2924/14 , H01L2924/15153 , H01L2924/19107 , H01L2924/00012 , H01L2924/00
摘要： A multi-wavelength light-emitting module that includes a PCB, a drive IC structure, a conductive structure, a multi-wavelength LED array set, a plurality of conductive elements, and an optical amplifier structure. The PCB has at least one input/output pad. The drive IC structure is disposed on the PCB and having at least one concave groove formed on top surface thereof. The conductive structure is electrically connected between the drive IC structure and the at least one input/output pad. The multi-wavelength LED array set is received in the at least one concave groove. The conductive elements are electrically connected between drive IC structure and the multi-wavelength LED array set, respectively. The optical amplifier structure is disposed over the multi-wavelength LED array set for receiving light sources from the multi-wavelength LED array set.

4. 发明申请

US20120248585A1 ELECTROMAGNETIC INTERFERENCE SHIELDING STRUCTURE FOR INTEGRATED CIRCUIT SUBSTRATE AND METHOD FOR FABRICATING THE SAME 审中-公开
标题翻译：集成电路基板的电磁干扰屏蔽结构及其制作方法
公开(公告)号：US20120248585A1
公开(公告)日：2012-10-04
申请号：US13099559
申请日：2011-05-03
申请人： MING-CHE WU
发明人： MING-CHE WU
IPC分类号： H01L23/552 , H01L21/768
CPC分类号： H01L23/552 , H01L23/3121 , H01L23/49805 , H01L24/16 , H01L25/0655 , H01L2224/16225 , H01L2924/12042 , H01L2924/1421 , H01L2924/15311 , H01L2924/1815 , H01L2924/19105 , H01L2924/00
摘要： An electromagnetic interference (EMI) shielding structure for integrated circuit (IC) substrate includes a plurality of conductive contacts, a covering layer, and a sputtered layer. The conductive contacts are formed at the perimeter of a chip area on the IC substrate. The covering layer is formed on the conductive contacts and covers the chip area. A groove is formed on the covering layer for exposing the conductive contacts. The sputtered layer is formed on the covering layer and connected to the conductive contacts. The EMI shielding structure can restrain the interference in the chip area.
摘要翻译：用于集成电路（IC）衬底的电磁干扰（EMI）屏蔽结构包括多个导电触点，覆盖层和溅射层。导电触头形成在IC基板上的芯片区域的周边。覆盖层形成在导电触点上并覆盖芯片区域。在覆盖层上形成用于暴露导电触点的沟槽。溅射层形成在覆盖层上并连接到导电触头。 EMI屏蔽结构可以抑制芯片区域的干扰。

5. 发明申请

US20120074593A1 CHIP STACKED STRUCTURE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：芯片堆叠结构及其制造方法
公开(公告)号：US20120074593A1
公开(公告)日：2012-03-29
申请号：US13072951
申请日：2011-03-28
申请人： MING-CHE WU
发明人： MING-CHE WU
IPC分类号： H01L23/48 , H01L21/50
CPC分类号： H01L25/50 , H01L21/76898 , H01L23/481 , H01L25/0657 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2225/06551 , H01L2924/09701
摘要： A chip stacked structure and method of fabricating the same are provided. The chip stacked structure includes a first chip and a second chip stacked on the first chip. The first chip has a plurality of metal pads disposed on an upper surface thereof and grooves disposed on a side surface thereof. The metal pads are correspondingly connected to upper openings of the grooves. The second chip has a plurality of grooves on a side surface of the second chip, locations of which are corresponding to that of the grooves on the side surface of the first chip. Conductive films are formed on the grooves of the first chip and the second chip and the metal pads to electronically connect the first chip and second chip. The chip stacked structure may simplify the process and improve the process yield rate.
摘要翻译：提供了一种芯片堆叠结构及其制造方法。芯片堆叠结构包括堆叠在第一芯片上的第一芯片和第二芯片。第一芯片具有设置在其上表面上的多个金属焊盘和设置在其侧表面上的槽。金属焊盘相应地连接到槽的上部开口。第二芯片在第二芯片的侧表面上具有多个凹槽，其位置对应于第一芯片侧表面上的凹槽。导电膜形成在第一芯片和第二芯片的沟槽和金属焊盘上以电连接第一芯片和第二芯片。芯片堆叠结构可以简化工艺，提高工艺成品率。

6. 发明授权

US07759687B2 Multi-wavelength LED array package module and method for packaging the same 失效
标题翻译：多波长LED阵列封装模块及其封装方法相同
公开(公告)号：US07759687B2
公开(公告)日：2010-07-20
申请号：US12003689
申请日：2007-12-31
申请人： Ming-Che Wu
发明人： Ming-Che Wu
IPC分类号： H01L29/20
CPC分类号： B41J2/45
摘要： A method for packaging a multi-wavelength LED array package module includes: forming at least one concave groove on a drive IC structure; arranging a multi-wavelength LED array set in the at least one concave groove; solidifying a plurality of liquid conductive materials to form a plurality of conductive elements that is electrically connected between the drive IC structure and the multi-wavelength LED array set by a printing, a coating, a stamping, or a stencil printing process; arranging the drive IC structure on a PCB with at least one input/output pad; and then forming a conductive structure that is electrically connected between the drive IC structure and the at least one input/output pad.
摘要翻译：一种用于封装多波长LED阵列封装模块的方法包括：在驱动IC结构上形成至少一个凹槽; 布置在所述至少一个凹槽中的多波长LED阵列; 固化多个液体导电材料以形成电连接在驱动IC结构和通过印刷，涂层，冲压或模版印刷工艺组合的多波长LED阵列之间的多个导电元件; 将驱动IC结构布置在具有至少一个输入/输出垫的PCB上; 然后形成电连接在驱动IC结构和至少一个输入/输出焊盘之间的导电结构。

7. 发明申请

US20100001295A1 Embedded package structure module with high-density electrical connections and method for making the same 有权
标题翻译：具有高密度电气连接的嵌入式封装结构模块和制造相同的方法
公开(公告)号：US20100001295A1
公开(公告)日：2010-01-07
申请号：US12216397
申请日：2008-07-03
申请人： Ming-Che Wu
发明人： Ming-Che Wu
IPC分类号： H01L33/00
CPC分类号： B41J2/45
摘要： An embedded package structure module with high-density electrical connections, including: a drive IC structure, an LED array structure and a plurality of conductive structures. The drive IC structure has at least one concave groove. The LED array structure is received in the at least one concave groove of the drive IC structure, and the LED array structure has a plurality of second open grooves formed on its lateral wall and close to the drive IC structure. The conductive structures respectively traverse the second open grooves in order to make the conductive structures electrically connect between the drive IC structure and the LED array structure.
摘要翻译：一种具有高密度电连接的嵌入式封装结构模块，包括：驱动IC结构，LED阵列结构和多个导电结构。驱动IC结构具有至少一个凹槽。 LED阵列结构被容纳在驱动IC结构的至少一个凹槽中，并且LED阵列结构具有形成在其侧壁上且靠近驱动IC结构的多个第二开放槽。导电结构分别穿过第二开槽，以使导电结构在驱动IC结构和LED阵列结构之间电连接。

8. 发明申请

US20090189949A1 METHOD FOR ARRANGING PRINT HEAD CHIPS 失效
标题翻译：打印头盖的方法
公开(公告)号：US20090189949A1
公开(公告)日：2009-07-30
申请号：US12010664
申请日：2008-01-29
申请人： Ming-Che Wu
发明人： Ming-Che Wu
IPC分类号： B41J2/45 , B41J2/145 , H05K3/30 , B41J2/16
CPC分类号： B41J2/145 , B41J2/45 , B41J2202/19 , B41J2202/20 , H05K1/0269 , H05K3/303 , H05K3/328 , H05K2201/09918 , H05K2201/10106 , H05K2203/049 , Y10T29/4913 , Y10T29/49401
摘要： A method for arranging print head chips, includes: (a) setting a first fiducial mark and a second fiducial mark on a PCB for determining coordinate positions of a plurality of array units that are arranged on the PCB and calculating a print range of the array units, wherein each array unit has a plurality of spots that are transversely arranged from the first one of the spots to the last one of the spots in sequence; (b) setting a third fiducial mark as a start point for arranging the first spot of a first array unit of the array units on the PCB; and (c) arranging other array units on the PCB in sequence according to the coordinate positions and the start point.
摘要翻译：一种用于布置打印头芯片的方法，包括：（a）在PCB上设置第一基准标记和第二基准标记，以确定布置在PCB上的多个阵列单元的坐标位置，并计算阵列的打印范围单元，其中每个阵列单元具有从序列中的第一个点到最后一个点横向布置的多个点; （b）将第三基准标记设置为用于将阵列单元的第一阵列单元的第一点布置在PCB上的起始点; 和（c）根据坐标位置和起始点依次排列PCB上的其它阵列单元。

9. 发明申请

US20090184332A1 Package structure module with high density electrical connections and method for packaging the same 审中-公开
标题翻译：封装结构模块具有高密度电气连接和封装方法
公开(公告)号：US20090184332A1
公开(公告)日：2009-07-23
申请号：US12010235
申请日：2008-01-23
申请人： Ming-Che Wu
发明人： Ming-Che Wu
IPC分类号： H01L33/00
CPC分类号： H01L25/167 , B41J2/45 , H01L24/24 , H01L24/73 , H01L27/153 , H01L2924/12041 , H01L2924/14 , H05K1/142 , H05K3/3405 , H05K3/3442 , H05K3/36 , H05K2203/1527 , H01L2224/48091 , H01L2924/00014 , H01L2924/00
摘要： A package structure module with high density electrical connections includes a drive IC structure, an LED array structure, and a plurality of conductive structures. The drive IC structure has a plurality of first open grooves formed on a lateral wall thereof. The LED array structure has a plurality of second open grooves formed on a lateral wall thereof to respectively face the first open grooves. Each conductive structure traverse the corresponding first open groove and the corresponding second open groove in order to electrically connect between the drive IC structure and the LED array structure.
摘要翻译：具有高密度电连接的封装结构模块包括驱动IC结构，LED阵列结构和多个导电结构。驱动IC结构具有形成在其侧壁上的多个第一开槽。 LED阵列结构具有形成在其侧壁上的多个第二开放槽，以分别面对第一开放槽。每个导电结构横穿相应的第一开槽和对应的第二开槽，以便电连接驱动IC结构和LED阵列结构。

10. 发明授权

US07218400B2 In-situ overlay alignment 有权
标题翻译：原位重叠对齐
公开(公告)号：US07218400B2
公开(公告)日：2007-05-15
申请号：US10792147
申请日：2004-03-03
申请人： Grace H. Ho , Ming-Che Wu , Li-Heng Chou , Hung-Chang Hsieh , Jung Ting Chen , Yao-Ching Ku
发明人： Grace H. Ho , Ming-Che Wu , Li-Heng Chou , Hung-Chang Hsieh , Jung Ting Chen , Yao-Ching Ku
IPC分类号： G01B11/00
CPC分类号： G03F9/7084 , G03F7/70633
摘要： A semiconductor wafer is disclosed that includes a plurality of fields, including a plurality of alignment fields. Each alignment field includes a plurality of intra-field small scribe lane primary mark (SSPM) overlay mark pairs there around. The SSPM mark pairs allow for in-situ, non-passive intra-field alignment correction. In one embodiment, there may be between two and four alignment fields, and between two and four SSPM mark pairs around each alignment field. The SSPM marks of each mark pair may be extra scribe-lane marks.
摘要翻译：公开了一种半导体晶片，其包括多个场，包括多个对准场。每个对准场包括在其周围的多个场内小划线通道主标记（SSPM）覆盖标记对。 SSPM标记对允许原位，非被动场内对准校正。在一个实施例中，可以在两个和四个对准场之间以及围绕每个对准场的两个和四个SSPM标记对之间。每个标记对的SSPM标记可能是额外的划线标记。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式