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1. 发明授权

US06174818B1 Method of patterning narrow gate electrode 有权
标题翻译：窄栅电极图案方法
公开(公告)号：US06174818B1
公开(公告)日：2001-01-16
申请号：US09443424
申请日：1999-11-19
申请人： Hun-Jan Tao , Huan-Just Lin , Hung-Chang Hsieh , Chu-Yun Fu , Ying-Ying Wang , Chia-Shiung Tsai , Fang-Cheng Chen
发明人： Hun-Jan Tao , Huan-Just Lin , Hung-Chang Hsieh , Chu-Yun Fu , Ying-Ying Wang , Chia-Shiung Tsai , Fang-Cheng Chen
IPC分类号： H01L21302
CPC分类号： H01L21/0276 , H01L21/0332 , H01L21/28123 , H01L21/32139
摘要： A process is described for forming very narrow polysilicon gate lines for use as gate electrodes in FETs. The process uses a consumable hard mask of silicon oxynitride covered by a thin layer of silicon oxide during the etching of the polysilicon. The thicknesses of the two layers that make up the hard mask are chosen so that the structure also serves as an ARC for the photoresist coating immediately above it. A relatively thin layer of the latter is used in order to improve resolution. After the photoresist has been patterned it may be trimmed or it may be removed and re-formed, since the silicon oxide layer provides protection for the underlying silicon oxynitride. After the hard mask has been formed, all photoresist is removed and the polysilicon is etched. During etching there is simultaneous removal of the silicon oxide layer and part of the silicon oxynitride as well.
摘要翻译：描述了用于形成用于FET中的栅电极的非常窄的多晶硅栅极线的工艺。该方法在蚀刻多晶硅期间使用由氧化硅薄层覆盖的氮氧化硅的消耗性硬掩模。选择构成硬掩模的两层的厚度，使得该结构也用作其上方的光致抗蚀剂涂层的ARC。为了提高分辨率，使用后者的较薄层。在光致抗蚀剂被图案化之后，可以对其进行修整或者可以将其去除并重新形成，因为氧化硅层为下面的氮氧化硅提供保护。在形成硬掩模之后，除去所有光致抗蚀剂并蚀刻多晶硅。在蚀刻期间，同时去除氧化硅层和部分氮氧化硅。

2. 发明授权

US06497993B1 In situ dry etching procedure to form a borderless contact hole 有权
标题翻译：原位干蚀刻工艺形成无边界接触孔
公开(公告)号：US06497993B1
公开(公告)日：2002-12-24
申请号：US09614010
申请日：2000-07-11
申请人： Yuan-Hunh Chiu , Hun-Jan Tao , Chia-Shiung Tsai , Chu-Yun Fu
发明人： Yuan-Hunh Chiu , Hun-Jan Tao , Chia-Shiung Tsai , Chu-Yun Fu
IPC分类号： G03F736
CPC分类号： H01L21/76802 , H01L21/31116
摘要： A process for forming a contact hole opening, featuring the use in situ dry etching, and photoresist removal procedures, used to define the desired contact hole opening; in an overlying hard mask layer, in the dielectric layer, and in an underlying insulator stop layer, has been developed. The process features the initial definition of the contact hole opening, in an overlying hard mask insulator layer, accomplished in a chamber of a dry etch tool, followed by removal of an overlying, contact hole defining photoresist shape, performed in situ, in the same dry etch chamber. The contact hole opening is then transferred to the dielectric layer via a selective dry etch procedure, performed in situ, in the dry etch chamber, using the overlying hard mask insulator layer as an etch mask. A final dry etch procedure is then performed in situ, in the same dry etch chamber, to form the contact hole opening in the underlying insulator stop layer, with the final dry etch procedure also resulting in the removal of the exposed hard mask insulator layer, thus creating the desired contact hole opening in a dielectric layer, and in the underlying insulator stop layer.
摘要翻译：用于形成接触孔开口的方法，其特征在于使用原位干蚀刻和光致抗蚀剂去除程序，用于限定所需的接触孔开口; 在覆盖的硬掩模层，电介质层和下面的绝缘体停止层中已经开发出来。该方法具有接触孔开口的初始定义，在覆盖的硬掩模绝缘体层中，在干蚀刻工具的腔室中完成，随后除去在相同的位置原位执行限定光致抗蚀剂形状的上覆接触孔干蚀刻室。接触孔开口然后通过选择性干蚀刻方法，在干蚀刻室中原位进行，使用覆盖的硬掩模绝缘体层作为蚀刻掩模转移到电介质层。然后在相同的干蚀刻室中原位进行最终的干蚀刻工艺，以在下面的绝缘体停止层中形成接触孔开口，最终的干法蚀刻程序也导致暴露的硬掩模绝缘体层的去除，从而在电介质层中和在下面的绝缘体停止层中产生所需的接触孔开口。

3. 发明授权

US6063711A High selectivity etching stop layer for damascene process 失效
标题翻译：用于镶嵌工艺的高选择性蚀刻停止层
公开(公告)号：US6063711A
公开(公告)日：2000-05-16
申请号：US69456
申请日：1998-04-28
申请人： Li-Chih Chao , Chia-Shiung Tsai , Chu-Yun Fu , Jhon-Jhy Liaw
发明人： Li-Chih Chao , Chia-Shiung Tsai , Chu-Yun Fu , Jhon-Jhy Liaw
IPC分类号： H01L21/768 , H01L21/304 , B24B1/00 , H01L21/461
CPC分类号： H01L21/7681 , H01L21/76807
摘要： A high selectivity etch-stop layer comprising oxynitride is disclosed for forming damascene structures in the manufacturing of semiconductor substrates. Because of its relatively high selectivity to oxides, the oxynitride etch-stop can be made thinner than the conventionally used nitride layer. Therefore, the disclosed oxynitride etch-stop layer makes it possible to avoid the cracking problems of thicker etch-stop layers as well as the associated problems of poor definition of contact or via holes in the damascene structure.
摘要翻译：公开了一种包括氮氧化物的高选择性蚀刻停止层，用于在半导体衬底的制造中形成镶嵌结构。由于氧化物的选择性相对较高，氧氮化物蚀刻停止可以比常规使用的氮化物层薄。因此，所公开的氧氮化物蚀刻停止层使得可以避免较厚的蚀刻停止层的破裂问题以及相似的在镶嵌结构中接触或通孔的定义不良的问题。

4. 发明授权

US08110890B2 Method of fabricating semiconductor device isolation structure 有权
标题翻译：制造半导体器件隔离结构的方法
公开(公告)号：US08110890B2
公开(公告)日：2012-02-07
申请号：US11758043
申请日：2007-06-05
申请人： Chen-Hua Yu , Chen-Nan Yeh , Chu-Yun Fu , Ding-Yuan Chen
发明人： Chen-Hua Yu , Chen-Nan Yeh , Chu-Yun Fu , Ding-Yuan Chen
IPC分类号： H01L21/70
CPC分类号： H01L21/76202 , H01L21/26506 , H01L21/26533 , H01L21/26586 , H01L21/266 , H01L21/324 , H01L21/762 , H01L21/823481 , H01L29/0649 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device including reentrant isolation structures and a method for making such a device. A preferred embodiment comprises a substrate of semiconductor material forming at least one isolation structure having a reentrant profile and isolating one or more adjacent operational components. The reentrant profile of the at least one isolation structure is formed of substrate material and is created by ion implantation, preferably using oxygen ions applied at a number of different angles and energy levels. In another embodiment the present invention is a method of forming an isolation structure for a semiconductor device performing at least one oxygen ion implantation.
摘要翻译：包括可折入隔离结构的半导体器件和用于制造这种器件的方法。优选实施例包括形成至少一个隔离结构的半导体材料的衬底，该隔离结构具有折返轮廓并且隔离一个或多个相邻的操作部件。至少一个隔离结构的折返轮廓由衬底材料形成，并且通过离子注入产生，优选地使用以多个不同角度和能级施加的氧离子。在另一个实施方案中，本发明是形成用于进行至少一个氧离子注入的半导体器件的隔离结构的方法。

5. 发明申请

US20080194087A1 Polysilicon gate formation by in-situ doping 有权
公开(公告)号：US20080194087A1
公开(公告)日：2008-08-14
申请号：US11729009
申请日：2007-03-28
申请人： Chen-Hua Yu , Ding-Yuan Chen , Chu-Yun Fu , Liang-Gi Yao , Chen-Nan Yeh
发明人： Chen-Hua Yu , Ding-Yuan Chen , Chu-Yun Fu , Liang-Gi Yao , Chen-Nan Yeh
IPC分类号： H01L21/3205 , H01L21/22 , H01L21/38
CPC分类号： H01L29/7834 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L29/165 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate; forming a first silicon-containing layer on the gate dielectric layer, wherein the first silicon-containing layer is substantially free from p-type and n-type impurities; forming a second silicon-containing layer over the first silicon-containing layer, wherein the second silicon-containing layer comprises an impurity; and performing an annealing to diffuse the impurity in the second silicon-containing layer into the first silicon-containing layer.

6. 发明申请

US20080194072A1 Polysilicon gate formation by in-situ doping 审中-公开
标题翻译：通过原位掺杂形成多晶硅栅
公开(公告)号：US20080194072A1
公开(公告)日：2008-08-14
申请号：US11705655
申请日：2007-02-12
申请人： Chen-Hua Yu , Ding-Yuan Chen , Chu-Yun Fu , Liang-Gi Yao , Chen-Nan Yeh
发明人： Chen-Hua Yu , Ding-Yuan Chen , Chu-Yun Fu , Liang-Gi Yao , Chen-Nan Yeh
IPC分类号： H01L21/336
CPC分类号： H01L21/82345 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L29/165 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7848
摘要： A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate; forming a first silicon-containing layer on the gate dielectric layer, wherein the first silicon-containing layer is substantially free from p-type and n-type impurities; forming a second silicon-containing layer over the first silicon-containing layer, wherein the second silicon-containing layer comprises an impurity; and performing an annealing to diffuse the impurity in the second silicon-containing layer into the first silicon-containing layer.
摘要翻译：一种形成半导体结构的方法包括提供半导体衬底; 在所述半导体衬底上形成栅介电层; 在所述栅极电介质层上形成第一含硅层，其中所述第一含硅层基本上不含p型和n型杂质; 在所述第一含硅层上形成第二含硅层，其中所述第二含硅层包含杂质; 并进行退火以将第二含硅层中的杂质扩散到第一含硅层中。

7. 发明授权

US06365523B1 Integrated high density plasma chemical vapor deposition (HDP-CVD) method and chemical mechanical polish (CMP) planarizing method for forming patterned planarized aperture fill layers 有权
标题翻译：集成高密度等离子体化学气相沉积（HDP-CVD）方法和用于形成图案化平面化孔径填充层的化学机械抛光（CMP）平面化方法
公开(公告)号：US06365523B1
公开(公告)日：2002-04-02
申请号：US09177188
申请日：1998-10-22
申请人： Syun-Ming Jang , Chu-Yun Fu , Ying-Ho Chen
发明人： Syun-Ming Jang , Chu-Yun Fu , Ying-Ho Chen
IPC分类号： H01L21302
CPC分类号： H01L21/76229 , H01L21/31053 , H01L21/31612
摘要： A method for forming a series of patterned planarized aperture fill layers within a series of apertures within a topographic substrate layer employed within a microelectronics fabrication. There is first provided a topographic substrate layer employed within a microelectronics fabrication, where the topographic substrate layer comprises a series of mesas of substantially equivalent height but of differing widths and the series of mesas is separated by a series of apertures. There is then formed upon the topographic substrate layer a blanket first aperture fill layer. The blanket first aperture fill layer is formed employing a first simultaneous deposition and sputter method. The blanket first aperture fill layer fills the series of apertures to a planarizing thickness at least as high as the height of the mesas while simultaneously forming a series of protrusions of the blanket first aperture fill layer corresponding with the series of mesas, where the thickness of a protrusion of the blanket first aperture fill layer over a narrow mesa is less than the thickness of a protrusion of the blanket first aperture fill layer over a wide mesa. The first simultaneous deposition and sputter method employs a first deposition rate:sputter rate ratio which provides sufficient thickness of the blanket first aperture fill layer over the narrow mesa such that upon chemical mechanical polish (CMP) planarizing the blanket first aperture fill layer to form a series of patterned planarized first aperture fill layers within the series of apertures erosion of the narrow mesa is attenuated. Finally, there is then chemical mechanical polish (CMP) planarized the blanket first aperture fill layer to form the series of patterned planarized first aperture fill layers within the series of apertures.
摘要翻译：一种用于在微电子学制造中使用的地形衬底层内的一系列孔内形成一系列图案化的平坦化孔填充层的方法。首先提供了在微电子制造中使用的地形衬底层，其中地形衬底层包括基本上等同的高度但具有不同宽度的一系列台面，并且一系列台面由一系列孔分隔开。然后在地形衬底层上形成毯子第一孔填充层。毯子第一孔填充层使用第一同时沉积和溅射方法形成。毯子第一孔填充层将一系列孔填充至至少与台面的高度相同的平坦化厚度，同时形成与一系列台面相对应的毯子第一孔填充层的一系列突起，其中厚度毯子第一孔填充层在窄台面上的突起小于宽台面上的第一孔填充层的突起的厚度。第一同时沉积和溅射方法使用第一沉积速率：溅射速率比，其在窄台面上提供足够厚度的第一孔填充层，使得在化学机械抛光（CMP）上平坦化第一孔填充层以形成一系列图案化的平面化的第一孔径填充层在一系列孔径内的狭窄台面的侵蚀被衰减。最后，然后是化学机械抛光（CMP）平坦化第一孔填充层，以在一系列孔内形成一系列图案化的平坦化的第一孔填充层。

8. 发明授权

US07611963B1 Method for forming a multi-layer shallow trench isolation structure in a semiconductor device 有权
标题翻译：在半导体器件中形成多层浅沟槽隔离结构的方法
公开(公告)号：US07611963B1
公开(公告)日：2009-11-03
申请号：US12111355
申请日：2008-04-29
申请人： Shu-Tine Yang , Chen-Hua Yu , Chu-Yun Fu
发明人： Shu-Tine Yang , Chen-Hua Yu , Chu-Yun Fu
IPC分类号： H01L21/301
CPC分类号： H01L21/76224
摘要： A method for forming a multi-layer shallow trench isolation structure in a semiconductor device is described. In one embodiment, the method includes etching a shallow trench in a silicon substrate of a semiconductor device and forming a dielectric liner layer on a floor and walls of the shallow trench. The method further includes forming a first doped oxide layer in the shallow trench, the first layer formed by vapor deposition of precursors including a source of silicon, a source of oxygen, and sources of doping materials at a first processing condition and forming a second doped oxide layer above the first doped oxide layer by vapor deposition using precursors of silicon and doping materials, at a second processing condition, different from the first processing condition.
摘要翻译：描述了在半导体器件中形成多层浅沟槽隔离结构的方法。在一个实施例中，该方法包括蚀刻半导体器件的硅衬底中的浅沟槽，并在浅沟槽的地板和壁上形成介电衬垫层。该方法还包括在浅沟槽中形成第一掺杂氧化物层，第一层通过在第一处理条件下气相沉积包括硅源，氧源和掺杂源的前体形成，并形成第二掺杂氧化物层，其通过使用硅和掺杂材料的前体的气相沉积，在与第一处理条件不同的第二处理条件下进行。

9. 发明申请

US20060211250A1 Scratch reduction for chemical mechanical polishing 有权
标题翻译：化学机械抛光刮刮
公开(公告)号：US20060211250A1
公开(公告)日：2006-09-21
申请号：US11082517
申请日：2005-03-17
申请人： Chuang-Ping Hou , Syun-Ming Jang , Ying-Ho Chen , Chu-Yun Fu , Tung-Ching Tseng
发明人： Chuang-Ping Hou , Syun-Ming Jang , Ying-Ho Chen , Chu-Yun Fu , Tung-Ching Tseng
IPC分类号： H01L21/461 , H01L21/302
CPC分类号： H01L21/31053
摘要： A method for forming a semiconductor device utilizing a chemical-mechanical polishing (CMP) process is provided. In one example, the method includes sequentially performing a first CMP process for removing a first portion of an oxide surface of a semiconductor device using a high selectivity slurry (HSS) and a first polish pad, interrupting the first CMP process, cleaning the semiconductor device and the first polish pad, and performing a second CMP process for removing a second portion of the oxide surface.
摘要翻译：提供了一种利用化学机械抛光（CMP）工艺形成半导体器件的方法。在一个示例中，该方法包括依次执行第一CMP处理，以使用高选择性浆料（HSS）和第一抛光垫去除半导体器件的氧化物表面的第一部分，中断第一CMP工艺，清洁半导体器件和第一抛光垫，并且执行用于去除氧化物表面的第二部分的第二CMP工艺。

10. 发明授权

US06461966B1 Method of high density plasma phosphosilicate glass process on pre-metal dielectric application for plasma damage reducing and throughput improvement 有权
标题翻译：高密度等离子体磷硅酸盐玻璃工艺对金属前介电应用的方法，用于等离子体损伤降低和生产率提高
公开(公告)号：US06461966B1
公开(公告)日：2002-10-08
申请号：US10017954
申请日：2001-12-14
申请人： Yao-Hsiang Chen , Chu-Yun Fu , Syung-Ming Jang
发明人： Yao-Hsiang Chen , Chu-Yun Fu , Syung-Ming Jang
IPC分类号： H01L21311
CPC分类号： H01L21/02274 , H01L21/02129 , H01L21/02164 , H01L21/31625
摘要： A method of forming a composite dielectric layer comprising the following steps. A structure having at least two semiconductor structures separated by a gap therebetween is provided. A first dielectric layer is formed over the structure, the two semiconductor structures and within the gap between the two semiconductor structures to a thickness as least as high as the top of the semiconductor structures by a first high density plasma (HDP) process. The first HDP process having a first high bias RF power, a low first deposition: sputter ratio and a first chucking bias voltage. A second dielectric layer is then formed over the first dielectric layer by a second HDP process to form the composite dielectric layer. The second HDP process having: a second bias RF power that is less than the first bias RF power; a second deposition: sputter ratio that is greater than the first deposition: sputter ratio; and a second chucking bias voltage that is zero.
摘要翻译：一种形成复合电介质层的方法，包括以下步骤。提供了具有由它们之间的间隙隔开的至少两个半导体结构的结构。第一介电层通过第一高密度等离子体（HDP）工艺形成在半导体结构的两个半导体结构之间，并且在两个半导体结构之间的间隙内至少与半导体结构的顶部一样高的厚度。第一HDP工艺具有第一高偏压RF功率，低的第一沉积：溅射比和第一夹持偏置电压。然后通过第二HDP工艺在第一介电层上形成第二介电层以形成复合介电层。第二HDP处理具有：小于第一偏置RF功率的第二偏置RF功率; 第二沉积：溅射比大于第一沉积：溅射比; 和第二夹持偏置电压为零。

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