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51. 发明授权

US07148715B2 Systems and methods for testing microelectronic imagers and microfeature devices 有权
公开(公告)号：US07148715B2
公开(公告)日：2006-12-12
申请号：US10860699
申请日：2004-06-02
申请人： Salman Akram , William M. Hiatt , Alan G. Wood , Charles M. Watkins , Kyle K. Kirby
发明人： Salman Akram , William M. Hiatt , Alan G. Wood , Charles M. Watkins , Kyle K. Kirby
IPC分类号： G01R31/02 , G01R31/26 , H01L27/00
CPC分类号： G01R31/2635 , G01R31/2831
摘要： Systems and methods for testing microelectronic imagers and microfeature devices are disclosed herein. In one embodiment, a method includes providing a microfeature workpiece including a substrate having a front side, a backside, and a plurality of microelectronic dies. The individual dies include an integrated circuit and a plurality of contact pads at the backside of the substrate operatively coupled to the integrated circuit. The method includes contacting individual contact pads with corresponding pins of a probe card. The method further includes testing the dies. In another embodiment, the individual dies can further comprise an image sensor at the front side of the substrate and operatively coupled to the integrated circuit. The image sensors are illuminated while the dies are tested.

52. 发明授权

US07391117B2 Method for fabricating semiconductor components with conductive spring contacts 有权
标题翻译：用导电弹簧触点制造半导体元件的方法
公开(公告)号：US07391117B2
公开(公告)日：2008-06-24
申请号：US11347930
申请日：2006-02-06
申请人： Kyle K. Kirby , Warren M. Farnworth
发明人： Kyle K. Kirby , Warren M. Farnworth
IPC分类号： H01L23/12
CPC分类号： G01R1/06733 , B33Y70/00 , B33Y80/00 , G01R1/06711 , G01R1/07314 , G01R3/00 , H01L23/49811 , H01L24/72 , H01L2224/05571 , H01L2224/05573 , H01L2224/13011 , H01L2224/13019 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01009 , H01L2924/01012 , H01L2924/01013 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01082 , H01L2924/12042 , H01L2924/14 , H05K3/326 , H05K3/4092 , H01L2924/00 , H01L2224/05599
摘要： An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage component contacts on a semiconductor component. Each interconnect contact includes a compliant conductive layer formed as a conductive spring element. In addition, the complaint conductive layer includes a tip for engaging the component contact and a spring segment portion for resiliently supporting the tip. A method for fabricating the interconnect includes the steps of shaping the substrate, forming a conductive layer on a shaped portion of the substrate and removing at least some of the shaped portion. The shaped portion can comprise a raised step or dome, or a shaped recess in the substrate. The conductive layer can comprise a metal, a conductive polymer or a polymer tape can include a penetrating structure or penetrating particles. The interconnect can be used to construct wafer level test systems, and die level test systems as well, for semiconductor components such as wafers, dice and packages.
摘要翻译：用于测试半导体部件的互连件包括衬底，以及被配置为电接合半导体部件上的部件触点的衬底上的互连触点。每个互连触点包括形成为导电弹簧元件的柔性导电层。此外，柔性导电层包括用于接合部件触头的尖端和用于弹性地支撑尖端的弹簧部分部分。一种用于制造互连的方法包括以下步骤：对衬底进行成形，在衬底的成形部分上形成导电层，并移除至少部分成形部分。成形部分可以包括升高的台阶或圆顶，或者基板中的成形凹部。导电层可以包括金属，导电聚合物或聚合物带可以包括穿透结构或穿透颗粒。互连可以用于构建晶片级测试系统和芯片级测试系统，用于诸如晶片，芯片和封装的半导体元件。

53. 发明授权

US08503156B2 Methods of processing semiconductor substrates, electrostatic carriers for retaining substrates for processing, and assemblies comprising electrostatic carriers having substrates electrostatically bonded thereto 有权
公开(公告)号：US08503156B2
公开(公告)日：2013-08-06
申请号：US13169915
申请日：2011-06-27
申请人： Dewali Ray , Warren M. Farnworth , Kyle K. Kirby
发明人： Dewali Ray , Warren M. Farnworth , Kyle K. Kirby
IPC分类号： H01L21/683
CPC分类号： H01L21/6833
摘要： A method of processing a substrate includes physically contacting an exposed conductive electrode of an electrostatic carrier with a conductor to electrostatically bond a substrate to the electrostatic carrier. The conductor is removed from physically contacting the exposed conductive electrode. Dielectric material is applied over the conductive electrode. The substrate is treated while it is electrostatically bonded to the electrostatic carrier. In one embodiment, a conductor is forced through dielectric material that is received over a conductive electrode of an electrostatic carrier to physically contact the conductor with the conductive electrode to electrostatically bond a substrate to the electrostatic carrier. After removing the conductor from the dielectric material, the substrate is treated while it is electrostatically bonded to the electrostatic carrier. Electrostatic carriers for retaining substrates for processing, and such assemblies, are also disclosed.

54. 发明授权

US07989022B2 Methods of processing substrates, electrostatic carriers for retaining substrates for processing, and assemblies comprising electrostatic carriers having substrates electrostatically bonded thereto 有权
标题翻译：处理基板的方法，用于保持用于处理的基板的静电载体，以及包括静电载体的组件，所述静电载体具有静电键合的基板
公开(公告)号：US07989022B2
公开(公告)日：2011-08-02
申请号：US11780628
申请日：2007-07-20
申请人： Dewali Ray , Warren M. Farnworth , Kyle K. Kirby
发明人： Dewali Ray , Warren M. Farnworth , Kyle K. Kirby
IPC分类号： C23C16/00
CPC分类号： H01L21/6833
摘要： A method of processing a substrate includes physically contacting an exposed conductive electrode of an electrostatic carrier with a conductor to electrostatically bond a substrate to the electrostatic carrier. The conductor is removed from physically contacting the exposed conductive electrode. Dielectric material is applied over the conductive electrode. The substrate is treated while it is electrostatically bonded to the electrostatic carrier. In one embodiment, a conductor is forced through dielectric material that is received over a conductive electrode of an electrostatic carrier to physically contact the conductor with the conductive electrode to electrostatically bond a substrate to the electrostatic carrier. After removing the conductor from the dielectric material, the substrate is treated while it is electrostatically bonded to the electrostatic carrier. Electrostatic carriers for retaining substrates for processing, and such assemblies, are also disclosed.
摘要翻译：处理衬底的方法包括使静电载体的暴露的导电电极与导体物理接触，以将衬底静电结合到静电载体上。导体从物理接触暴露的导电电极去除。电介质材料施加在导电电极上。在静电接触静电载体的同时对衬底进行处理。在一个实施例中，将导体强制通过介电材料，其被接收在静电载体的导电电极上，以与导电电极物理接触导体，以使基板静电地接合到静电载体上。在从电介质材料中去除导体之后，将衬底静电结合到静电载体上进行处理。还公开了用于保持用于加工的基材和这种组件的静电载体。

55. 发明授权

US07547850B2 Semiconductor device assemblies with compliant spring contact structures 有权
标题翻译：具有柔性弹簧接触结构的半导体器件组件
公开(公告)号：US07547850B2
公开(公告)日：2009-06-16
申请号：US11476471
申请日：2006-06-28
申请人： Kyle K. Kirby , Warren M. Farnworth
发明人： Kyle K. Kirby , Warren M. Farnworth
IPC分类号： H05K1/16
CPC分类号： H01L23/49811 , B33Y80/00 , G01R1/06727 , G01R1/07357 , G01R3/00 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/48 , H01L24/72 , H01L24/81 , H01L2224/13099 , H01L2224/13111 , H01L2224/136 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2224/8121 , H01L2224/81815 , H01L2224/81903 , H01L2224/83102 , H01L2224/92125 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01018 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0104 , H01L2924/01042 , H01L2924/01047 , H01L2924/01049 , H01L2924/01051 , H01L2924/01072 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15787 , H01L2924/16152 , H01L2924/351 , H05K3/4092 , H05K2201/0311 , Y10T29/49204 , Y10T29/49222 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Photolithography patterned spring contacts are disclosed. The spring contacts may be fabricated using thin film processing techniques. A substrate, such as a silicon wafer or a carrier substrate is provided. At least one layer of a metal or alloy film may be deposited on the substrate or on at least one intervening release layer and patterned to form metal traces. A stressable material, exhibiting an at least partially tensile stress state, may be deposited on the metal traces in a localized region. A portion of the substrate or a portion of the intervening release layer underneath the metal traces may be removed by etching, causing the metal traces to curl upward resulting in the spring contacts. The spring contacts may be used as compliant electrical contacts for electrical devices, such as integrated circuits or carrier substrates. The compliant electrical contacts may also be used for probe cards to test other electrical devices.
摘要翻译：公开了光刻图案的弹簧触点。可以使用薄膜处理技术来制造弹簧触点。提供了诸如硅晶片或载体衬底的衬底。至少一层金属或合金膜可以沉积在衬底上或至少一个中间释放层上并且被图案化以形成金属迹线。表现出至少部分拉伸应力状态的可压应材料可以沉积在局部区域的金属迹线上。可以通过蚀刻去除基底的一部分或金属迹线下方的中间释放层的一部分，导致金属迹线向上卷曲，导致弹簧接触。弹簧触点可以用作电气装置的柔性电触点，例如集成电路或载体基板。兼容的电触点也可用于探针卡以测试其他电气设备。

56. 发明授权

US07449910B2 Test system for semiconductor components having conductive spring contacts 失效
标题翻译：具有导电弹簧触点的半导体部件的测试系统
公开(公告)号：US07449910B2
公开(公告)日：2008-11-11
申请号：US11348094
申请日：2006-02-06
申请人： Kyle K. Kirby , Warren M. Farnworth
发明人： Kyle K. Kirby , Warren M. Farnworth
IPC分类号： G01R31/26
CPC分类号： G01R1/06733 , B33Y70/00 , B33Y80/00 , G01R1/06711 , G01R1/07314 , G01R3/00 , H01L23/49811 , H01L24/72 , H01L2224/05571 , H01L2224/05573 , H01L2224/13011 , H01L2224/13019 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01009 , H01L2924/01012 , H01L2924/01013 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01082 , H01L2924/12042 , H01L2924/14 , H05K3/326 , H05K3/4092 , H01L2924/00 , H01L2224/05599
摘要： An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage component contacts on a semiconductor component. Each interconnect contact includes a compliant conductive layer formed as a conductive spring element. In addition, the complaint conductive layer includes a tip for engaging the component contact and a spring segment portion for resiliently supporting the tip. A method for fabricating the interconnect includes the steps of shaping the substrate, forming a conductive layer on a shaped portion of the substrate and removing at least some of the shaped portion. The shaped portion can comprise a raised step or dome, or a shaped recess in the substrate. The conductive layer can comprise a metal, a conductive polymer or a polymer tape can include a penetrating structure or penetrating particles. The interconnect can be used to construct wafer level test systems, and die level test systems as well, for semiconductor components such as wafers, dice and packages.
摘要翻译：用于测试半导体部件的互连件包括衬底，以及被配置为电接合半导体部件上的部件触点的衬底上的互连触点。每个互连触点包括形成为导电弹簧元件的柔性导电层。此外，投诉导电层包括用于接合部件触点的尖端和用于弹性地支撑尖端的弹簧部分部分。一种用于制造互连的方法包括以下步骤：对衬底进行成形，在衬底的成形部分上形成导电层，并移除至少部分成形部分。成形部分可以包括升高的台阶或圆顶，或者基板中的成形凹部。导电层可以包括金属，导电聚合物或聚合物带可以包括穿透结构或穿透颗粒。互连可以用于构建晶片级测试系统和芯片级测试系统，用于诸如晶片，芯片和封装的半导体元件。

57. 发明授权

US07411304B2 Semiconductor interconnect having conductive spring contacts 失效
标题翻译：具有导电弹簧触点的半导体互连
公开(公告)号：US07411304B2
公开(公告)日：2008-08-12
申请号：US11031160
申请日：2005-01-06
申请人： Kyle K. Kirby , Warren M. Farnworth
发明人： Kyle K. Kirby , Warren M. Farnworth
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： G01R1/06733 , B33Y70/00 , B33Y80/00 , G01R1/06711 , G01R1/07314 , G01R3/00 , H01L23/49811 , H01L24/72 , H01L2224/05571 , H01L2224/05573 , H01L2224/13011 , H01L2224/13019 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01009 , H01L2924/01012 , H01L2924/01013 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01082 , H01L2924/12042 , H01L2924/14 , H05K3/326 , H05K3/4092 , H01L2924/00 , H01L2224/05599
摘要： An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage component contacts on a semiconductor component. Each interconnect contact includes a compliant conductive layer formed as a conductive spring element. In addition, the complaint conductive layer includes a tip for engaging the component contact and a spring segment portion for resiliently supporting the tip. A method for fabricating the interconnect includes the steps of shaping the substrate, forming a conductive layer on a shaped portion of the substrate and removing at least some of the shaped portion. The shaped portion can comprise a raised step or dome, or a shaped recess in the substrate. The conductive layer can comprise a metal, a conductive polymer or a polymer tape can include a penetrating structure or penetrating particles. The interconnect can be used to construct wafer level test systems, and die level test systems as well, for semiconductor components such as wafers, dice and packages.
摘要翻译：用于测试半导体部件的互连件包括衬底，以及被配置为电接合半导体部件上的部件触点的衬底上的互连触点。每个互连触点包括形成为导电弹簧元件的柔性导电层。此外，投诉导电层包括用于接合部件触点的尖端和用于弹性地支撑尖端的弹簧部分部分。一种用于制造互连的方法包括以下步骤：对衬底进行成形，在衬底的成形部分上形成导电层，并移除至少部分成形部分。成形部分可以包括升高的台阶或圆顶，或者基板中的成形凹部。导电层可以包括金属，导电聚合物或聚合物带可以包括穿透结构或穿透颗粒。互连可以用于构建晶片级测试系统和芯片级测试系统，用于诸如晶片，芯片和封装的半导体元件。

58. 发明授权

US07101792B2 Methods of plating via interconnects 有权
标题翻译：通过互连电镀的方法
公开(公告)号：US07101792B2
公开(公告)日：2006-09-05
申请号：US10682703
申请日：2003-10-09
申请人： Kyle K. Kirby , Warren M. Farnworth
发明人： Kyle K. Kirby , Warren M. Farnworth
IPC分类号： H01L21/44
CPC分类号： H01L21/2885 , H01L21/76898 , H01L23/481 , H01L2224/02372 , H01L2224/0401 , H01L2224/05548 , H01L2224/13022 , H01L2224/13024 , H01L2224/131 , Y10S438/928 , H01L2924/014
摘要： Methods for filling high aspect ratio vias with conductive material. At least one high aspect ratio via is formed in the backside of a semiconductor substrate. The at least one via is closed at one end by a conductive element forming a conductive structure of the semiconductor substrate. The backside of the semiconductor substrate is exposed to an electroplating solution containing a conductive material in solution with the active surface semiconductor substrate isolated thereform. An electric potential is applied across the conductive element through the electroplating solution and a conductive contact pad in direct or indirect electrical communication with the conductive element at the closed end of the at least one via (or forming such conductive element) to cause conductive material to electrochemically deposit from the electroplating solution and fill the at least one via. Semiconductor devices and in-process semiconductor devices are also disclosed.
摘要翻译：用导电材料填充高纵横比孔的方法。在半导体衬底的背面形成至少一个高宽比通孔。至少一个通孔在一端由形成半导体衬底的导电结构的导电元件封闭。将半导体衬底的背面暴露于在其中分离有源表面半导体衬底的溶液中含有导电材料的电镀溶液。电导通过电镀溶液施加在导电元件上，导电接触焊盘在至少一个通孔的封闭端（或形成这种导电元件）与导电元件直接或间接电连通，以使导电材料从电镀溶液电化学沉积并填充至少一个通孔。还公开了半导体器件和工艺中半导体器件。

59. 发明授权

US07528491B2 Semiconductor components and assemblies including vias of varying lateral dimensions 有权
标题翻译：半导体元件和组件包括不同横向尺寸的通孔
公开(公告)号：US07528491B2
公开(公告)日：2009-05-05
申请号：US11516424
申请日：2006-09-05
申请人： Kyle K. Kirby , Warren M. Farnworth
发明人： Kyle K. Kirby , Warren M. Farnworth
IPC分类号： H01L23/48 , H01L21/44
CPC分类号： H01L21/76898 , H01L23/3114 , H01L23/3677 , H01L23/481 , H01L25/0657 , H01L2224/16 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2225/06589 , H01L2924/00011 , H01L2924/00014 , H05K1/115 , H05K2201/09563 , H05K2201/09845 , H05K2203/0733 , H01L2224/0401
摘要： Methods for forming vias are disclosed. The methods include providing a substrate having a first surface and an opposing, second surface. A first opening, a second opening, and a third opening are formed in a substrate such that the first opening, the second opening, and the third opening are in communication with each other. A portion of the first opening, the second opening, and the third opening are filled with a conductive material. Semiconductor devices, including the vias of the present invention, are also disclosed. Semiconductor components and assemblies resulting therefrom, and an electronic system, including the vias of the present invention, are further disclosed.
摘要翻译：公开了形成通孔的方法。所述方法包括提供具有第一表面和相对的第二表面的基底。第一开口，第二开口和第三开口形成在基板中，使得第一开口，第二开口和第三开口彼此连通。第一开口，第二开口和第三开口的一部分填充有导电材料。还公开了包括本发明的通孔的半导体器件。进一步公开了由其产生的半导体部件和组件以及包括本发明的通孔的电子系统。

60. 发明授权

US07378342B2 Methods for forming vias varying lateral dimensions 有权
标题翻译：形成不同横向尺寸的通孔的方法
公开(公告)号：US07378342B2
公开(公告)日：2008-05-27
申请号：US10928598
申请日：2004-08-27
申请人： Kyle K. Kirby , Warren M. Farnworth
发明人： Kyle K. Kirby , Warren M. Farnworth
IPC分类号： H01L21/44
CPC分类号： H01L21/76898 , H01L23/3114 , H01L23/3677 , H01L23/481 , H01L25/0657 , H01L2224/16 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2225/06589 , H01L2924/00011 , H01L2924/00014 , H05K1/115 , H05K2201/09563 , H05K2201/09845 , H05K2203/0733 , H01L2224/0401
摘要： Methods for forming vias are disclosed. The methods include providing a substrate having a first surface and an opposing, second surface. A first opening, a second opening, and a third opening are formed in a substrate such that the first opening, the second opening, and the third opening are in communication with each other. A portion of the first opening, the second opening, and the third opening are filled with a conductive material. Semiconductor devices, including the vias of the present invention, are also disclosed. A method of forming semiconductor components, semiconductor components and assemblies resulting therefrom, and an electronic system, including the vias of the present invention, are further disclosed.
摘要翻译：公开了形成通孔的方法。所述方法包括提供具有第一表面和相对的第二表面的基底。第一开口，第二开口和第三开口形成在基板中，使得第一开口，第二开口和第三开口彼此连通。第一开口，第二开口和第三开口的一部分填充有导电材料。还公开了包括本发明的通孔的半导体器件。还公开了一种形成半导体部件，由其产生的半导体部件和组件以及包括本发明的通孔的电子系统的方法。

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