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51. 发明授权

US07490280B2 Microcontroller for logic built-in self test (LBIST) 有权
标题翻译：用于逻辑的微控制器内置自检（LBIST）
公开(公告)号：US07490280B2
公开(公告)日：2009-02-10
申请号：US11276413
申请日：2006-02-28
申请人： Gary D. Grise , David E. Lackey , Steven F. Oakland , Donald L. Wheater
发明人： Gary D. Grise , David E. Lackey , Steven F. Oakland , Donald L. Wheater
IPC分类号： G01R31/28
CPC分类号： G01R31/31724 , G01R31/31727
摘要： Built-in self-test (BIST) microcontroller integrated circuit adapted for logic verification. Microcontroller includes a plurality of hardware description language files representing a hierarchical description of the microcontroller, the plurality of hardware description language files including a library of circuit design elements, a plurality of library design circuit elements adapted to store a uniquely defined set of input and output signals to enable a logic BIST, and a plurality of latches adapted to store a plurality of values corresponding to a behavioral profile of a test clock.
摘要翻译：内置自检（BIST）微控制器集成电路，适用于逻辑验证。微控制器包括表示微控制器的分层描述的多个硬件描述语言文件，所述多个硬件描述语言文件包括电路设计元素库，多个库设计电路元件，适于存储唯一定义的输入和输出集合用于启用逻辑BIST的信号，以及适于存储对应于测试时钟的行为轮廓的多个值的多个锁存器。

52. 发明授权

US07484149B2 Negative edge flip-flops for muxscan and edge clock compatible LSSD 失效
标题翻译：用于muxscan和边缘时钟兼容LSSD的负边沿触发器
公开(公告)号：US07484149B2
公开(公告)日：2009-01-27
申请号：US11276768
申请日：2006-03-14
申请人： David E. Lackey
发明人： David E. Lackey
IPC分类号： G01R31/28
CPC分类号： G01R31/318541
摘要： A method of synchronous digital operation and scan based testing of an integrated circuit using a flip-flop. The flip-flop including a master latch having an input and a clock pin; a slave latch having an output, a first clock pin and a second clock pin, the slave latch connected to the master latch; a first AND gate having a first input, an inverted second input and an output, the output of the first AND gate connected to the first clock pin of the master latch; a second AND gate having a first input, an inverted second input and an output, the output of the second AND gate connected to the second input of the first AND gate and to the first clock pin of the slave latch.
摘要翻译：使用触发器的集成电路的同步数字操作和基于扫描的测试的方法。触发器包括具有输入和时钟引脚的主锁存器; 具有输出的从锁存器，第一时钟引脚和第二时钟引脚，从锁存器连接到主锁存器; 具有第一输入，反相第二输入和输出的第一与门，连接到主锁存器的第一时钟引脚的第一与门的输出; 第二与门，其具有第一输入，反相第二输入和输出，第二与门的输出连接到第一与门的第二输入和从锁存器的第一时钟引脚。

53. 发明申请

US20080270863A1 METHODS OF SYNCHRONOUS DIGITAL OPERATION AND SCAN BASED TESTING OF AN INTEGRATED CIRCUIT USING NEGATIVE EDGE FLIP-FLOPS FOR MUXSCAN AND EDGE CLOCK COMPATIBLE LSSD 审中-公开
标题翻译：同步数字操作和扫描的测试方法使用负边缘FLIPPS对多功能和边缘时钟兼容的LSSD进行集成电路的测试
公开(公告)号：US20080270863A1
公开(公告)日：2008-10-30
申请号：US12168210
申请日：2008-07-07
申请人： David E. Lackey
发明人： David E. Lackey
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318541
摘要： A method of synchronous digital operation and scan based testing of an integrated circuit using a flip-flop. The method including: providing a flip-flop comprising: a master latch having an input and a clock pin; and a slave latch having an output, a first clock pin and a second clock pin; capturing data presented at said input of said master latch and transferring data stored in said master latch to said slave latch in response to a negative edge of a first clock signal on said clock pin of said master latch; launching data stored in said slave latch to said output of said slave latch in response to said negative edge of said first clock signal; and capturing data presented at said input of said master latch in response to a positive edge of a second clock signal on said clock pin of said master latch.
摘要翻译：使用触发器的集成电路的同步数字操作和基于扫描的测试的方法。该方法包括：提供触发器，包括：具有输入和时钟引脚的主锁存器; 以及具有输出的从锁存器，第一时钟引脚和第二时钟引脚; 捕获在所述主锁存器的所述输入处呈现的数据，并且响应于所述主锁存器的所述时钟引脚上的第一时钟信号的负沿，将存储在所述主锁存器中的数据传送到所述从锁存器; 响应于所述第一时钟信号的所述负沿，将存储在所述从锁存器中的数据发射到所述从锁存器的所述输出; 以及响应于所述主锁存器的所述时钟引脚上的第二时钟信号的上升沿，捕获呈现在所述主锁存器的所述输入端的数据。

54. 发明授权

US07381986B2 Arrangement for testing semiconductor chips while incorporated on a semiconductor wafer 有权
公开(公告)号：US07381986B2
公开(公告)日：2008-06-03
申请号：US11477963
申请日：2006-06-28
申请人： Brion L. Keller , Bernd K. F. Koenermann , David E. Lackey , Donald L. Wheater
发明人： Brion L. Keller , Bernd K. F. Koenermann , David E. Lackey , Donald L. Wheater
IPC分类号： H01L23/58
CPC分类号： G01R31/2884 , G01R31/2831 , G01R31/2889 , H01L22/32 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： An arrangement that will provide multiple communication paths for the simultaneously testing of a plurality of un-diced chips on a semiconductor wafer that will simultaneously permit each such communication path to service more than one chip while using a minimum number of tester contacts. These and other objects, features and advantages of the present invention are accomplished in a semiconductor wafer having thereon a number of kerf isolated integrated chips, each of said chips being coupled to at least two different ones of strategically placed administration circuits via two different stimulus buses; each chip being coupled to each administration circuit via selection control circuits laid down in the kerf area between the chips. It is this redundancy that significantly reduces the possibility of failure associated administration or selection control circuits. The stimulus busses can also be used to provide each chip with parallel serial scan data as well as power and other signals such as clock and enable and disable signals. Each chip control circuit provides the chip with power, bus clock, control, enable and response lines, can also connected to each chip via suitable lines in the kerfs.

55. 发明授权

US06883152B2 Voltage island chip implementation 失效
标题翻译：电压岛芯片实现
公开(公告)号：US06883152B2
公开(公告)日：2005-04-19
申请号：US10867914
申请日：2004-06-15
申请人： Thomas R. Bednar , Scott W. Gould , David E. Lackey , Douglas W. Stout , Paul S. Zuchowski
发明人： Thomas R. Bednar , Scott W. Gould , David E. Lackey , Douglas W. Stout , Paul S. Zuchowski
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5045
摘要： A method and structure for designing an integrated circuit chip supplies a chip design and partitions elements of the chip design according to similarities in voltage requirements and timing of power states of the elements to create voltage islands. The invention outputs a voltage island specification list comprising power and timing information of each voltage island; and automatically, and without user intervention, synthesizes power supply networks for the voltage islands.
摘要翻译：用于设计集成电路芯片的方法和结构提供芯片设计，并且根据电压要求的相似性和元件的功率状态的时序来分配芯片设计的元件以产生电压岛。本发明输出包括每个电压岛的功率和定时信息的电压岛规格表; 并自动，无需用户干预，就可以合成电压岛的供电网络。

56. 发明授权

US06731154B2 Global voltage buffer for voltage islands 有权
标题翻译：电压岛的全局电压缓冲器
公开(公告)号：US06731154B2
公开(公告)日：2004-05-04
申请号：US10063504
申请日：2002-05-01
申请人： Thomas Richard Bednar , Scott Whitney Gould , David E. Lackey , Douglas Willard Stout , Paul Steven Zuchowski
发明人： Thomas Richard Bednar , Scott Whitney Gould , David E. Lackey , Douglas Willard Stout , Paul Steven Zuchowski
IPC分类号： H03K1706
CPC分类号： H03K19/0016
摘要： A method and apparatus for buffering a signal in a voltage island that is in standby or sleep mode. The apparatus uses a buffer(s) that are powered from a global power supply voltage that is always powered, and such buffer(s) are placed within the sleeping island itself. The sleeping island can be at the same or different voltage from the global voltage.
摘要翻译：一种用于缓冲处于待机或休眠模式的电压岛中的信号的方法和装置。该设备使用由始终供电的全局电源电压供电的缓冲器，并且这样的缓冲器被放置在睡眠岛本身内。睡眠岛可以处于与全局电压相同或不同的电压。

57. 发明授权

US06566681B2 Apparatus for assisting backside focused ion beam device modification 有权
标题翻译：用于辅助背侧聚焦离子束装置修改的装置
公开(公告)号：US06566681B2
公开(公告)日：2003-05-20
申请号：US09908925
申请日：2001-07-19
申请人： David E. Lackey , Theodore M. Levin , Leah M. Pastel
发明人： David E. Lackey , Theodore M. Levin , Leah M. Pastel
IPC分类号： H01L2358
CPC分类号： H01J37/3056 , H01J2237/304 , H01J2237/31737 , H01J2237/31742
摘要： An apparatus for assisting backside focused ion beam (FIB) device modification is disclosed. The apparatus for assisting backside FIB device modification includes an FIB device modification circuit and a control circuit. The FIB device modification circuit includes an input, an output, an FIB input pad, and an FIB output pad. The FIB device modification circuit allows the input to be electrically connected to the output. The control circuit, which is coupled to the FIB device modification circuit, may include a jumper and a cut. The control circuit is preferably located in a proximity of a backside of a substrate to allow the jumper and the cut to be modified by an FIB machine.
摘要翻译：公开了一种用于辅助背侧聚焦离子束（FIB）装置修改的装置。用于辅助背面FIB设备修改的设备包括FIB设备修改电路和控制电路。 FIB设备修改电路包括输入，输出，FIB输入焊盘和FIB输出焊盘。 FIB设备修改电路允许输入电连接到输出。耦合到FIB设备修改电路的控制电路可以包括跳线和切断。控制电路优选位于衬底的背面附近，以允许跳线和切口由FIB机器修改。

58. 发明授权

US06467044B1 On-board clock-control templates for testing integrated circuits 失效
标题翻译：用于测试集成电路的板载时钟控制模板
公开(公告)号：US06467044B1
公开(公告)日：2002-10-15
申请号：US09421861
申请日：1999-10-20
申请人： David E. Lackey
发明人： David E. Lackey
IPC分类号： G06F108
CPC分类号： G01R31/31727 , G06F1/10
摘要： An integrated circuit employing a built-in self testing is provided. The circuit comprises a clock controller, a plurality of logic domains, and a system clock. The clock controller includes a plurality of programmable clock templates. The logic domains operate based on clocks having different clocks and/or on different edges of the clocks and operable asynchronously with respect to the others of said logic domains. The system clock is distributed to the logic domains and to the clock controller. Herein, each logic domain generates master/slave signals in response to the received system clock and each of the clock templates distributes enabling signals to at least one corresponding logic domain. The enabling signals are for selectively gating the generated master/slave signals for distribution throughout at least one corresponding logic domain.
摘要翻译：提供了采用内置自检的集成电路。电路包括时钟控制器，多个逻辑域和系统时钟。时钟控制器包括多个可编程时钟模板。逻辑域基于具有不同时钟的时钟和/或在时钟的不同边缘上操作，并且可以相对于所述逻辑域的其他逻辑域异步地操作。系统时钟分配到逻辑域和时钟控制器。这里，每个逻辑域响应于接收到的系统时钟而产生主/从信号，并且每个时钟模板将使能信号分配给至少一个对应的逻辑域。使能信号用于选择性地选通所产生的主/从信号以分配至少一个对应的逻辑域。

59. 发明授权

US5783960A Integrated circuit device with improved clock signal control 失效
标题翻译：具有改进的时钟信号控制的集成电路器件
公开(公告)号：US5783960A
公开(公告)日：1998-07-21
申请号：US893307
申请日：1997-07-15
申请人： David E. Lackey
发明人： David E. Lackey
IPC分类号： G01R31/3185 , H03K5/13
CPC分类号： G01R31/318552
摘要： A remote clock signal generation means is provided which allows a plurality of clock signals to be generated remotely at the "leaf" level thereby removing the need to have multiple clock signals at the system, or "tree" level. More particularly, this system is designed for use in an LBIST circuit featuring LSSD master-slave clock control. This disclosure teaches a clock control method and structure in which the master and slave clocks are generated directly from the system clock after the clock powering logic to thereby avoid intrusion or modification effects associated with logical manipulation of the clock signals.
摘要翻译：提供了一种远程时钟信号产生装置，其允许以“叶”级远程生成多个时钟信号，从而消除了在系统或“树”级具有多个时钟信号的需要。更具体地说，该系统设计用于具有LSSD主 - 从时钟控制的LBIST电路。该公开内容教导了时钟控制方法和结构，其中主时钟和从时钟直接从时钟供电逻辑之后的系统时钟产生，从而避免与时钟信号的逻辑操作相关联的入侵或修改效应。

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