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51. 发明授权

US06205045B1 Semiconductor memory device having improved cell array layout 失效
标题翻译：具有改善的单元阵列布局的半导体存储器件
公开(公告)号：US06205045B1
公开(公告)日：2001-03-20
申请号：US09544293
申请日：2000-04-06
申请人： Masao Kuriyama , Shigeru Atsumi
发明人： Masao Kuriyama , Shigeru Atsumi
IPC分类号： G11C506
CPC分类号： G11C5/025
摘要： Each of first and second cell array groups has a cell array and a row decoder. Circuit blocks including a reset transistor, a Y selector, a write transistor, a block decoder, and a source decoder except the cell array and row decoder are arranged in the area between the first and second cell array groups. Since an address signal, a control signal, and a power supply common to the circuit blocks can be shared, the layout area can be reduced.
摘要翻译：第一和第二单元阵列组中的每一个具有单元阵列和行解码器。包括复位晶体管，Y选择器，写入晶体管，块解码器和除了单元阵列和行解码器之外的源解码器的电路块布置在第一和第二单元阵列组之间的区域中。由于可以共享地址信号，控制信号和电路块公用的电源，所以可以减小布局面积。

52. 发明授权

US5559744A Semiconductor integrated circuit device having a test mode setting circuit 失效
标题翻译：具有测试模式设定电路的半导体集成电路装置
公开(公告)号：US5559744A
公开(公告)日：1996-09-24
申请号：US389165
申请日：1995-02-15
申请人： Masao Kuriyama , Hironori Banba
发明人： Masao Kuriyama , Hironori Banba
IPC分类号： G01R31/28 , G01R31/3185 , G11C16/02 , G11C16/06 , G11C17/00 , G11C29/00 , G11C29/14 , G11C29/46 , H01L21/66 , G11C7/00
CPC分类号： G11C29/46
摘要： A semiconductor integrated circuit device includes a test mode setting circuit. The test mode setting circuit includes an AND circuit for deriving the logical AND of a test mode setting permission signal and a signal input from a pin, and a latch circuit which is set by an output of the AND circuit and reset by a test mode setting release signal. After the test content is latched in the latch circuit in response to a test mode setting permission signal, the test is effected according to the setting of state of the semiconductor integrated circuit device and data latched in the latch circuit.
摘要翻译：半导体集成电路装置包括测试模式设置电路。测试模式设置电路包括用于导出测试模式设置许可信号和从引脚输入的信号的逻辑与的AND电路，以及由AND电路的输出设置并通过测试模式设置复位的锁存电路释放信号。在根据测试模式设置许可信号将测试内容锁存在锁存电路中之后，根据半导体集成电路器件的状态设置和锁存在锁存电路中的数据进行测试。

53. 发明申请

US20090201749A1 SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR OPERATING THE SAME 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US20090201749A1
公开(公告)日：2009-08-13
申请号：US12333884
申请日：2008-12-12
申请人： Masao Kuriyama
发明人： Masao Kuriyama
IPC分类号： G11C11/416
CPC分类号： G11C7/18 , G11C7/12
摘要： A semiconductor storage device includes a plurality of memory cells connected to first and second column trees, and a sensing circuit reading data from the memory cells. The sensing circuit performing a read operation by electrically connecting the column tree, which is connected to a read-selected memory cell, to a sensing node and electrically connecting the column tree, which is connected to a non-selected memory cell, to a reference sensing line.
摘要翻译：半导体存储装置包括连接到第一和第二列树的多个存储单元，以及从存储单元读取数据的感测电路。感测电路通过将连接到读选择的存储单元的列树电连接到感测节点并将连接到未选择的存储器单元的列树电连接到参考电路来执行读取操作传感线。

54. 发明申请

US20070297242A1 Negative potential discharge circuit and method thereof 有权
标题翻译：负电位放电电路及其方法
公开(公告)号：US20070297242A1
公开(公告)日：2007-12-27
申请号：US11812927
申请日：2007-06-22
申请人： Masao Kuriyama
发明人： Masao Kuriyama
IPC分类号： G11C11/34
CPC分类号： G11C5/147 , G11C5/145 , G11C16/30
摘要： A negative potential discharge circuit may include an internal voltage generating circuit and/or a discharge unit. The internal voltage generating circuit may be configured to generate a regulated output voltage based on a power supply voltage. The discharge unit may be configured to discharge a negative potential using the regulated output voltage. A method of discharging a negative potential may include generating a regulated output voltage based on a power supply voltage, and/or discharging a negative potential using the regulated output voltage.
摘要翻译：负电位放电电路可以包括内部电压产生电路和/或放电单元。内部电压发生电路可以被配置为基于电源电压产生稳定的输出电压。放电单元可以被配置为使用调节的输出电压来放电负电位。放电负电位的方法可以包括基于电源电压产生稳定的输出电压，和/或使用调节的输出电压来排出负电位。

55. 发明授权

US06373325B1 Semiconductor device with a charge pumping circuit 失效
标题翻译：具有电荷泵电路的半导体器件
公开(公告)号：US06373325B1
公开(公告)日：2002-04-16
申请号：US09523729
申请日：2000-03-13
申请人： Masao Kuriyama
发明人： Masao Kuriyama
IPC分类号： B05F316
CPC分类号： G11C5/145 , G11C16/30
摘要： A semiconductor device comprises a charge pumping circuit including plural stages of circuit portions connected in series. Each circuit portion has a transistor having a drain and gate connected to each other and a capacitor having a connection node at which one electrode of the capacitor is connected to the drain of the transistor in such a way that potentials to be applied to adjoining connection nodes of individual capacitors alternately attain a high level and a low level when the charge-pumping circuit is operating. When the charge-pumping circuit stops operating, each of the potentials of the connection nodes of the individual capacitors is fixed at a high level if an output voltage of the charge-pumping circuit is positive.
摘要翻译：半导体器件包括电荷泵浦电路，其包括串联连接的多级电路部分。每个电路部分具有一个具有彼此连接的漏极和栅极的晶体管，以及具有连接节点的电容器，电容器的一个电极以这样的方式连接到晶体管的漏极，使得施加到相邻连接节点的电位的单个电容器在电荷泵电路工作时交替地达到高电平和低电平。当电荷泵浦电路停止工作时，如果电荷泵浦电路的输出电压为正，各个电容器的连接节点的每个电位固定在高电平。

56. 发明授权

US06160738A Nonvolatile semiconductor memory system 失效
标题翻译：非易失性半导体存储器系统
公开(公告)号：US06160738A
公开(公告)日：2000-12-12
申请号：US181404
申请日：1994-01-13
申请人： Shigeru Atsumi , Hironori Banba , Masao Kuriyama
发明人： Shigeru Atsumi , Hironori Banba , Masao Kuriyama
IPC分类号： G11C17/00 , G11C16/02 , G11C16/34 , G11C16/06
CPC分类号： G11C16/3431 , G11C16/3418
摘要： A nonvolatile semiconductor memory system is provided with a nonvolatile memory cell array divided into erase blocks data and refresh blocks, and a flag cell array including a plurality of nonvolatile flag cells each of which corresponds to one of the refresh blocks and stores data representing the refresh status of the corresponding refresh block.
摘要翻译：非易失性半导体存储器系统设置有被划分为擦除块数据和刷新块的非易失性存储单元阵列，以及包括多个非易失性标志单元的标志单元阵列，每个非易失性标志单元对应于一个刷新块，并存储表示刷新的数据相应刷新块的状态。

57. 发明授权

US5559737A Nonvolatile semiconductor memory capable of simultaneously equalizing bit lines and sense lines 失效
标题翻译：非易失性半导体存储器能够同时均衡位线和感测线
公开(公告)号：US5559737A
公开(公告)日：1996-09-24
申请号：US338827
申请日：1994-11-10
申请人： Sumio Tanaka , Shigeru Atsumi , Masao Kuriyama
发明人： Sumio Tanaka , Shigeru Atsumi , Masao Kuriyama
IPC分类号： G11C17/00 , G11C7/12 , G11C16/06 , G11C16/28
CPC分类号： G11C7/12 , G11C16/28
摘要： In a nonvolatile semiconductor memory having a two-stage sense read circuit using a level shift circuit and a single-end sense amplifier, relationships of sizes of a main memory cell bit line charge transistor, a main memory cell bit line transfer gate transistor, a main memory cell bit line load transistor, a dummy cell bit line charge transistor, a dummy cell bit line transfer gate transistor, and a dummy cell bit line load transistor are set to simultaneously satisfy conditions for equalizing a bit line and a dummy cell bit line and conditions for equalizing a sense line and a dummy cell sense line. Therefore, the potentials of the bit line and the dummy cell bit line and the potentials of the sense line and the dummy cell sense line can be simultaneously equalized, and a high-speed read operation can be achieved.
摘要翻译：在具有使用电平移位电路和单端读出放大器的两级读出电路的非易失性半导体存储器中，主存储单元位线电荷晶体管，主存储单元位线传输栅极晶体管，主存储单元位线负载晶体管，虚设单元位线充电晶体管，虚设单元位线传输门晶体管和虚设单元位线负载晶体管被设置为同时满足用于对位线和虚设单元位线进行均衡的条件以及用于均衡感测线和虚拟细胞感测线的条件。因此，可以同时均衡位线和虚设单元位线的电位和感测线和虚设单元感测线的电位，并且可以实现高速读取操作。

58. 发明授权

US5296801A Bias voltage generating circuit 失效
标题翻译：偏置电压发生电路
公开(公告)号：US5296801A
公开(公告)日：1994-03-22
申请号：US921098
申请日：1992-07-29
申请人： Nobuaki Ohtsuka , Sumio Tanaka , Masao Kuriyama
发明人： Nobuaki Ohtsuka , Sumio Tanaka , Masao Kuriyama
IPC分类号： G11C16/30 , G05F3/16
CPC分类号： G11C16/30
摘要： A bias voltage generating circuit supplies a bias voltage to a memory's bit lines. One end of a first transistor is connected to a first power supply. The first transistor conducts in response to a control signal. A second transistor is connected to another end of the first transistor. Another end of the second transistor and a gate of the second transistor are connected to an output node. One end of a third transistor and a gate connected to the output node. One end of a fourth transistor and a gate are connected to a second end of the third transistor. A second end of the fourth transistor is connected to a second power supply. One end of a fifth transistor is connected to the first power supply. The fifth transistor also conducts in response to the control signal. A sixth transistor is connected to a second end of the fifth transistor. A second end of the sixth transistor is connected to the output node and the gate of the sixth transistor is connected to a potential source. A seventh transistor is connected to the output node. A second end of the seventh transistor is connected to a ground potential. The seventh transistor also conducts in response to the control signal. The output node outputs a bias voltage to the bit lines when the control signal is activated, and is grounded through the seventh transistor when the control signal is non-activated.
摘要翻译：偏置电压产生电路将偏置电压提供给存储器的位线。第一晶体管的一端连接到第一电源。第一晶体管响应于控制信号而导通。第二晶体管连接到第一晶体管的另一端。第二晶体管的另一端和第二晶体管的栅极连接到输出节点。第三晶体管的一端和连接到输出节点的栅极。第四晶体管和栅极的一端连接到第三晶体管的第二端。第四晶体管的第二端连接到第二电源。第五晶体管的一端连接到第一电源。第五晶体管也响应于控制信号而导通。第六晶体管连接到第五晶体管的第二端。第六晶体管的第二端连接到输出节点，第六晶体管的栅极连接到电位源。第七晶体管连接到输出节点。第七晶体管的第二端连接到地电位。第七晶体管也响应于控制信号而导通。当控制信号被激活时，输出节点向位线输出偏置电压，并且当控制信号不被激活时，输出节点通过第七晶体管接地。

59. 发明授权

US5262919A Semiconductor memory device including programming circuitry 失效
标题翻译：半导体存储器件包括编程电路
公开(公告)号：US5262919A
公开(公告)日：1993-11-16
申请号：US709825
申请日：1991-06-04
申请人： Masao Kuriyama , Shigeru Atsumi , Junichi Miyamoto
发明人： Masao Kuriyama , Shigeru Atsumi , Junichi Miyamoto
IPC分类号： G11C17/00 , G11C16/02 , G11C16/10 , G11C16/32 , H01L21/8247 , H01L27/10 , H01L29/788 , H01L29/792 , G11C7/00
CPC分类号： G11C16/32 , G11C16/10
摘要： A data input circuit outputs input data in accordance with a write enable signal. A program control circuit generates different data items on the basis of the input data output from the data input circuit and the write enable signal, and turns programming transistors on/off in accordance with the different data items as generated. The programming transistors are connected to a pair of cell transistors forming an EPROM cells, and program into these cell transistors the different data items generated by the write control circuit. A timing circuit delays the timing at which the write enable signal is supplied to the write control circuit, until the input data is established within the data input circuit.

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