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51. 发明申请

US20060129318A1 Symbol position detection device and symbol position detection method 审中-公开
标题翻译：符号位置检测装置和符号位置检测方法
公开(公告)号：US20060129318A1
公开(公告)日：2006-06-15
申请号：US10540022
申请日：2003-12-26
申请人： Yuji Mizuguchi , Nobuhiko Yasui , Noboru Katta , Takahisa Sakai , Yutaka Takahira , Hirotsugu Kawada , Toshitomo Umei , Takashi Akita , Takefumi Yoshikawa , Shiro Dosho
发明人： Yuji Mizuguchi , Nobuhiko Yasui , Noboru Katta , Takahisa Sakai , Yutaka Takahira , Hirotsugu Kawada , Toshitomo Umei , Takashi Akita , Takefumi Yoshikawa , Shiro Dosho
IPC分类号： G06F19/00
CPC分类号： H04L7/0334 , H04L7/005 , H04L7/027 , H04L7/033
摘要： To a data reception device, a signal having a frequency of 12.5 MHz and including data is transmitted. The data reception device generates a clock B having a frequency of 400 MHz of (1) in FIG. 8, and performs sampling for the above-described 12.5 MHz signal based on the clock B ((2) in FIG. 8). Then, the data reception device detects zero cross points of the sampled data, and generates a 25 MHz frequency clock signal indicating the zero cross points ((3) in FIG. 8). Next, the data reception device generates, by delaying the generated clock signal by the time amount corresponding to eight clocks ((4) in FIG. 8), a 25 MHz signal indicating symbol points. Thus, symbol points can be detected.
摘要翻译：向数据接收装置发送频率为12.5MHz并包括数据的信号。数据接收装置在图1中生成具有400MHz的频率的时钟B（1）。基于时钟B（图8的（2））对上述12.5MHz信号进行采样。然后，数据接收装置检测取样数据的零交叉点，生成表示零交叉点（图8的（3））的25MHz频率时钟信号。接下来，数据接收装置通过将生成的时钟信号延迟与8个时钟（图8的（4））对应的时间量来生成表示符号点的25MHz信号。因此，可以检测符号点。

52. 发明授权

US06559895B1 Analog memory and image processing system for reducing fixed pattern noise 有权
标题翻译：用于减少固定模式噪声的模拟记忆和图像处理系统
公开(公告)号：US06559895B1
公开(公告)日：2003-05-06
申请号：US09508447
申请日：2000-03-10
申请人： Shiro Dosho , Naoshi Yanagisawa , Masayuki Ozasa , Hidehiko Kurimoto , Tatsuo Okamoto
发明人： Shiro Dosho , Naoshi Yanagisawa , Masayuki Ozasa , Hidehiko Kurimoto , Tatsuo Okamoto
IPC分类号： H04N978
CPC分类号： G11C27/04 , G11C27/024
摘要： Fixed pattern noise of an analog memory is reduced. Transfer paths of an address selection signal (SL) between an address generation unit (10) and respective storage elements (21) for storing an analog signal are constructed to have a substantially uniform electric characteristic in driving the storage elements (21) by the address selection signal (SL) to such an extent that the output signal of the analog memory is free from fixed pattern noise. A buffer unit (50) for temporarily storing and outputting the address selection signal is provided between the address generation unit (10) and the respective storage elements (21), and the buffer unit (50) is constructed to have an output characteristic substantially uniform between the storage elements (21). Also, lines between the buffer unit (50) and the storage elements (21) are constructed to have substantially the same electric characteristic. In this manner, charge feed through noise of the respective storage elements (21) are made substantially uniform, resulting in suppressing the fixed pattern noise.
摘要翻译：模拟存储器的固定模式噪声降低。在地址产生单元（10）和用于存储模拟信号的各个存储元件（21）之间的地址选择信号（SL）的传输路径被构造为在通过地址驱动存储元件（21）时具有基本均匀的电特性选择信号（SL）使得模拟存储器的输出信号没有固定模式噪声的程度。用于临时存储和输出地址选择信号的缓冲单元（50）设置在地址生成单元（10）和各个存储元件（21）之间，缓冲单元（50）被构造成具有基本均匀的输出特性在所述存储元件（21）之间。此外，缓冲单元（50）和存储元件（21）之间的线被构造成具有基本上相同的电特性。以这种方式，通过各个存储元件（21）的噪声的电荷馈送被制成基本均匀，导致抑制固定图案噪声。

53. 发明授权

US06552402B1 Composite MOS transistor device 有权
标题翻译：复合MOS晶体管器件
公开(公告)号：US06552402B1
公开(公告)日：2003-04-22
申请号：US09287310
申请日：1999-04-07
申请人： Masayuki Ozasa , Tatsuo Okamoto , Hidehiko Kurimoto , Shiro Dosho , Kazuhiko Nagaoka
发明人： Masayuki Ozasa , Tatsuo Okamoto , Hidehiko Kurimoto , Shiro Dosho , Kazuhiko Nagaoka
IPC分类号： H01L2976
CPC分类号： H01L21/823456 , H01L27/088
摘要： A composite MOS transistor device for a semiconductor integrated circuit includes at least a pair of MOS transistors, or first and second MOS transistors, placed on the same board. The first and second MOS transistors are made up of first and second groups of equally divided transistors with an equal gate width, respectively. These divided transistors are arranged in parallel to each other in the gate longitudinal direction. The divided transistors of these groups are arranged such that the sum of coordinates of respective gates, measured from a centerline, is equalized between these groups along the gate longitudinal direction. Since the sum of errors of respective gates along the length thereof becomes zero in each group of divided transistors, the current difference between the two MOS transistors can be eliminated. Accordingly, in forming a differential amplifier or a current mirror circuit using this MOS transistor pair, high current gain can be obtained while maintaining an adequate balance in output current.
摘要翻译：用于半导体集成电路的复合MOS晶体管器件至少包括一对放置在同一板上的MOS晶体管或第一和第二MOS晶体管。第一和第二MOS晶体管分别由具有相等栅极宽度的等分分割晶体管组成。这些分离的晶体管在栅极纵向方向上彼此平行地布置。这些组的分割晶体管被布置成使得从中心线测量的各个栅极的坐标之和在栅极纵向方向上在这些组之间相等。由于各组栅极沿其长度的误差之和在每组分割晶体管中变为零，所以可以消除两个MOS晶体管之间的电流差。因此，在形成使用该MOS晶体管对的差分放大器或电流镜电路时，可以在保持输出电流的充分平衡的同时获得高电流增益。

54. 发明授权

US08847812B2 Time-to-digital conversion stage and time-to-digital converter including the same 有权
标题翻译：时间到数字转换级和包括它的时间 - 数字转换器
公开(公告)号：US08847812B2
公开(公告)日：2014-09-30
申请号：US13589550
申请日：2012-08-20
申请人： Shiro Dosho , Takuji Miki
发明人： Shiro Dosho , Takuji Miki
IPC分类号： H03M1/50 , G04F10/00 , H03K5/151
CPC分类号： G04F10/005 , H03K5/1515 , H03M1/50
摘要： In a time-to-digital conversion stage, a time-to-digital conversion circuit outputs an n-bit digital signal, which represents an integer value ranging from −(2n-1−1) to +(2n-1−1), based on a phase difference between a first and a second signals input thereto; a time difference amplifier circuit amplifies the phase difference between the first and the second signals 2n-1 times, and outputs two signals having an amplified phase difference therebetween; a delay adjustment circuit adds a phase difference dependent on the digital signal to the two signals output from the time difference amplifier circuit, and outputs another two signals; an output detection circuit detects that the delay adjustment circuit has output the another two signals, and outputs a detection signal; and a storage circuit latches the digital signal in synchronism with the detection signal. Multi-stage coupling of the time-to-digital conversion stages forms a pipeline time-to-digital converter.
摘要翻译：在时间数字转换阶段，时间数字转换电路输出表示从 - （2n-1-1）到+（2n-1-1）的整数值的n位数字信号，基于输入到其的第一和第二信号之间的相位差; 时差放大器电路将第一和第二信号2n-1次之间的相位差放大倍数，并输出两个放大相位差的信号; 延迟调整电路将与数字信号相关的相位差与从时差放大器电路输出的两个信号相加，并输出另外两个信号; 输出检测电路检测出延迟调整电路输出了另外两个信号，并输出检测信号; 并且存储电路与检测信号同步地锁存数字信号。时间 - 数字转换级的多级耦合形成流水线时间 - 数字转换器。

55. 发明授权

US08674864B2 Integrator and oversampling A/D converter having the same 有权
标题翻译：具有相同的积分器和过采样A / D转换器
公开(公告)号：US08674864B2
公开(公告)日：2014-03-18
申请号：US13410964
申请日：2012-03-02
申请人： Shiro Dosho
发明人： Shiro Dosho
IPC分类号： H03M3/00
CPC分类号： G06G7/186 , H03H11/12 , H03M3/39 , H03M3/454
摘要： A high order integrator is configured using an operational amplifier, a first filter connected between an input terminal of the integrator and an inverted input terminal of the operational amplifier, and a second filter connected between the inverted input terminal and output terminal of the operational amplifier. The first filter includes n serially-connected first resistance elements, n−1 first capacitance elements each connected between each interconnecting node of the first resistance elements and the ground, and n−1 second resistance elements each connected between each interconnecting node of the first resistance elements and the ground. The second filter includes n serially-connected second capacitance elements, n−1 third resistance elements each connected between each interconnecting node of the second capacitance elements and the ground, and n−1 third capacitance elements each connected between each interconnecting node of the second capacitance elements and the ground.
摘要翻译：高阶积分器使用运算放大器配置，第一滤波器连接在积分器的输入端和运算放大器的反相输入端之间，第二滤波器连接在运算放大器的反相输入端和输出端之间。第一滤波器包括n个串联连接的第一电阻元件，每个连接在第一电阻元件的每个互连节点和地之间的n-1个第一电容元件，以及分别连接在第一电阻的每个互连节点之间的n-1个第二电阻元件元素和地面。第二滤波器包括n个串联连接的第二电容元件，n-1个第三电阻元件，每个连接在第二电容元件的每个互连节点和地之间; n-1个第三电容元件，每个连接在第二电容的每个互连节点之间元素和地面。

56. 发明申请

US20110018752A1 FLASH A/D CONVERTER, FLASH A/D CONVERSION MODULE, AND DELTA-SIGMA A/D CONVERTER 审中-公开
标题翻译：闪存A / D转换器，闪存A / D转换模块和DELTA-SIGMA A / D转换器
公开(公告)号：US20110018752A1
公开(公告)日：2011-01-27
申请号：US12899154
申请日：2010-10-06
申请人： Masao TAKAYAMA , Kazuo Matsukawa , Yosuke Mitani , Shiro Dosho
发明人： Masao TAKAYAMA , Kazuo Matsukawa , Yosuke Mitani , Shiro Dosho
IPC分类号： H03M3/00 , H03M1/36
CPC分类号： H03M1/002 , H03M1/208 , H03M1/361
摘要： In a flash A/D converter, a predictor predicts next analog input data based on a digital output signal from an A/D converter, and outputs prediction data. Based on the prediction data from the predictor, a controller turns on comparators having reference voltages near the prediction data, and in order to ensure a certain degree of A/D conversion accuracy even when the prediction fails, also turns on even-numbered comparators 103.2a (where a is 0 to 7), for example. In this manner, even when prediction of next analog input data fails, a 4-bit A/D converter can perform A/D conversion with 3-bit accuracy, while saving power consumption by reducing the number of comparators to be turned on.
摘要翻译：在闪存A / D转换器中，预测器基于来自A / D转换器的数字输出信号预测下一个模拟输入数据，并输出预测数据。基于来自预测器的预测数据，控制器打开具有靠近预测数据的参考电压的比较器，并且即使在预测失败时也确保一定程度的A / D转换精度，也打开偶数比较器103.2 a（其中a为0至7）。以这种方式，即使当下一个模拟输入数据的预测失败时，四位A / D转换器也可以以3位精度执行A / D转换，同时通过减少比较器的数量来导通，从而节省功耗。

57. 发明申请

US20080169948A1 Filter Adjustment Circuit 有权
标题翻译：过滤器调节电路
公开(公告)号：US20080169948A1
公开(公告)日：2008-07-17
申请号：US11792081
申请日：2005-09-02
申请人： Kouji Okamoto , Takashi Morie , Shiro Dosho , Hirokuni Fujiyama
发明人： Kouji Okamoto , Takashi Morie , Shiro Dosho , Hirokuni Fujiyama
IPC分类号： H03M1/06 , H03H11/04 , H03H11/20 , H03M1/10 , H03H11/12
CPC分类号： H03G5/16 , H03H11/1291 , H03H11/20
摘要： In a filter adjustment circuit for an analog filter circuit such as a Gm-C filter, an input signal IS from a reference signal generation circuit 1 is inputted to a Gm-C filter 2 to be filtered and then converted by a conversion circuit 3 to a digital signal. A reference signal RS from the reference signal generation circuit 1 is converted by a conversion circuit 4 to a digital signal. The two converted signals are held in time series in a holding circuit 5. A timing generation circuit 6 generates an update timing signal en based on a reference time-series signal ref from the holding circuit 5. A control signal generation circuit 7 generates a control signal CS based on the reference time-series signal ref and a filter output time-series signal tgt, each from the holding circuit 5. The control signal CS is inputted to the Gm-C filter 2 in response to the update timing signal en to adjust the gain of the Gm-C filter 2. As a result, variations in the response characteristics of the Gm-C filter 2 are adjusted with high accuracy with a simple circuit structure.
摘要翻译：在用于诸如Gm-C滤波器的模拟滤波器电路的滤波器调节电路中，来自参考信号产生电路1的输入信号IS被输入到要过滤的Gm-C滤波器2，然后由转换电路3转换成数字信号。来自参考信号发生电路1的参考信号RS由转换电路4转换成数字信号。两个转换信号在保持电路5中保持时间序列。定时产生电路6基于来自保持电路5的基准时间序列信号ref产生更新定时信号en。控制信号产生电路7产生控制基于参考时间序列信号ref的信号CS和来自保持电路5的滤波器输出时间序列信号tgt。控制信号CS响应于更新定时信号en至...而被输入到Gm-C滤波器2 调整Gm-C滤波器2的增益。结果，以简单的电路结构，高精度地调整Gm-C滤波器2的响应特性的变化。

58. 发明授权

US07298219B2 Phase-locked loop circuit 有权
标题翻译：锁相环电路
公开(公告)号：US07298219B2
公开(公告)日：2007-11-20
申请号：US11269742
申请日：2005-11-09
申请人： Shiro Dosho , Takashi Morie , Kouji Okamoto , Yuji Yamada , Kazuaki Sogawa
发明人： Shiro Dosho , Takashi Morie , Kouji Okamoto , Yuji Yamada , Kazuaki Sogawa
IPC分类号： H03L7/00 , H03L1/02
CPC分类号： H03L7/0995 , H03L7/0898 , H03L7/18 , H03L7/1976
摘要： The phase-locked loop circuit includes a gain setting circuit for setting a gain of a voltage controlled oscillator, and a time-constant setting circuit for setting a time constant, which is determined by the amount of current in a charge pump circuit and a capacitance value of a loop filter. The gain setting circuit sets the gain to a predetermined value, and the time-constant setting circuit sets the time constant to a predetermined value, whereby the loop band width of the phase-locked loop circuit is set to a desired value.
摘要翻译：锁相环电路包括用于设定压控振荡器的增益的增益设定电路和用于设定时间常数的时间常数设定电路，时间常数由电荷泵电路中的电流量和电容环路滤波器的值。增益设定电路将增益设定为预定值，时间常数设定电路将时间常数设定为规定值，由此将锁相环电路的环带宽度设定为期望值。

59. 发明授权

US07078948B2 Low-pass filter, feedback system, and semiconductor integrated circuit 失效
标题翻译：低通滤波器，反馈系统和半导体集成电路
公开(公告)号：US07078948B2
公开(公告)日：2006-07-18
申请号：US10815672
申请日：2004-04-02
申请人： Shiro Dosho
发明人： Shiro Dosho
IPC分类号： H04B7/197
CPC分类号： H03H7/06 , H03H11/126 , H03L7/0893 , H03L7/0895 , H03L7/093 , H03L7/18
摘要： In a low-pass filter which is preferably used as a loop filter in a PLL or DLL, filter characteristics which are the same as those of a conventional low-pass filter are realized without causing collateral problems, such as an increase in the circuit area, the circuit complexity, or the resistance value, which may be caused due to size reduction of a capacitive element in the conventional low-pass filter. Thus, in a loop filter including a capacitive element and a resistive element which are connected in series, the first input terminal is provided at the side including the resistive element, and the second input terminal is provided at a connection point of the capacitive element and the resistive element. The first input terminal is supplied with the first electric current. On the other hand, the second electric current, which is a part of the first electric current supplied to the first input terminal, is extracted from the second input terminal, so that the electric current flowing into the capacitive element is smaller than the electric current flowing through the resistive element.
摘要翻译：在PLL或DLL中优选用作环路滤波器的低通滤波器中，实现与常规低通滤波器相同的滤波器特性，而不会引起诸如电路面积增加之类的附带问题，电路复杂度或电阻值，这可能是由于常规低通滤波器中的电容元件的尺寸减小而引起的。因此，在包括串联连接的电容元件和电阻元件的环路滤波器中，第一输入端子设置在包括电阻元件的一侧，第二输入端子设置在电容元件的连接点处，电阻元件。第一输入端被提供有第一电流。另一方面，从第二输入端子抽出作为提供给第一输入端子的第一电流的一部分的第二电流，使得流入电容元件的电流小于电流流过电阻元件。

60. 发明授权

US06982581B2 Duty cycle correction circuit 失效
标题翻译：占空比校正电路
公开(公告)号：US06982581B2
公开(公告)日：2006-01-03
申请号：US10713162
申请日：2003-11-17
申请人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara
发明人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara
IPC分类号： H03K3/017
CPC分类号： H03K5/133 , H03K5/1565
摘要： In order to correct the duty cycle of a given clock signal to produce a clock signal with a 50% duty cycle, a duty cycle correction circuit includes a delay unit for delaying a first clock signal to output a second clock signal and a clock-signal output unit. The clock-signal output unit includes two transistors which use the first and second clock signals as the inputs of respective gates and an inverter circuit for inverting a signal output from a common drain of the transistors to output a third clock signal. The delay unit delays the first clock signal so that the first clock signal falling appears at a timing at which the duty cycle thereof becomes 50%. The two transistors in the clock-signal output unit output, as the third clock signal, a ground voltage and a source voltage as the signal from the common drain in response to the rising of the first clock signal and the falling of the second clock signal, respectively.
摘要翻译：为了校正给定时钟信号的占空比以产生具有50％占空比的时钟信号，占空比校正电路包括用于延迟第一时钟信号以输出第二时钟信号和时钟信号的延迟单元输出单元。时钟信号输出单元包括使用第一和第二时钟信号作为各个门的输入的两个晶体管，以及用于反相从晶体管的公共漏极输出的信号以输出第三时钟信号的反相器电路。延迟单元延迟第一时钟信号，使得第一时钟信号在占空比变为50％的定时出现。时钟信号输出单元中的两个晶体管响应于第一时钟信号的上升和第二时钟信号的下降而输出作为第三时钟信号的接地电压和源极电压作为来自公共漏极的信号，分别。

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