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51. 发明申请

US20120170347A1 MEMORY SYSTEM WITH SECTIONAL DATA LINES 有权
公开(公告)号：US20120170347A1
公开(公告)日：2012-07-05
申请号：US13362320
申请日：2012-01-31
申请人： Tianhong Yan , Luca Fasoli
发明人： Tianhong Yan , Luca Fasoli
IPC分类号： G11C5/02
CPC分类号： G11C16/24 , G11C13/0028
摘要： The system includes multiple sets of local data lines in one or more routing metal layers below the three-dimensional memory array and multiple sets of global data lines in one or more top metal layers above the three-dimensional memory array. Each set of one or more blocks include one set of the local data lines. Each bay includes one set of global data lines that connect to the group of sense amplifiers associated with the blocks of the respective bay. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines of the first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines associated with a respective bay.

52. 发明申请

US20110299340A1 Non-Volatile Memory Having 3d Array of Read/Write Elements and Read/Write Circuits and Method Thereof 有权
标题翻译：具有3d阵列读/写元件和读/写电路的非易失性存储器及其方法
公开(公告)号：US20110299340A1
公开(公告)日：2011-12-08
申请号：US13151204
申请日：2011-06-01
申请人： George Samachisa , Luca Fasoli , Yan Li , Tianhong Yan
发明人： George Samachisa , Luca Fasoli , Yan Li , Tianhong Yan
IPC分类号： G11C16/26 , G11C16/10
CPC分类号： G11C13/0069 , G11C13/0007 , G11C13/004 , G11C13/0097 , G11C16/06 , G11C2013/0054 , G11C2213/32 , G11C2213/71 , G11C2213/77 , H01L27/249 , H01L45/06 , H01L45/065 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/148 , H01L45/149 , H01L45/1675
摘要： A three-dimensional array is especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. During sensing, to compensate for word line resistance, a sense amplifier references a stored reference value during sensing of a memory element at a given location of the word line. A layout with a row of sense amplifiers between two memory arrays is provided to facilitate the referencing. A selected memory element is reset without resetting neighboring ones when it is subject to a bias voltage under predetermined conditions.
摘要翻译：三维阵列特别适合于响应于在其上施加电压差而可逆地改变电导水平的存储器元件。存储元件跨越位于半导体衬底上方不同距离的多个平面形成。所有平面的存储元件连接到的位线的二维阵列从衬底垂直定向并穿过多个平面。在感测期间，为了补偿字线电阻，读出放大器在对字线的给定位置处的存储元件的感测期间参考存储的参考值。提供了在两个存储器阵列之间具有一行读出放大器的布局以便于参考。当在预定条件下经受偏置电压时，选择的存储元件被复位而不重置相邻的存储元件。

53. 发明申请

US20110299314A1 Non-Volatile Memory Having 3d Array of Read/Write Elements with Efficient Decoding of Vertical Bit Lines and Word Lines 有权
标题翻译：具有3d阵列读/写元素的非易失性存储器，用于对垂直位线和字线进行高效解码
公开(公告)号：US20110299314A1
公开(公告)日：2011-12-08
申请号：US13151224
申请日：2011-06-01
申请人： George Samachisa , Luca Fasoli , Masaaki Higashitani , Roy Edwin Scheuerlein
发明人： George Samachisa , Luca Fasoli , Masaaki Higashitani , Roy Edwin Scheuerlein
IPC分类号： G11C5/02
CPC分类号： G11C16/10 , G11C13/003 , G11C2213/71 , H01L27/2409 , H01L27/249 , H01L45/06 , H01L45/065 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/144 , H01L45/146 , H01L45/149
摘要： A three-dimensional array of memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar lines from the substrate through the multiple layers of planes. A first set of pillar lines acts as local bit lines for accessing the memory elements together with an array of word lines on each plane. A second set of pillar lines is connected to the word lines. An array of metal lines on the substrate is switchable connected to the pillar lines to provide access to the first and second sets of pillar lines, thereby to provide access respectively to the bit lines and word lines of the three-dimensional array.
摘要翻译：存储元件的三维阵列形成在位于半导体衬底上方不同距离的多个平面层上。存储元件响应于在其上施加的电压差而可逆地改变电导级。三维阵列包括从基板到多层平面的两列立柱阵列。第一组支柱线作为用于在每个平面上与字线阵列一起存取存储元件的局部位线。第二组柱线连接到字线。衬底上的金属线阵列可切换地连接到柱线以提供对第一和第二组柱线的接近，从而分别提供对三维阵列的位线和字线的访问。

54. 发明申请

US20110182105A1 MEMORY SYSTEM WITH SECTIONAL DATA LINES 有权
标题翻译：具有数据线的存储系统
公开(公告)号：US20110182105A1
公开(公告)日：2011-07-28
申请号：US13079613
申请日：2011-04-04
申请人： Tianhong Yan , Luca Fasoli
发明人： Tianhong Yan , Luca Fasoli
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C16/24 , G11C13/0028
摘要： A storage system includes a three-dimensional memory array that has multiple layers of non-volatile storage elements grouped into blocks. The blocks are grouped into bays. The storage system includes array lines of a first type in communication with storage elements, array lines of a second type in communication with storage elements, and sense amplifiers. Each block is geographically associated with two sense amplifiers and all blocks of a particular bay share a group of sense amplifiers associated with the blocks of the particular bay. The system includes multiple sets of local data lines in one or more routing metal layers below the three-dimensional memory array and multiple sets of global data lines in one or more top metal layers above the three-dimensional memory array. Each set of one or more blocks include one set of the local data lines. Each bay includes one set of global data lines that connect to the group of sense amplifiers associated with the blocks of the respective bay. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines of the first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines associated with a respective bay.
摘要翻译：存储系统包括具有分组成块的多层非易失性存储元件的三维存储器阵列。块被分组成海湾。存储系统包括与存储元件通信的第一类型的阵列线，与存储元件通信的第二类型的阵列线和读出放大器。每个块在地理上与两个读出放大器相关联，并且特定间隔的所有块共享与特定间隔的块相关联的一组读出放大器。该系统在三维存储器阵列下面的一个或多个路由金属层中的多组本地数据线和在三维存储器阵列上方的一个或多个顶部金属层中的多组全局数据线。每个一个或多个块的集合包括一组本地数据线。每个托架包括一组全局数据线，其连接到与相应托架的块相关联的读出放大器组。每个块包括用于选择性地将第一类型的阵列线的子集耦合到相应的本地数据线的第一选择电路的子集。每个块包括用于选择性地将各个本地数据线的子集耦合到与相应的间隔相关联的全局数据线的第二选择电路的子集。

55. 发明申请

US20100302835A1 LIMITED CHARGE DELIVERY FOR PROGRAMMING NON-VOLATILE STORAGE ELEMENTS 有权
标题翻译：用于编程非挥发性储存元件的有限费用交付
公开(公告)号：US20100302835A1
公开(公告)日：2010-12-02
申请号：US12472074
申请日：2009-05-26
申请人： Andrei Mihnea , Luca Fasoli
发明人： Andrei Mihnea , Luca Fasoli
IPC分类号： G11C11/00 , G11C8/18 , G11C5/14 , G11C8/00
CPC分类号： G11C5/145 , G11C8/12 , G11C8/18 , G11C13/0038 , G11C2213/71 , G11C2213/72
摘要： A memory system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and a circuit for detecting the setting and resetting of the reversible resistance-switching elements. In one aspect a circuit that has one or more clock inputs is run for a predetermined number of clock cycles. The circuit generates an amount of charge over the predetermined number of clock cycles. At most the amount of charge is provided to non-volatile storage element to program the non-volatile storage element. It is determined whether the non-volatile storage element is programmed to a desired state as a result of providing at most the amount of charge to the non-volatile storage element. Techniques disclosed herein can be applied to program memory cells other than memory cells with reversible resistance-switching elements.
摘要翻译：存储器系统包括衬底，衬底上的控制电路，包括具有可逆电阻切换元件的多个存储单元的三维存储器阵列（衬底上方），以及用于检测可逆电阻的设置和复位的电路开关元件在一个方面，具有一个或多个时钟输入的电路运行预定数量的时钟周期。电路在预定数量的时钟周期内产生一定量的电荷。最多将充电量提供给非易失性存储元件以对非易失性存储元件进行编程。作为对非易失性存储元件的充电量最多提供的结果，确定非易失性存储元件是否被编程到期望状态。本文公开的技术可以应用于具有可逆电阻切换元件的存储单元以外的程序存储单元。

56. 发明申请

US20100259961A1 Three-Dimensional Array of Re-Programmable Non-Volatile Memory Elements Having Vertical Bit Lines and a Double-Global-Bit-Line Architecture 有权
标题翻译：具有垂直位线和双全局位线架构的可重新编程的非易失性存储器元件的三维阵列
公开(公告)号：US20100259961A1
公开(公告)日：2010-10-14
申请号：US12748233
申请日：2010-03-26
申请人： Luca Fasoli , George Samachisa
发明人： Luca Fasoli , George Samachisa
IPC分类号： G11C5/02 , G11C5/06
CPC分类号： G11C11/5685 , B82Y10/00 , G11C11/5614 , G11C11/5678 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/003 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C13/025 , G11C2013/0045 , G11C2013/0088 , G11C2213/19 , G11C2213/32 , G11C2213/34 , G11C2213/71 , G11C2213/72 , G11C2213/78 , H01L27/2436 , H01L27/249 , H01L45/06 , H01L45/065 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/142 , H01L45/143 , H01L45/146 , H01L45/148 , H01L45/149
摘要： A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. A double-global-bit-line architecture provides a pair of global bit lines for each bit lines for accessing a row of memory elements in parallel. A first one of each pair allows the local bit lines of the row to be sensed while a second one of each pair allows local bit lines in an adjacent row to be set to a definite voltage so as to eliminate leakage currents between adjacent rows of local bit lines.
摘要翻译：特别适用于响应于在其上施加电压差而可逆地改变电导水平的存储元件的三维阵列。存储元件跨越位于半导体衬底上方不同距离的多个平面形成。所有平面的存储元件连接到的位线的二维阵列从衬底垂直定向并穿过多个平面。双全局位线架构为每个位线提供一对全局位线，用于并行访问一行存储器元件。每对中的第一个允许检测行的局部位线，而每对中的第二个行允许将相邻行中的局部位线设置为一定电压，以便消除相邻的本地行之间的泄漏电流位线。

57. 发明申请

US20060126415A1 Programmable system device having a shared power supply voltage generator for FLASH and PLD modules 有权
标题翻译：具有用于FLASH和PLD模块的共享电源电压发生器的可编程系统设备
公开(公告)号：US20060126415A1
公开(公告)日：2006-06-15
申请号：US11012521
申请日：2004-12-15
申请人： Stella Matarrese , Luca Fasoli , Oron Michael , Cuong Trinh
发明人： Stella Matarrese , Luca Fasoli , Oron Michael , Cuong Trinh
IPC分类号： G11C5/14
CPC分类号： G11C5/14 , G11C16/30
摘要： A programmable system device includes an embedded FLASH memory module and an embedded programmable logic device (PLD) module. A sole embedded power supply voltage generator generates a plurality of voltages for use by the FLASH memory module and the PLD module during programming, reading and erasing operations. A switching network receives at least some of the generated voltages and selectively chooses among and between the received generated voltages for application to the FLASH memory module and the PLD module depending on whether that particular module is engaged in programming, reading or erasing operations. A load adjustment circuit controls operation of the sole power supply voltage generator based on whether the generated voltages are being used by the FLASH memory module or the PLD module to account for differences in loading between the FLASH memory module and the PLD module during programming, reading and erasing operations. A voltage trimming circuit controls operation of the sole embedded power supply voltage generator to make adjustments in voltage level for at least some of the generated voltages depending on whether those generated voltages are being used by the FLASH memory module or the PLD module during programming, reading and erasing operations.
摘要翻译：可编程系统设备包括嵌入式闪存模块和嵌入式可编程逻辑器件（PLD）模块。唯一的嵌入式电源电压发生器在编程，读取和擦除操作期间产生多个电压供FLASH存储器模块和PLD模块使用。交换网络接收至少一些所产生的电压，并且根据所述特定模块是否参与编程，读取或擦除操作，在所接收的产生的电压之间和之间选择性地选择应用于闪速存储器模块和PLD模块。负载调整电路基于在闪存存储器模块或PLD模块中是否使用所产生的电压来解释编程，读取期间FLASH存储器模块和PLD模块之间的负载差异，来控制唯一电源电压发生器的操作并擦除操作。电压调整电路控制唯一嵌入式电源电压发生器的操作，以根据在编程，读取期间FLASH存储器模块或PLD模块中是否使用那些产生的电压来调整至少一些所产生的电压的电压电平并擦除操作。

58. 发明授权

US08547720B2 Non-volatile memory having 3D array of read/write elements with efficient decoding of vertical bit lines and word lines 有权
标题翻译：具有读/写元素的3D阵列的非易失性存储器，其具有垂直位线和字线的有效解码
公开(公告)号：US08547720B2
公开(公告)日：2013-10-01
申请号：US13151224
申请日：2011-06-01
申请人： George Samachisa , Luca Fasoli , Masaaki Higashitani , Roy Edwin Scheuerlein
发明人： George Samachisa , Luca Fasoli , Masaaki Higashitani , Roy Edwin Scheuerlein
IPC分类号： G11C5/02
CPC分类号： G11C16/10 , G11C13/003 , G11C2213/71 , H01L27/2409 , H01L27/249 , H01L45/06 , H01L45/065 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/144 , H01L45/146 , H01L45/149
摘要： A three-dimensional array of memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar lines from the substrate through the multiple layers of planes. A first set of pillar lines acts as local bit lines for accessing the memory elements together with an array of word lines on each plane. A second set of pillar lines is connected to the word lines. An array of metal lines on the substrate is switchable connected to the pillar lines to provide access to the first and second sets of pillar lines, thereby to provide access respectively to the bit lines and word lines of the three-dimensional array.
摘要翻译：存储元件的三维阵列形成在位于半导体衬底上方不同距离的多个平面层上。存储元件响应于在其上施加的电压差而可逆地改变电导级。三维阵列包括从基板到多层平面的两列立柱阵列。第一组支柱线作为用于在每个平面上与字线阵列一起存取存储元件的局部位线。第二组柱线连接到字线。衬底上的金属线阵列可切换地连接到柱线以提供对第一和第二组柱线的接近，从而分别提供对三维阵列的位线和字线的访问。

59. 发明申请

US20120236663A1 PROGRAM CYCLE SKIP 有权
标题翻译：程序循环跳
公开(公告)号：US20120236663A1
公开(公告)日：2012-09-20
申请号：US13488600
申请日：2012-06-05
申请人： Gopinath Balakrishnan , Luca Fasoli , Tz-Yi Liu , Yuheng Zhang , Yan Li
发明人： Gopinath Balakrishnan , Luca Fasoli , Tz-Yi Liu , Yuheng Zhang , Yan Li
IPC分类号： G11C7/00
CPC分类号： G11C13/0069 , G11C5/02 , G11C13/0007 , G11C13/0061 , G11C17/165 , G11C17/18 , G11C2013/0076 , G11C2013/0085 , G11C2213/71
摘要： A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non-volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming.
摘要翻译：非易失性存储系统包括在编程页面（或其他单元）数据时跳过编程周期的技术。在对页面（或其他单元）数据的当前子集进行编程时，系统将评估页面（或其他单元）的下一个子集是否应编程为非易失性存储元素或跳过。不应被跳过的页面（或其他单元）的子集被编程到非易失性存储元件中。一些实施例包括将适当数据传送到临时锁存器/寄存器，以准备编程，同时评估是编程还是跳过编程。

60. 发明申请

US20120170346A1 MEMORY SYSTEM WITH SECTIONAL DATA LINES 有权
标题翻译：具有数据线的存储系统
公开(公告)号：US20120170346A1
公开(公告)日：2012-07-05
申请号：US13362311
申请日：2012-01-31
申请人： Tianhong Yan , Luca Fasoli
发明人： Tianhong Yan , Luca Fasoli
IPC分类号： G11C5/02
CPC分类号： G11C16/24 , G11C13/0028
摘要： The system includes multiple sets of local data lines in one or more routing metal layers below the three-dimensional memory array and multiple sets of global data lines in one or more top metal layers above the three-dimensional memory array. Each set of one or more blocks include one set of the local data lines. Each bay includes one set of global data lines that connect to the group of sense amplifiers associated with the blocks of the respective bay. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines of the first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines associated with a respective bay.
摘要翻译：该系统在三维存储器阵列下面的一个或多个路由金属层中的多组本地数据线和在三维存储器阵列上方的一个或多个顶部金属层中的多组全局数据线。每个一个或多个块的集合包括一组本地数据线。每个托架包括一组全局数据线，其连接到与相应托架的块相关联的读出放大器组。每个块包括用于选择性地将第一类型的阵列线的子集耦合到相应的本地数据线的第一选择电路的子集。每个块包括用于选择性地将各个本地数据线的子集耦合到与相应的间隔相关联的全局数据线的第二选择电路的子集。

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