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1. 发明申请

US20060126415A1 Programmable system device having a shared power supply voltage generator for FLASH and PLD modules 有权
标题翻译：具有用于FLASH和PLD模块的共享电源电压发生器的可编程系统设备
公开(公告)号：US20060126415A1
公开(公告)日：2006-06-15
申请号：US11012521
申请日：2004-12-15
申请人： Stella Matarrese , Luca Fasoli , Oron Michael , Cuong Trinh
发明人： Stella Matarrese , Luca Fasoli , Oron Michael , Cuong Trinh
IPC分类号： G11C5/14
CPC分类号： G11C5/14 , G11C16/30
摘要： A programmable system device includes an embedded FLASH memory module and an embedded programmable logic device (PLD) module. A sole embedded power supply voltage generator generates a plurality of voltages for use by the FLASH memory module and the PLD module during programming, reading and erasing operations. A switching network receives at least some of the generated voltages and selectively chooses among and between the received generated voltages for application to the FLASH memory module and the PLD module depending on whether that particular module is engaged in programming, reading or erasing operations. A load adjustment circuit controls operation of the sole power supply voltage generator based on whether the generated voltages are being used by the FLASH memory module or the PLD module to account for differences in loading between the FLASH memory module and the PLD module during programming, reading and erasing operations. A voltage trimming circuit controls operation of the sole embedded power supply voltage generator to make adjustments in voltage level for at least some of the generated voltages depending on whether those generated voltages are being used by the FLASH memory module or the PLD module during programming, reading and erasing operations.
摘要翻译：可编程系统设备包括嵌入式闪存模块和嵌入式可编程逻辑器件（PLD）模块。唯一的嵌入式电源电压发生器在编程，读取和擦除操作期间产生多个电压供FLASH存储器模块和PLD模块使用。交换网络接收至少一些所产生的电压，并且根据所述特定模块是否参与编程，读取或擦除操作，在所接收的产生的电压之间和之间选择性地选择应用于闪速存储器模块和PLD模块。负载调整电路基于在闪存存储器模块或PLD模块中是否使用所产生的电压来解释编程，读取期间FLASH存储器模块和PLD模块之间的负载差异，来控制唯一电源电压发生器的操作并擦除操作。电压调整电路控制唯一嵌入式电源电压发生器的操作，以根据在编程，读取期间FLASH存储器模块或PLD模块中是否使用那些产生的电压来调整至少一些所产生的电压的电压电平并擦除操作。

2. 发明授权

US07180813B2 Programmable system device having a shared power supply voltage generator for FLASH and PLD modules 有权
标题翻译：具有用于FLASH和PLD模块的共享电源电压发生器的可编程系统设备
公开(公告)号：US07180813B2
公开(公告)日：2007-02-20
申请号：US11012521
申请日：2004-12-15
申请人： Stella Matarrese , Luca G. Fasoli , Oron Michael , Cuong Q. Trinh
发明人： Stella Matarrese , Luca G. Fasoli , Oron Michael , Cuong Q. Trinh
IPC分类号： G11C5/14
CPC分类号： G11C5/14 , G11C16/30
摘要： A programmable system device includes an embedded FLASH memory module and an embedded programmable logic device (PLD) module. A sole embedded power supply voltage generator generates a plurality of voltages for use by the FLASH memory module and the PLD module during programming, reading and erasing operations. A switching network receives at least some of the generated voltages and selectively chooses among and between the received generated voltages for application to the FLASH memory module and the PLD module depending on whether that particular module is engaged in programming, reading or erasing operations. A load adjustment circuit controls operation of the sole power supply voltage generator based on whether the generated voltages are being used by the FLASH memory module or the PLD module to account for differences in loading between the FLASH memory module and the PLD module during programming, reading and erasing operations. A voltage trimming circuit controls operation of the sole embedded power supply voltage generator to make adjustments in voltage level for at least some of the generated voltages depending on whether those generated voltages are being used by the FLASH memory module or the PLD module during programming, reading and erasing operations.
摘要翻译：可编程系统设备包括嵌入式闪存模块和嵌入式可编程逻辑器件（PLD）模块。唯一的嵌入式电源电压发生器在编程，读取和擦除操作期间产生多个电压供FLASH存储器模块和PLD模块使用。交换网络接收至少一些所产生的电压，并且根据所述特定模块是否参与编程，读取或擦除操作，在所接收的产生的电压之间和之间选择性地选择应用于闪速存储器模块和PLD模块。负载调整电路基于在闪存存储器模块或PLD模块中是否使用所产生的电压来解释编程，读取期间FLASH存储器模块和PLD模块之间的负载差异，来控制唯一电源电压发生器的操作并擦除操作。电压调整电路控制唯一嵌入式电源电压发生器的操作，以根据在编程，读取期间FLASH存储器模块或PLD模块中是否使用那些产生的电压来调整至少一些所产生的电压的电压电平并擦除操作。

3. 发明申请

US20130346671A1 On-Chip Bad Block Management for NAND Flash Memory 有权
标题翻译：用于NAND闪存的片上坏块管理
公开(公告)号：US20130346671A1
公开(公告)日：2013-12-26
申请号：US13530518
申请日：2012-06-22
申请人： Oron Michael , Robin John Jigour , Anil Gupta
发明人： Oron Michael , Robin John Jigour , Anil Gupta
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F3/0679 , G06F2212/7201
摘要： Certain functions relating to creation and use of a look-up table for bad block mapping may be implemented “on chip” in the memory device itself, that is on the same die in an additional circuit, or even within the command and control logic of the memory device, so as to reduce the overhead. Moreover, the on-chip implementation of the look-up table may be tightly integrated with other functions of the command and control logic to enable powerful new commands for NAND flash memory, such as a continuous read command and variations thereof.
摘要翻译：关于创建和使用用于坏块映射的查找表的某些功能可以在存储器设备本身中“在芯片上”实现，即在附加电路中的相同裸片上，或者甚至在命令和控制逻辑存储设备，以减少开销。此外，查找表的片上实现可以与命令和控制逻辑的其他功能紧密集成，以实现NAND闪存的强大的新命令，例如连续读取命令及其变体。

4. 发明授权

US08667368B2 Method and apparatus for reading NAND flash memory 有权
标题翻译：读取NAND闪存的方法和装置
公开(公告)号：US08667368B2
公开(公告)日：2014-03-04
申请号：US13464535
申请日：2012-05-04
申请人： Anil Gupta , Oron Michael , Robin John Jigour
发明人： Anil Gupta , Oron Michael , Robin John Jigour
IPC分类号： G11C29/00
CPC分类号： G06F11/1064 , G11C2029/0411
摘要： A page buffer for a NAND memory array has a data register and a cache register that are suitably organized and operated to eliminate gaps and discontinuities in the output data during a continuous page read. The cache register may be organized in two portions, and the page data in the cache may be output from the cache portions in alternation. ECC delay may be eliminated from the output by performing the ECC computation on one cache portion while the other is being output. The data register may also be organized in two portions corresponding to the cache portions, so that data may be transferred to one cache portion while the other is being output. In a variation, the continuous page read may be done without ECC.
摘要翻译：用于NAND存储器阵列的页缓冲器具有适当地组织和操作的数据寄存器和高速缓存寄存器，以在连续页读取期间消除输出数据中的间隙和不连续性。高速缓存寄存器可以以两部分组织，并且高速缓存中的页面数据可以从高速缓存部分交替地输出。可以通过在一个高速缓存部分执行ECC计算而另一个缓存部分被输出来从输出消除ECC延迟。数据寄存器也可以被组织在与高速缓存部分对应的两部分中，从而数据可以被传送到一个高速缓存部分而另一个被输出。在一个变型中，连续页面读取可以在不进行ECC的情况下完成。

5. 发明授权

US06665213B1 Sense amplifier circuit and method for nonvolatile memory devices 有权
标题翻译：用于非易失性存储器件的感应放大器电路和方法
公开(公告)号：US06665213B1
公开(公告)日：2003-12-16
申请号：US10345474
申请日：2003-01-15
申请人： Oron Michael , Ilan Sever
发明人： Oron Michael , Ilan Sever
IPC分类号： G11C1606
CPC分类号： G11C7/067 , G11C7/062 , G11C16/28 , G11C2207/063
摘要： A sense amplifier circuit and method are disclosed for nonvolatile memory devices, such as flash memory devices. The sense amplifier circuit includes a current source that is configurable to source any of at least two nonzero current levels in the sense amplifier circuit. The sense amplifier circuit is controlled by control circuitry in the nonvolatile memory device so that each sense amplifier circuit sources a first current level during the precharge cycle of a memory read operation, and a second current level, greater than the first current level, during the memory cell sense operation. In this way, the sense amplifier circuit consumes less power during the memory read operation without an appreciable loss in performance.
摘要翻译：公开了用于非易失性存储器件（例如闪存器件）的读出放大器电路和方法。读出放大器电路包括可配置为在读出放大器电路中源于至少两个非零电流电平中的任何一个的电流源。感测放大器电路由非易失性存储器件中的控制电路控制，使得每个读出放大器电路在存储器读取操作的预充电循环期间和在第一电流电平期间在第存储单元检测操作。以这种方式，读出放大器电路在存储器读取操作期间消耗较少的功率，而没有明显的性能损失。

6. 发明授权

US08737135B2 Method for and flash memory device having improved read performance 有权
标题翻译：具有改善的读取性能的方法和闪速存储器件
公开(公告)号：US08737135B2
公开(公告)日：2014-05-27
申请号：US13216103
申请日：2011-08-23
申请人： Oron Michael
发明人： Oron Michael
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C16/26
摘要： A Flash memory device operable under a single-bit or multiple-bit serial protocol is provided with a capability to determine the address boundary condition of an application from the address field of an address boundary configurable (“ABC”) read command. Based on the identified address boundary condition, the Flash memory device may perform multiple sensing of the memory array as required by the ABC read command using optimal internal sense times for each sensing. The number of dummy bytes may be specified for the read command in advance by the user, based on the address boundary of the application and the desired frequency of operation of the Flash memory device. Therefore, Flash memory device read performance is improved both by minimizing the number of dummy bytes in the read command and by optimizing the internal sense times for the read operation.
摘要翻译：在单位或多位串行协议下可操作的闪速存储器件具有从地址边界可配置（“ABC”）读取命令的地址字段确定应用的地址边界条件的能力。基于所识别的地址边界条件，闪存器件可以使用针对每个感测的最佳内部检测时间来执行ABC读取命令所要求的存储器阵列的多次感测。可以基于应用的地址边界和闪存设备的期望操作频率，由用户预先为读取命令指定虚拟字节的数量。因此，通过最小化读取命令中的虚拟字节数以及通过优化读取操作的内部检测时间来改善闪存器件读取性能。

7. 发明申请

US20130297987A1 Method and Apparatus for Reading NAND Flash Memory 有权
标题翻译：读取NAND闪存的方法和装置
公开(公告)号：US20130297987A1
公开(公告)日：2013-11-07
申请号：US13464535
申请日：2012-05-04
申请人： Anil Gupta , Oron Michael , Robin John Jigour
发明人： Anil Gupta , Oron Michael , Robin John Jigour
IPC分类号： G11C29/00 , G06F11/16
CPC分类号： G06F11/1064 , G11C2029/0411
摘要： A page buffer for a NAND memory array has a data register and a cache register that are suitably organized and operated to eliminate gaps and discontinuities in the output data during a continuous page read. The cache register may be organized in two portions, and the page data in the cache may be output from the cache portions in alternation. ECC delay may be eliminated from the output by performing the ECC computation on one cache portion while the other is being output. The data register may also be organized in two portions corresponding to the cache portions, so that data may be transferred to one cache portion while the other is being output. In a variation, the continuous page read may be done without ECC.
摘要翻译：用于NAND存储器阵列的页缓冲器具有适当地组织和操作的数据寄存器和高速缓存寄存器，以在连续页读取期间消除输出数据中的间隙和不连续性。高速缓存寄存器可以以两部分组织，并且高速缓存中的页面数据可以从高速缓存部分交替地输出。可以通过在一个高速缓存部分执行ECC计算而另一个缓存部分被输出来从输出消除ECC延迟。数据寄存器也可以被组织在与高速缓存部分对应的两部分中，从而数据可以被传送到一个高速缓存部分而另一个被输出。在一个变型中，连续页面读取可以在不进行ECC的情况下完成。

8. 发明授权

US06707715B2 Reference generator circuit and method for nonvolatile memory devices 有权
标题翻译：用于非易失性存储器件的参考发生器电路和方法
公开(公告)号：US06707715B2
公开(公告)日：2004-03-16
申请号：US09922016
申请日：2001-08-02
申请人： Oron Michael , Ilan Sever
发明人： Oron Michael , Ilan Sever
IPC分类号： G11C1604
CPC分类号： G11C16/28 , G11C5/147 , G11C7/14
摘要： Reference generator circuitry for providing a reference to sense amplifiers in a flash memory device. The circuitry includes a reference current generator for generating a reference current for use by the sense amplifier circuits. A current buffer circuit in the flash memory device mirrors the reference current and applies a plurality of mirrored reference currents to the reference inputs of the sense amplifiers. A startup circuit is utilized in order to provide a fast settling time of the reference node appearing at the input of the sense amplifiers. The startup circuit includes first and second discharge current stages, with the first discharge current stage discharging the charge appearing at the reference node input of the sense amplifiers based upon a bandgap reference current. The second discharge current stage discharging the charge appearing at the reference node input of the sense amplifiers based upon the reference current. Each discharge current stage utilizes feedback to gradually decrease the rate of discharge by the discharge current stage so that the discharge current stages are disabled by the time the voltage appearing at the reference node input of the sense amplifiers reaches the desired voltage level.
摘要翻译：参考发生器电路，用于提供闪速存储器件中的读出放大器的参考。电路包括用于产生用于读出放大器电路的参考电流的参考电流发生器。闪速存储器件中的当前缓冲电路反映参考电流并将多个镜像参考电流施加到读出放大器的基准输入。利用启动电路来提供在感测放大器的输入处出现的参考节点的快速建立时间。启动电路包括第一和第二放电电流级，第一放电电流级基于带隙基准电流来放电出现在读出放大器的参考节点输入端的电荷。第二放电电流级基于参考电流对出现在读出放大器的参考节点输入端的电荷进行放电。每个放电电流级利用反馈来逐渐降低放电电流级的放电速率，使得在感测放大器的参考节点输入处出现的电压达到期望的电压电平时，放电电流级被禁用。

9. 发明授权

US09128822B2 On-chip bad block management for NAND flash memory 有权
标题翻译：用于NAND闪存的片上坏块管理
公开(公告)号：US09128822B2
公开(公告)日：2015-09-08
申请号：US13530518
申请日：2012-06-22
申请人： Oron Michael , Robin John Jigour , Anil Gupta
发明人： Oron Michael , Robin John Jigour , Anil Gupta
IPC分类号： G06F12/02 , G06F3/06
CPC分类号： G06F12/0246 , G06F3/0679 , G06F2212/7201
摘要： Certain functions relating to creation and use of a look-up table for bad block mapping may be implemented “on chip” in the memory device itself, that is on the same die in an additional circuit, or even within the command and control logic of the memory device, so as to reduce the overhead. Moreover, the on-chip implementation of the look-up table may be tightly integrated with other functions of the command and control logic to enable powerful new commands for NAND flash memory, such as a continuous read command and variations thereof.
摘要翻译：关于创建和使用用于坏块映射的查找表的某些功能可以在存储器设备本身中“在芯片上”实现，即在附加电路中的相同裸片上，或者甚至在命令和控制逻辑存储设备，以减少开销。此外，查找表的片上实现可以与命令和控制逻辑的其他功能紧密集成，以实现NAND闪存的强大的新命令，例如连续读取命令及其变体。

10. 发明申请

US20130051154A1 Method for and Flash Memory Device Having Improved Read Performance 有权
标题翻译：具有改进的读取性能的方法和闪存设备
公开(公告)号：US20130051154A1
公开(公告)日：2013-02-28
申请号：US13216103
申请日：2011-08-23
申请人： Oron Michael
发明人： Oron Michael
IPC分类号： G11C16/26 , G11C16/06
CPC分类号： G11C16/26
摘要： A Flash memory device operable under a single-bit or multiple-bit serial protocol is provided with a capability to determine the address boundary condition of an application from the address field of an address boundary configurable (“ABC”) read command. Based on the identified address boundary condition, the Flash memory device may perform multiple sensing of the memory array as required by the ABC read command using optimal internal sense times for each sensing. The number of dummy bytes may be specified for the read command in advance by the user, based on the address boundary of the application and the desired frequency of operation of the Flash memory device. Therefore, Flash memory device read performance is improved both by minimizing the number of dummy bytes in the read command and by optimizing the internal sense times for the read operation.
摘要翻译：在单位或多位串行协议下可操作的闪速存储器件具有从地址边界可配置（ABC）读取命令的地址字段确定应用的地址边界条件的能力。基于所识别的地址边界条件，闪存器件可以使用针对每个感测的最佳内部检测时间来执行ABC读取命令所要求的存储器阵列的多次感测。可以基于应用的地址边界和闪存设备的期望操作频率，由用户预先为读取命令指定虚拟字节的数量。因此，通过最小化读取命令中的虚拟字节数以及通过优化读取操作的内部检测时间来改善闪存器件读取性能。

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