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51. 发明申请

US20100014203A1 Monitoring Method, Circuit, and System 有权
标题翻译：监控方法，电路和系统
公开(公告)号：US20100014203A1
公开(公告)日：2010-01-21
申请号：US12363095
申请日：2009-01-30
申请人： Ross E. Teggatz , Wayne T. Chen , Brett Smith
发明人： Ross E. Teggatz , Wayne T. Chen , Brett Smith
IPC分类号： G01R19/00 , H02H3/24 , H02H3/20
CPC分类号： H02H3/207 , G01R19/16542 , G01R31/3658 , H02H7/18 , Y10T307/826 , Y10T307/832 , Y10T307/858 , Y10T307/865
摘要： Systems, circuits, and methods are described for providing efficient, monitoring capabilities for providing output reactive to monitored conditions. According to the disclosed methods, steps are included for providing a floating gate monitoring circuit in association with a monitored circuit and programming the floating gate to a selected charge level. The programmed floating gate charge level is then compared with a signal level in a monitored circuit. In an additional step, selected comparison criteria are used for selectably activating output. Exemplary embodiments of methods and associated circuits and systems employing the methods are also disclosed, in which protection for a monitored circuit is provided in the event of undervoltage, undercurrent, overvoltage, or undervoltage. Configurations of preferred embodiments of circuits, systems, and methods using the principles of the invention are disclosed in which ultra-low power is consumed by operation in an “ON” state, and little or no significant power is consumed when operating in an “OFF” state.
摘要翻译：描述了系统，电路和方法，用于提供有效的监控功能，以提供对受监视条件的反应。根据所公开的方法，包括用于提供与被监视电路相关联的浮动栅极监视电路并将浮动栅极编程为所选择的电荷电平的步骤。然后将编程的浮置栅极电荷电平与被监测电路中的信号电平进行比较。在附加步骤中，选择的比较标准用于可选择地激活输出。还公开了采用这些方法的方法和相关电路和系统的示例性实施例，其中在欠电压，欠电流，过电压或欠电压的情况下提供对被监控电路的保护。公开了使用本发明的原理的电路，系统和方法的优选实施例的配置，其中超低功耗在“接通”状态下操作消耗，并且当以“关” “状态。

52. 发明授权

US06678829B1 System and method of regulating the distribution of power throughout a system through the use of uni-directional and bi-directional switches 有权
标题翻译：通过使用单向和双向开关来调节整个系统的功率分配的系统和方法
公开(公告)号：US06678829B1
公开(公告)日：2004-01-13
申请号：US09596451
申请日：2000-06-19
申请人： Ross E. Teggatz , David J. Baldwin , Sanmukh M. Patel , Juan F. Alvarez
发明人： Ross E. Teggatz , David J. Baldwin , Sanmukh M. Patel , Juan F. Alvarez
IPC分类号： G06F128
CPC分类号： G06F1/266 , G06F1/26
摘要： An integrated solution to power management and distribution on a power bus, such as needed for an IEEE 1394 compliant expansion board. The integrated circuit includes a uni-directional switch on the input and one or more bi-directional switches on one or more outputs. Current can flow from the system power supply to any connected peripherals via the uni-directional switch and bi-directional switches, or can flow from the peripheral having the highest voltage power supply to the other peripherals via the bi-directional switches, but current will not flow back to the main system because of the unidirectional switch connected to the system power supply. Over-current conditions are quickly detected and the bi-directional switch is opened to prevent damage or over-heating. The switches are preferably fabricated as power FETs using NMOS technology. Several integrated circuits can be cascaded together to accommodate multiple peripherals.
摘要翻译：电源总线上的电源管理和分配的集成解决方案，如IEEE 1394兼容扩展板所需。集成电路包括输入上的单向开关和一个或多个输出上的一个或多个双向开关。电流可以通过单向开关和双向开关从系统电源流向任何连接的外围设备，或者可以通过双向开关从具有最高电压电源的外围设备流向其他外设，但是当前将由于单向开关连接到系统电源，不会流回主系统。快速检测过电流状态，并打开双向开关以防止损坏或过热。这些开关优选地使用NMOS技术制造为功率FET。几个集成电路可以级联在一起以适应多个外围设备。

53. 发明授权

US06650100B1 Bootstrap technique for a multiple mode switching regulator 有权
标题翻译：多模开关稳压器的自举技术
公开(公告)号：US06650100B1
公开(公告)日：2003-11-18
申请号：US10233811
申请日：2002-09-03
申请人： James A. Kohout , David J. Baldwin , Ross E. Teggatz
发明人： James A. Kohout , David J. Baldwin , Ross E. Teggatz
IPC分类号： G05F1563
CPC分类号： H02M3/1582 , G05F1/613 , H02M2001/0006 , H02M2001/009 , H03K17/063
摘要： A multiple mode switching regulator with a bootstrap technique includes an inductor 20; a high side input switch 22 coupled to a first end of the inductor 20; a low side input switch 24 coupled to the first end of the inductor 20; a high side driver 34 coupled to a control node of the high side input switch 22; a low side driver 36 coupled to a control node of the low side input switch 24; a high side output switch 26 coupled to a second end of the inductor 20; a low side output switch 28 coupled to the second end of the inductor 20; a first bootstrap capacitor 30 coupled between the first end of the inductor 20 and a voltage supply node of the high side driver 34; a second bootstrap capacitor 32 coupled between the second end of the inductor 20 and a voltage supply node of the low side driver 36; and a first diode 40 coupled between the voltage supply node of the high side driver 34 and the voltage supply node of the low side driver 36. The two bootstrap capacitors 30 and 32 are employed on both sides of inductor 20 to provide gate voltage to high side input switch 22 through high side driver 34 in any mode of operation. This allows the regulator to work in three modes of operation without different external components or configurations depending on the mode.
摘要翻译：具有自举技术的多模开关调节器包括电感器20; 耦合到电感器20的第一端的高侧输入开关22; 耦合到电感器20的第一端的低侧输入开关24; 耦合到高侧输入开关22的控制节点的高侧驱动器34; 耦合到低侧输入开关24的控制节点的低侧驱动器36; 耦合到电感器20的第二端的高侧输出开关26; 耦合到电感器20的第二端的低侧输出开关28; 耦合在电感器20的第一端和高侧驱动器34的电压供应节点之间的第一自举电容器30; 耦合在电感器20的第二端和低侧驱动器36的电压供应节点之间的第二自举电容器32; 以及耦合在高侧驱动器34的电压供应节点和低侧驱动器36的电压供应节点之间的第一二极管40.两个自举电容器30和32用于电感器20的两侧以将栅极电压提供到高电平在任何操作模式下通过高侧驱动器34进行侧面输入开关22。这允许调节器在三种工作模式下工作，而不需要不同的外部组件或配置，这取决于模式。

54. 发明授权

US06486740B1 Method and system for dynamic compensation 有权
标题翻译：动态补偿方法和系统
公开(公告)号：US06486740B1
公开(公告)日：2002-11-26
申请号：US09651568
申请日：2000-08-28
申请人： David J. Baldwin , Ross E. Teggatz , Joseph A. Devore
发明人： David J. Baldwin , Ross E. Teggatz , Joseph A. Devore
IPC分类号： H03F114
CPC分类号： H03F1/14
摘要： One aspect of the invention is an integrated circuit (10 or 110) comprising an amplifier (11 or 111) having at least two poles in its frequency response and an output impedance compensation circuit (M1A, M2, M3, AC1 or M1A, M2, M3, M4, AC1) coupled to an output node (30) of the amplifier (11 or 111). The output impedance compensation circuit (M1A, M2, M3, AC1 or M1A, M2, M3, M4, AC1) is operable to create a feedback signal proportional to the impedance of an output load (50) coupled to the output node (30), and create a zero in the frequency response of the amplifier (11 or 111) in response to the feedback signal between the at least two poles.
摘要翻译：本发明的一个方面是一种集成电路（10或110），包括在其频率响应中具有至少两个极的放大器（11或111）和输出阻抗补偿电路（M1A，M2，M3，AC1或M1A，M2， M3，M4，AC1）耦合到放大器（11或111）的输出节点（30）。输出阻抗补偿电路（M1A，M2，M3，AC1或M1A，M2，M3，M4，AC1）可操作以产生与耦合到输出节点（30）的输出负载（50）的阻抗成比例的反馈信号，，并且响应于至少两个极之间的反馈信号，在放大器（11或111）的频率响应中产生零。

55. 发明授权

US06376870B1 Low voltage transistors with increased breakdown voltage to substrate 有权
标题翻译：具有对衬底的击穿电压增加的低压晶体管
公开(公告)号：US06376870B1
公开(公告)日：2002-04-23
申请号：US09658202
申请日：2000-09-08
申请人： John H. Carpenter, Jr. , Joseph A. Devore , Toru Tanaka , Ross E. Teggatz
发明人： John H. Carpenter, Jr. , Joseph A. Devore , Toru Tanaka , Ross E. Teggatz
IPC分类号： H01L2972
CPC分类号： H01L21/823493 , H01L27/088 , H01L29/1087
摘要： A high-breakdown voltage transistor (30; 30′) is disclosed. The transistor (30; 30′) is formed into a well arrangement in which a shallow, heavily doped, well (44) is disposed at least partially within a deeper, more lightly-doped well (50), both formed into an epitaxial layer (43) of the substrate (42). The deep well (50) is also used, by itself, for the formation of high-voltage transistors, while the shallower well (44) is used by itself in low-voltage, high-performance transistors. This construction permits the use of high-performance, and precisely matching, transistors in high bias voltage applications, without fear of body-to-substrate (or “back-gate-to-substrate”) junction breakdown.
摘要翻译：公开了一种高耐压晶体管（30; 30'）。晶体管（30; 30'）形成为阱布置，其中浅的，重掺杂的阱（44）至少部分地设置在更深，更轻掺杂的阱（50）内，两者都形成为外延层（42）的（43）。深阱（50）本身也用于形成高压晶体管，而较浅的阱（44）本身用于低电压，高性能的晶体管。这种结构允许在高偏压应用中使用高性能和精确匹配的晶体管，而不用担心体对衬底（或“背栅极到衬底”）结击穿。

56. 发明授权

US06300922B1 Driver system and method for a field emission device 有权
标题翻译：用于场发射装置的驱动器系统和方法
公开(公告)号：US06300922B1
公开(公告)日：2001-10-09
申请号：US09224978
申请日：1999-01-04
申请人： Ross E. Teggatz
发明人： Ross E. Teggatz
IPC分类号： G09G322
CPC分类号： G09G3/22 , G09G3/2014 , G09G2330/021
摘要： A field emission device (10) for reducing the power dissipation of an array (14) includes video controller (12) coupled to array (14) by memory (13), column drivers (16), row drivers (20), and anode power supply (22). Column drivers (16) includes PWM circuit (17) coupled to signal conditioner (18). Signal conditioner (18) receives input digital signal (24) from PWM circuit (17) and generates output digital signal (26) that reduces the frequency of state transitions of signal (24) while maintaining the same duty cycle as that of signal (24). This reduces the power dissipation of parasitic capacitances (36) associated with array (14) pursuant to the equation P=½CV2f.
摘要翻译：用于减少阵列（14）的功率消耗的场致发射装置（10）包括由存储器（13），列驱动器（16），行驱动器（20）和阳极（14）耦合到阵列（14）的视频控制器（12）电源（22）。列驱动器（16）包括耦合到信号调节器（18）的PWM电路（17）。信号调节器（18）从PWM电路（17）接收输入数字信号（24），并产生输出数字信号（26），其在保持与信号（24）相同的占空比的同时降低信号（24）的状态转换频率）。这降低了与阵列（14）相关联的寄生电容（36）根据等式P =½CV2f的功耗。

57. 发明授权

US06169309A High breakdown-voltage transistor with transient protection 有权
标题翻译：具有瞬态保护功能的高击穿电压晶体管
公开(公告)号：US06169309A
公开(公告)日：2001-01-02
申请号：US09159947
申请日：1998-09-24
申请人： Ross E. Teggatz , Joseph A. Devore , David J. Baldwin
发明人： Ross E. Teggatz , Joseph A. Devore , David J. Baldwin
IPC分类号： H01L2976
CPC分类号： H01L27/0251
摘要： A circuit for protecting a transistor against electrical transients. The circuit comprises a first diode coupled between a first terminal coupled to a power supply and a control terminal of the protected transistor. The circuit also comprises a second diode and a resistor coupling the control terminal of the protected transistor to a reference potential. A second transistor is coupled in shunt to the protected transistor. The voltage on the control terminal of the second transistor is determined by the current through the resistor. The embodiments may be implemented in an integrated circuit wherein the second, shunting transistor is formed from parasitic elements within the semiconductor body in which the protected transistor is formed. In one embodiment, the protected MOS transistor is formed in an n-well 504 and a shunting bipolar transistor is formed between the n-well 504 and an n-doped guard ring 500 formed adjacent to the n-well in the p-doped substrate 508.
摘要翻译：用于保护晶体管免受电瞬态的电路。电路包括耦合在耦合到电源的第一端子和受保护晶体管的控制端子之间的第一二极管。该电路还包括将受保护晶体管的控制端耦合到参考电位的第二二极管和电阻器。第二晶体管耦合到分流到保护晶体管。第二晶体管的控制端子上的电压由通过电阻器的电流决定。实施例可以在集成电路中实现，其中第二分流晶体管由形成有保护晶体管的半导体主体内的寄生元件形成。在一个实施例中，被保护的MOS晶体管形成在n阱504中，并且分流双极晶体管形成在n阱504和邻近p掺杂衬底中的n阱附近形成的n掺杂保护环500之间 508。

58. 发明授权

US6144070A High breakdown-voltage transistor with electrostatic discharge protection 有权
标题翻译：具有静电放电保护的高击穿电压晶体管
公开(公告)号：US6144070A
公开(公告)日：2000-11-07
申请号：US141496
申请日：1998-08-28
申请人： Joseph A. Devore , Ross E. Teggatz , David J. Baldwin
发明人： Joseph A. Devore , Ross E. Teggatz , David J. Baldwin
IPC分类号： H01L23/60 , H01L27/02 , H01L29/06 , H01L29/40 , H01L29/739 , H01L29/78 , H01L29/76 , H01L23/58 , H01L23/62 , H01L29/94
CPC分类号： H01L29/7816 , H01L23/60 , H01L27/0262 , H01L29/0878 , H01L29/402 , H01L29/7393 , H01L29/7436 , H01L29/7813 , H01L2924/0002
摘要： A transistor including a source region 506 in a semiconductor body 502; a bulk region 508 in the semiconductor body adjacent the source region; a drain region in the semiconductor body adjacent the bulk region but opposite the source region, the drain region including doped regions 504,514 of n and p dopant types; and a field plate 516 formed over the semiconductor body adjacent the drain region between the drain region and the bulk region.
摘要翻译：一种晶体管，包括半导体本体502中的源极区域506; 邻近源极区域的半导体本体区域508; 所述半导体本体中的漏极区域邻近所述体区域但与所述源极区域相对，所述漏极区域包括n和p掺杂剂类型的掺杂区域504,514; 以及形成在半导体本体上的与漏极区域和主体区域之间的漏极区域相邻的场板516。

59. 发明授权

US5892283A Connection of active circuitry via wire bonding procedure 失效
标题翻译：通过接线方法连接有源电路
公开(公告)号：US5892283A
公开(公告)日：1999-04-06
申请号：US991118
申请日：1997-12-16
申请人： David John Baldwin , Ross E. Teggatz
发明人： David John Baldwin , Ross E. Teggatz
IPC分类号： H01L21/66 , H01L21/60 , H01L23/485 , H01L23/58 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/05 , H01L22/32 , H01L2224/05554 , H01L2224/05599 , H01L2224/05624 , H01L2224/05647 , H01L2224/05666 , H01L2224/05684 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/05042 , H01L2924/12035 , H01L2924/14
摘要： A method of fabricating a bond and the bond. The process includes providing a lower level (M1,13, 15) of electrically conductive metal disposed on a substrate having a pair of spaced apart sections. An electrically insulating layer (11) is then disposed over the lower level and vias (23) are formed in the electrically insulating layer, individual ones of the vias extending to one of the spaced apart section of the lower level. An upper level of electrically conductive metal (M2, 17, 19) is disposed on the electrically insulating layer, the upper level having a pair of spaced apart sections, each coupled to one of the sections of the lower level through a via. One of the pair of spaced apart sections of the lower level is preferably essentially U-shaped (13) and the other section (15) of the lower level is essentially rectangular shaped and extends into the open end of the "U". One of the pair of spaced apart section of the upper level is essentially rectangular (17) with a rectangular aperture at its central region and the other section of the upper level (19) is essentially rectangular and disposed within the rectangular aperture. A bond (23) is formed completely enclosing the spaced apart sections of the upper level.
摘要翻译：一种制造键和键的方法。该方法包括提供设置在具有一对间隔开的部分的基底上的较低级别的导电金属（M1,13,15）。然后将电绝缘层（11）设置在下层上，并且通孔（23）形成在电绝缘层中，各个通孔延伸到下层的间隔开的部分之一。导电金属（M2,17,19）的上层设置在电绝缘层上，上层具有一对间隔开的部分，每个部分通过通孔连接到下层的一个部分。较低级别的一对间隔开的部分之一优选地基本上为U形（13），并且下层的另一部分（15）基本上为矩形并且延伸到“U”的开口端。上层的一对间隔开的部分基本上是矩形（17），在其中心区域具有矩形孔，而上层（19）的另一部分基本上是矩形的并且设置在矩形孔内。形成完全包围上层间隔开的部分的粘结（23）。

60. 发明授权

US5691940A Method and apparatus for programmable current limits 失效
标题翻译：用于可编程电流限制的方法和装置
公开(公告)号：US5691940A
公开(公告)日：1997-11-25
申请号：US656553
申请日：1996-05-31
申请人： Andrew Marshall , Kenneth G. Buss , Ross E. Teggatz , Joe A. Devore
发明人： Andrew Marshall , Kenneth G. Buss , Ross E. Teggatz , Joe A. Devore
IPC分类号： G01R31/30 , G06F1/30 , G11C11/34
CPC分类号： G01R31/3004 , G06F1/30
摘要： A method and apparatus for programmable current limits is provided in which a plurality of current limit programmable cells (44 and 46) are programmed with a current limit. Output circuitry (14 and 16) which outputs current is limited by current limit circuitry (20, 24, 38, 40, and 42) when the output current reaches the programmed current limit.
摘要翻译：提供了一种用于可编程电流限制的方法和装置，其中多个限流可编程单元（44和46）被编程为电流限制。当输出电流达到编程电流极限时，输出电流的输出电路（14和16）受限流电路（20,24,38,40和42）限制。

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