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1. 发明授权

US09530555B2 Wireless power transmittal 有权
标题翻译：无线功率传输
公开(公告)号：US09530555B2
公开(公告)日：2016-12-27
申请号：US13434807
申请日：2012-03-29
申请人： Ross E. Teggatz , Wayne T. Chen
发明人： Ross E. Teggatz , Wayne T. Chen
IPC分类号： H01F38/00 , H01F38/14 , H02J5/00
CPC分类号： H01F38/14 , H02J5/005 , H02J7/025 , H02J50/12 , H02J50/50 , H02J50/80 , H02J50/90
摘要： Wireless power transmittal apparatus and systems are disclosed in which transmitter and receiver inductors, or coils, are coupled in configurations for wirelessly transferring power and/or data among them. In preferred implementations, a plurality of non-coplanar primary side coils are provided in power transmittal apparatus for transmitting power, or power and data.
摘要翻译：公开了无线电力传输装置和系统，其中发射机和接收机电感器或线圈以用于在它们之间无线传输功率和/或数据的配置耦合。在优选实施方案中，在功率传输装置中提供多个非共面初级侧线圈，用于发射功率或功率和数据。

2. 发明授权

US09343988B2 Current mode regulator 有权
标题翻译：电流模式调节器
公开(公告)号：US09343988B2
公开(公告)日：2016-05-17
申请号：US13567039
申请日：2012-08-04
申请人： Ross E. Teggatz , David D. Briggs , Amer H. Atrash , Wayne T. Chen
发明人： Ross E. Teggatz , David D. Briggs , Amer H. Atrash , Wayne T. Chen
IPC分类号： H02M3/24 , H02M3/338 , H02M1/42 , H02M1/00
CPC分类号： H02M3/33507 , H02M1/08 , H02M1/14 , H02M1/42 , H02M1/4225 , H02M3/3387 , H02M2001/0006 , H02M2001/0009 , H02M2001/0032 , H05B33/0815 , H05B33/0851 , Y02B70/126 , Y02B70/16
摘要： Circuits, systems, and methods of current mode regulation include a primary side for receiving an input signal and a secondary for outputting an output signal. A regulator spans the primary and secondary sides in a configuration by which the input signal may be rectified and thereafter provided to the output node as an output signal. A current monitor is provided at the output node for comparing the output signal to a reference. A communication link is included for providing feedback to the primary side of the regulator for use in regulating the signal.
摘要翻译：电流模式调节的电路，系统和方法包括用于接收输入信号的初级侧和用于输出输出信号的次级。调节器跨越主要和次要侧面，通过该配置可以对输入信号进行整流，此后将其提供给输出节点作为输出信号。在输出节点处提供电流监视器，用于将输出信号与参考值进行比较。包括通信链路，用于向调节器的初级侧提供反馈信号以用于调节信号。

3. 发明申请

US20130062967A1 TUNABLE SYNCHRONOUS RECTIFIER 有权
标题翻译：同步同步整流器（TUNABLE SYNCHRONOUS RECTIFIER）
公开(公告)号：US20130062967A1
公开(公告)日：2013-03-14
申请号：US13616726
申请日：2012-09-14
申请人： Ross E. Teggatz , Amer H. Atrash , Jonathan R. Knight
发明人： Ross E. Teggatz , Amer H. Atrash , Jonathan R. Knight
IPC分类号： H01F38/14
CPC分类号： H02J50/12 , H01F38/14 , H02J5/005 , H02J50/80
摘要： A system for power transfer is provided. In one exemplary embodiment, the system includes an inductive power device, such as a device that transmits or receives power over an inductive coupling. For example, an adjustable impedance is coupled to the inductive power device, where the adjustable impedance is used for dynamically controlling the power gain in the inductive power device, such as by damping power generated by circuit impedances, such as inductances, capacitances or resistances, and combinations thereof.
摘要翻译：提供电力传输系统。在一个示例性实施例中，系统包括感应功率器件，例如通过感应耦合发送或接收功率的器件。例如，可调阻抗耦合到感应功率器件，其中可调阻抗用于动态地控制感应功率器件中的功率增益，例如通过阻抗由电路阻抗（例如电感，电容或电阻）产生的功率，及其组合。

4. 发明申请

US20120087187A1 Method for Programming a Floating Gate 有权
标题翻译：浮动门编程方法
公开(公告)号：US20120087187A1
公开(公告)日：2012-04-12
申请号：US13327364
申请日：2011-12-15
申请人： Ross E. Teggatz , Wayne T. Chen , Brett Smith , Eric Blackall
发明人： Ross E. Teggatz , Wayne T. Chen , Brett Smith , Eric Blackall
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C16/10 , G11C16/0408 , G11C16/3468 , G11C27/005
摘要： The invention provides methods for programming a floating gate. A floating gate tunneling device is used with an analog comparing device in a circuit having a floating reference node and an offset-mitigating feedback loop for iteratively programming a floating gate, or multiple floating gates.
摘要翻译：本发明提供了编程浮动栅极的方法。在具有浮置参考节点和偏移减轻反馈环路的电路中使用浮动栅极隧道装置与模拟比较装置，用于迭代地编程浮动栅极或多个浮动栅极。

5. 再颁专利

USRE42494E1 Preventing drain to body forward bias in a MOS transistor 有权
标题翻译：防止在MOS晶体管中排出体内正向偏置
公开(公告)号：USRE42494E1
公开(公告)日：2011-06-28
申请号：US11800071
申请日：2007-05-03
申请人： Ross E. Teggatz
发明人： Ross E. Teggatz
IPC分类号： H03K5/003
CPC分类号： H03K5/003
摘要： A voltage level shifting circuit (FIG. 4) has a plurality of PMOS transistors M1, M2, M3 connected in parallel for respectively driving a capacitive load CL with a selected different voltage level V1, V2 or V3. Transistors M1, M2, M3 are controlled so that one of them is placed in the ON condition, with the others in the OFF condition, to connect one of the voltages V1, V2 or V3 to charge the load CL. The largest voltage transistor M3 has its body connected to its source. The lower voltage transistors M1, M2 have their bodies respectively connected to switches S1, S2, which connect the bodies to the sources when the transistors are placed in the ON condition and connect the bodies to the highest voltage V3 when the transistors are placed in the OFF condition.
摘要翻译：电压电平移动电路（图4）具有并联连接的多个PMOS晶体管M1，M2，M3，分别驱动具有所选择的不同电压电平V1，V2或V3的电容性负载CL。控制晶体管M1，M2，M3，使其中的一个被置于ON状态，其他的处于OFF状态，以连接电压V1，V2或V3中的一个来对负载CL充电。最大的电压晶体管M3的主体连接到其源极。低电压晶体管M1，M2的主体分别连接到开关S1，S2，开关S1，S2将晶体管置于ON状态时将主体连接到源极，并将晶体管放置在 OFF状态。

6. 发明授权

US06407626B1 Analog filtering with symmetrical timing using a single comparator 有权
标题翻译：使用单个比较器进行对称定时的模拟滤波
公开(公告)号：US06407626B1
公开(公告)日：2002-06-18
申请号：US09715759
申请日：2000-11-17
申请人： John H. Carpenter, Jr. , Joseph A. Devore , Tohru Tanaka , Ross E. Teggatz
发明人： John H. Carpenter, Jr. , Joseph A. Devore , Tohru Tanaka , Ross E. Teggatz
IPC分类号： H03K500
CPC分类号： H03K5/1252 , H03K5/082
摘要： Provided is a symmetrical filter that uses a single comparator. In addition to a voltage divider, a current regulator, and a comparator, the filter of the invention provides control logic that turns on or off a pull up switch and/or pull down switch in order to fully charge or fully discharge a capacitor. Accordingly, in one aspect, the invention is a control logic for a symmetrical filter. Furthermore, timing logic is provided to provide for a more rigorous symmetrical filter performance.
摘要翻译：提供了使用单个比较器的对称滤波器。除了分压器，电流调节器和比较器之外，本发明的滤波器还提供控制逻辑，其接通或断开上拉开关和/或下拉开关以便完全充电或完全放电电容器。因此，一方面，本发明是用于对称滤波器的控制逻辑。此外，提供定时逻辑以提供更严格的对称滤波器性能。

7. 发明授权

US06373343B1 Oscillator and method 有权
标题翻译：振荡器和方法
公开(公告)号：US06373343B1
公开(公告)日：2002-04-16
申请号：US09649367
申请日：2000-08-28
申请人： David J. Baldwin , Christopher M. Cooper , Joseph A. Devore , Ross E. Teggatz
发明人： David J. Baldwin , Christopher M. Cooper , Joseph A. Devore , Ross E. Teggatz
IPC分类号： H03B524
CPC分类号： H03K3/0231
摘要： An integrated circuit (10) is disclosed comprising a fundamental frequency oscillator comprising a reference node (32) whose voltage varies between a high threshold and a low threshold. The fundamental frequency oscillator is operable to generate a first output at the fundamental frequency on a first output node (36). The integrated circuit (10) also comprises a circuit (C2) coupled to the reference node. The circuit (C2) is operable to sense the voltage at the reference node (32), to determine when the voltage exceeds an intermediate threshold between the high threshold and the low threshold, and to generate a second output in response to the determination. The integrated circuit (10) also comprises logic (40) coupled to the circuit (C2) and load circuitry (50) coupled to the logic (40). The logic (40) is operable to generate an output signal at an output frequency greater than the fundamental frequency in response to the second output and the first output.
摘要翻译：公开了一种集成电路（10），其包括基频振荡器，其包括其电压在高阈值和低阈值之间变化的参考节点（32）。基频振荡器可操作以在第一输出节点（36）上产生基频处的第一输出。集成电路（10）还包括耦合到参考节点的电路（C2）。电路（C2）可操作以感测参考节点（32）处的电压，以确定电压何时超过高阈值和低阈值之间的中间阈值，并响应于该确定产生第二输出。集成电路（10）还包括耦合到电路（C2）的逻辑（40）和耦合到逻辑（40）的负载电路（50）。逻辑（40）可操作以响应于第二输出和第一输出而以大于基频的输出频率产生输出信号。

8. 发明授权

US06215637B1 Internal voltage clamp protection circuit without parasitic cross-talk 有权
标题翻译：内部电压钳保护电路无寄生串扰
公开(公告)号：US06215637B1
公开(公告)日：2001-04-10
申请号：US09290283
申请日：1999-04-13
申请人： Ross E. Teggatz , John H. Carpenter, Jr. , Tohru Tanaka , Joseph A. Devore
发明人： Ross E. Teggatz , John H. Carpenter, Jr. , Tohru Tanaka , Joseph A. Devore
IPC分类号： H02H322
CPC分类号： H01L27/0259
摘要： A internal circuitry protection scheme which protects on-IC circuitry when an external pin is shorted to a higher than normal voltage. The disclosed solution eliminates cross-talk due to a parasitic NPN.
摘要翻译：内部电路保护方案，当外部引脚短路到高于正常电压时，保护IC上的电路。所公开的解决方案消除了由于寄生NPN引起的串扰。

9. 发明授权

US5869882A Zener diode structure with high reverse breakdown voltage 失效
标题翻译：具有高反向击穿电压的齐纳二极管结构
公开(公告)号：US5869882A
公开(公告)日：1999-02-09
申请号：US724575
申请日：1996-09-30
申请人： Wayne T. Chen , Ross E. Teggatz , Taylor R. Efland
发明人： Wayne T. Chen , Ross E. Teggatz , Taylor R. Efland
IPC分类号： H01L29/866 , H01L29/861 , H01L31/107
CPC分类号： H01L29/866 , H01L29/0692 , H01L29/402 , H01L29/66106
摘要： A zener diode capable of breakdown at much higher voltages than in the prior art is fabricated by providing a semiconductor substrate of a first conductivity type having an opposite conductivity type first tank disposed therein. The first tank includes relatively lower and relatively higher resistivity portions, the relatively lower doped portion isolating the relatively higher doped portion from the substrate. A first region of first conductivity type is disposed in the higher doped portion and a second region of opposite conductivity type and more highly doped than the first tank is spaced from the first region. Structure is provided between the first and second regions for repelling majority charge carriers associated with the opposite conductivity type which can be a field plate spaced from the first tank; a portion at the surface of the first tank having the first conductivity type; or a tank, of first conductivity type disposed in the first tank, abutting the first region, extending more deeply into the first tank than does the first region and more lightly doped than the first region. In accordance with a further embodiment, the diode includes a semiconductor substrate, a first tank portion disposed in the substrate and a second tank portion disposed in the first tank portion as in the prior embodiments. A first region of first conductivity type is disposed in the second tank portion and extends into the first tank portion. A second region of opposite conductivity type more highly doped than the first tank portion is disposed in the first tank portion and spaced from the first region.
摘要翻译：能够以比现有技术高得多的电压击穿的齐纳二极管通过提供具有设置在其中的具有相反导电类型的第一容器的第一导电类型的半导体衬底来制造。第一罐包括相对较低和相对较高的电阻率部分，相对较低的掺杂部分将相对较高的掺杂部分与衬底隔离。第一导电类型的第一区域设置在较高掺杂部分中，并且具有相反导电类型的第二区域和比第一容器更高掺杂的第二区域与第一区域间隔开。在第一和第二区域之间提供结构，用于排斥与相反导电类型相关联的多数电荷载体，其可以是与第一罐间隔开的场板; 第一罐的表面上具有第一导电类型的部分; 或第一导电类型的罐，邻接第一区域，比第一区域更深地延伸到第一槽中，并且比第一区域更轻地掺杂。根据另一实施例，二极管包括半导体衬底，设置在衬底中的第一容器部分和如先前实施例中那样设置在第一容器部分中的第二容器部分。第一导电类型的第一区域设置在第二罐部分中并延伸到第一罐部分中。与第一容器部分相比更高掺杂的相反导电类型的第二区域设置在第一罐部分中并与第一区域间隔开。

10. 发明授权

US5579193A Reducing the natural current limit in a power MOS device by reducing the gate-source voltage 失效
标题翻译：通过降低栅源电压降低功率MOS器件的自然电流限制
公开(公告)号：US5579193A
公开(公告)日：1996-11-26
申请号：US486926
申请日：1995-06-07
申请人： Thomas A. Schmidt , Ross E. Teggatz , Joseph A. Devore
发明人： Thomas A. Schmidt , Ross E. Teggatz , Joseph A. Devore
IPC分类号： H03K17/082 , H02H7/10
CPC分类号： H03K17/0822
摘要： In accordance with the present invention, an output current limit circuit for protecting a power MOS output device of an integrated circuit from an excessive drain current comprises a power MOS device 110, sensing circuitry 30 to sense a predetermined trigger current, and limitation circuitry 20 to reduce a gate-source voltage on MOS output device 110 to a predetermined approximately fixed value. A drain current I.sub.D flows through power MOS device 110 from output terminal 102 in response to the gate-source voltage. A short circuit condition may allow an excessive amount of drain current I.sub.D to flow through output terminal 102. The gate-source voltage is reduced in response to sensing the trigger current. Reducing the gate-source voltage raises a drain-source resistance of MOS device 110 and reduces drain current I.sub.D so that MOS device 110 is not damaged by the short circuit condition.
摘要翻译：根据本发明，用于保护集成电路的功率MOS输出装置与过剩漏极电流的输出限流电路包括功率MOS器件110，检测电路30以感测预定的触发电流，以及限制电路20至将MOS输出装置110上的栅极 - 源极电压降低到预定的大致固定值。漏极电流ID响应于栅极 - 源极电压从输出端子102流过功率MOS器件110。短路状态可允许过量的漏极电流ID流过输出端子102.响应于感测触发电流，栅极 - 源极电压被降低。降低栅极 - 源极电压会提高MOS器件110的漏极 - 源极电阻并且减少漏极电流ID，使得MOS器件110不会被短路状态损坏。

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