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1. 发明授权

US6111737A Internal voltage protection circuit 有权
标题翻译：内部电压保护电路
公开(公告)号：US6111737A
公开(公告)日：2000-08-29
申请号：US267490
申请日：1999-03-11
申请人： David J. Baldwin , Ross E. Teggatz , John H. Carpenter, Jr. , Joseph A. Devore
发明人： David J. Baldwin , Ross E. Teggatz , John H. Carpenter, Jr. , Joseph A. Devore
IPC分类号： H01L27/02 , H02H3/20
CPC分类号： H01L27/0251
摘要： An internal circuitry protection scheme which protects on-IC circuitry when an external regulator voltage pin is shorted to a higher voltage. The circuit prevents damage to the on-die circuitry that is on the internal voltage rail, by clamping the received voltage, thereby eliminating the chance of damaging the on die circuitry. The circuit offers protection even if the voltage difference is large, but the difference remains small between the internal rail and the external regulated voltage under normal operation.
摘要翻译：内部电路保护方案，当外部稳压器电压引脚短路到较高电压时，保护IC内部电路。该电路通过钳位接收到的电压来防止损坏内部电压轨上的片上电路，从而消除了损坏管芯电路的可能性。即使电压差大，电路也能提供保护，但在正常工作状态下，内部轨道与外部调节电压之间的差异仍然很小。

2. 发明授权

US06373343B1 Oscillator and method 有权
标题翻译：振荡器和方法
公开(公告)号：US06373343B1
公开(公告)日：2002-04-16
申请号：US09649367
申请日：2000-08-28
申请人： David J. Baldwin , Christopher M. Cooper , Joseph A. Devore , Ross E. Teggatz
发明人： David J. Baldwin , Christopher M. Cooper , Joseph A. Devore , Ross E. Teggatz
IPC分类号： H03B524
CPC分类号： H03K3/0231
摘要： An integrated circuit (10) is disclosed comprising a fundamental frequency oscillator comprising a reference node (32) whose voltage varies between a high threshold and a low threshold. The fundamental frequency oscillator is operable to generate a first output at the fundamental frequency on a first output node (36). The integrated circuit (10) also comprises a circuit (C2) coupled to the reference node. The circuit (C2) is operable to sense the voltage at the reference node (32), to determine when the voltage exceeds an intermediate threshold between the high threshold and the low threshold, and to generate a second output in response to the determination. The integrated circuit (10) also comprises logic (40) coupled to the circuit (C2) and load circuitry (50) coupled to the logic (40). The logic (40) is operable to generate an output signal at an output frequency greater than the fundamental frequency in response to the second output and the first output.
摘要翻译：公开了一种集成电路（10），其包括基频振荡器，其包括其电压在高阈值和低阈值之间变化的参考节点（32）。基频振荡器可操作以在第一输出节点（36）上产生基频处的第一输出。集成电路（10）还包括耦合到参考节点的电路（C2）。电路（C2）可操作以感测参考节点（32）处的电压，以确定电压何时超过高阈值和低阈值之间的中间阈值，并响应于该确定产生第二输出。集成电路（10）还包括耦合到电路（C2）的逻辑（40）和耦合到逻辑（40）的负载电路（50）。逻辑（40）可操作以响应于第二输出和第一输出而以大于基频的输出频率产生输出信号。

3. 发明授权

US06486740B1 Method and system for dynamic compensation 有权
标题翻译：动态补偿方法和系统
公开(公告)号：US06486740B1
公开(公告)日：2002-11-26
申请号：US09651568
申请日：2000-08-28
申请人： David J. Baldwin , Ross E. Teggatz , Joseph A. Devore
发明人： David J. Baldwin , Ross E. Teggatz , Joseph A. Devore
IPC分类号： H03F114
CPC分类号： H03F1/14
摘要： One aspect of the invention is an integrated circuit (10 or 110) comprising an amplifier (11 or 111) having at least two poles in its frequency response and an output impedance compensation circuit (M1A, M2, M3, AC1 or M1A, M2, M3, M4, AC1) coupled to an output node (30) of the amplifier (11 or 111). The output impedance compensation circuit (M1A, M2, M3, AC1 or M1A, M2, M3, M4, AC1) is operable to create a feedback signal proportional to the impedance of an output load (50) coupled to the output node (30), and create a zero in the frequency response of the amplifier (11 or 111) in response to the feedback signal between the at least two poles.
摘要翻译：本发明的一个方面是一种集成电路（10或110），包括在其频率响应中具有至少两个极的放大器（11或111）和输出阻抗补偿电路（M1A，M2，M3，AC1或M1A，M2， M3，M4，AC1）耦合到放大器（11或111）的输出节点（30）。输出阻抗补偿电路（M1A，M2，M3，AC1或M1A，M2，M3，M4，AC1）可操作以产生与耦合到输出节点（30）的输出负载（50）的阻抗成比例的反馈信号，，并且响应于至少两个极之间的反馈信号，在放大器（11或111）的频率响应中产生零。

4. 发明授权

US06169309A High breakdown-voltage transistor with transient protection 有权
标题翻译：具有瞬态保护功能的高击穿电压晶体管
公开(公告)号：US06169309A
公开(公告)日：2001-01-02
申请号：US09159947
申请日：1998-09-24
申请人： Ross E. Teggatz , Joseph A. Devore , David J. Baldwin
发明人： Ross E. Teggatz , Joseph A. Devore , David J. Baldwin
IPC分类号： H01L2976
CPC分类号： H01L27/0251
摘要： A circuit for protecting a transistor against electrical transients. The circuit comprises a first diode coupled between a first terminal coupled to a power supply and a control terminal of the protected transistor. The circuit also comprises a second diode and a resistor coupling the control terminal of the protected transistor to a reference potential. A second transistor is coupled in shunt to the protected transistor. The voltage on the control terminal of the second transistor is determined by the current through the resistor. The embodiments may be implemented in an integrated circuit wherein the second, shunting transistor is formed from parasitic elements within the semiconductor body in which the protected transistor is formed. In one embodiment, the protected MOS transistor is formed in an n-well 504 and a shunting bipolar transistor is formed between the n-well 504 and an n-doped guard ring 500 formed adjacent to the n-well in the p-doped substrate 508.
摘要翻译：用于保护晶体管免受电瞬态的电路。电路包括耦合在耦合到电源的第一端子和受保护晶体管的控制端子之间的第一二极管。该电路还包括将受保护晶体管的控制端耦合到参考电位的第二二极管和电阻器。第二晶体管耦合到分流到保护晶体管。第二晶体管的控制端子上的电压由通过电阻器的电流决定。实施例可以在集成电路中实现，其中第二分流晶体管由形成有保护晶体管的半导体主体内的寄生元件形成。在一个实施例中，被保护的MOS晶体管形成在n阱504中，并且分流双极晶体管形成在n阱504和邻近p掺杂衬底中的n阱附近形成的n掺杂保护环500之间 508。

5. 发明授权

US6144070A High breakdown-voltage transistor with electrostatic discharge protection 有权
标题翻译：具有静电放电保护的高击穿电压晶体管
公开(公告)号：US6144070A
公开(公告)日：2000-11-07
申请号：US141496
申请日：1998-08-28
申请人： Joseph A. Devore , Ross E. Teggatz , David J. Baldwin
发明人： Joseph A. Devore , Ross E. Teggatz , David J. Baldwin
IPC分类号： H01L23/60 , H01L27/02 , H01L29/06 , H01L29/40 , H01L29/739 , H01L29/78 , H01L29/76 , H01L23/58 , H01L23/62 , H01L29/94
CPC分类号： H01L29/7816 , H01L23/60 , H01L27/0262 , H01L29/0878 , H01L29/402 , H01L29/7393 , H01L29/7436 , H01L29/7813 , H01L2924/0002
摘要： A transistor including a source region 506 in a semiconductor body 502; a bulk region 508 in the semiconductor body adjacent the source region; a drain region in the semiconductor body adjacent the bulk region but opposite the source region, the drain region including doped regions 504,514 of n and p dopant types; and a field plate 516 formed over the semiconductor body adjacent the drain region between the drain region and the bulk region.
摘要翻译：一种晶体管，包括半导体本体502中的源极区域506; 邻近源极区域的半导体本体区域508; 所述半导体本体中的漏极区域邻近所述体区域但与所述源极区域相对，所述漏极区域包括n和p掺杂剂类型的掺杂区域504,514; 以及形成在半导体本体上的与漏极区域和主体区域之间的漏极区域相邻的场板516。

6. 发明授权

US06324044B1 Driver for controller area network 有权
标题翻译：控制器区域网络的驱动程序
公开(公告)号：US06324044B1
公开(公告)日：2001-11-27
申请号：US09305571
申请日：1999-05-05
申请人： Ross E. Teggatz , Joseph A. Devore , Timothy J. Legat , Timothy P. Pauletti , David J. Baldwin
发明人： Ross E. Teggatz , Joseph A. Devore , Timothy J. Legat , Timothy P. Pauletti , David J. Baldwin
IPC分类号： H02H100
CPC分类号： G06F13/385
摘要： A controlled area network (CAN) driver provides improved symmetry between its differential output signals CAN-H and CAN-L, and provides protection for its low voltage devices from voltage transients occurring on its output lines. A plurality of CAN drivers 80 are serially interconnected to form a driver system, wherein each downstream driver stage receives a time-delayed form of the digital input signal TxD, each stage providing a time-delayed contribution to the differential output signals of the overall driver system.
摘要翻译：控制区域网络（CAN）驱动器在其差分输出信号CAN-H和CAN-L之间提供改进的对称性，并为其低压器件提供对其输出线路上发生的电压瞬变的保护。多个CAN驱动器80串联互连以形成驱动器系统，其中每个下游驱动器级接收时间延迟形式的数字输入信号TxD，每个级为整个驱动器的差分输出信号提供时间延迟的贡献系统。

7. 发明授权

US06696861B1 Switch mode regulator controller using hybrid technique 有权
标题翻译：使用混合技术的开关模式调节器控制器
公开(公告)号：US06696861B1
公开(公告)日：2004-02-24
申请号：US10285900
申请日：2002-11-01
申请人： David J. Baldwin , Zbigniew J. Lata , Sanmukh M. Patel , Ross E. Teggatz
发明人： David J. Baldwin , Zbigniew J. Lata , Sanmukh M. Patel , Ross E. Teggatz
IPC分类号： H03K1716
CPC分类号： H02M3/156 , H02M3/1563 , H02M3/1588 , Y02B70/1466
摘要： A switch mode controller circuit includes: a hysteretic comparator HYST_COMP for monitoring an output of a switch mode circuit; a standard comparator PHASE_COMP for monitoring a phase of the switch mode circuit; a logic block having a first input coupled to a clock signal generator Oscillator, a second input coupled to an output of the hysteretic comparator HYST_COMP, and a third input coupled to an output of the standard comparator PHASE_COMP, wherein the logic block generates switching cycles based on a fixed ON/OFF time during a first part of a cycle and based on a hysteretic control during a second part of the cycle.
摘要翻译：开关模式控制器电路包括：用于监视开关模式电路的输出的滞后比较器HYST_COMP; 用于监视开关模式电路的相位的标准比较器PHASE_COMP; 逻辑块，其具有耦合到时钟信号发生器振荡器的第一输入，耦合到迟滞比较器HYST_COMP的输出的第二输入和耦合到标准比较器PHASE_COMP的输出的第三输入，其中逻辑块基于在循环的第一部分期间处于固定的ON / OFF时间，并且基于在循环的第二部分期间的滞后控制。

8. 发明授权

US06678829B1 System and method of regulating the distribution of power throughout a system through the use of uni-directional and bi-directional switches 有权
标题翻译：通过使用单向和双向开关来调节整个系统的功率分配的系统和方法
公开(公告)号：US06678829B1
公开(公告)日：2004-01-13
申请号：US09596451
申请日：2000-06-19
申请人： Ross E. Teggatz , David J. Baldwin , Sanmukh M. Patel , Juan F. Alvarez
发明人： Ross E. Teggatz , David J. Baldwin , Sanmukh M. Patel , Juan F. Alvarez
IPC分类号： G06F128
CPC分类号： G06F1/266 , G06F1/26
摘要： An integrated solution to power management and distribution on a power bus, such as needed for an IEEE 1394 compliant expansion board. The integrated circuit includes a uni-directional switch on the input and one or more bi-directional switches on one or more outputs. Current can flow from the system power supply to any connected peripherals via the uni-directional switch and bi-directional switches, or can flow from the peripheral having the highest voltage power supply to the other peripherals via the bi-directional switches, but current will not flow back to the main system because of the unidirectional switch connected to the system power supply. Over-current conditions are quickly detected and the bi-directional switch is opened to prevent damage or over-heating. The switches are preferably fabricated as power FETs using NMOS technology. Several integrated circuits can be cascaded together to accommodate multiple peripherals.
摘要翻译：电源总线上的电源管理和分配的集成解决方案，如IEEE 1394兼容扩展板所需。集成电路包括输入上的单向开关和一个或多个输出上的一个或多个双向开关。电流可以通过单向开关和双向开关从系统电源流向任何连接的外围设备，或者可以通过双向开关从具有最高电压电源的外围设备流向其他外设，但是当前将由于单向开关连接到系统电源，不会流回主系统。快速检测过电流状态，并打开双向开关以防止损坏或过热。这些开关优选地使用NMOS技术制造为功率FET。几个集成电路可以级联在一起以适应多个外围设备。

9. 发明授权

US06650100B1 Bootstrap technique for a multiple mode switching regulator 有权
标题翻译：多模开关稳压器的自举技术
公开(公告)号：US06650100B1
公开(公告)日：2003-11-18
申请号：US10233811
申请日：2002-09-03
申请人： James A. Kohout , David J. Baldwin , Ross E. Teggatz
发明人： James A. Kohout , David J. Baldwin , Ross E. Teggatz
IPC分类号： G05F1563
CPC分类号： H02M3/1582 , G05F1/613 , H02M2001/0006 , H02M2001/009 , H03K17/063
摘要： A multiple mode switching regulator with a bootstrap technique includes an inductor 20; a high side input switch 22 coupled to a first end of the inductor 20; a low side input switch 24 coupled to the first end of the inductor 20; a high side driver 34 coupled to a control node of the high side input switch 22; a low side driver 36 coupled to a control node of the low side input switch 24; a high side output switch 26 coupled to a second end of the inductor 20; a low side output switch 28 coupled to the second end of the inductor 20; a first bootstrap capacitor 30 coupled between the first end of the inductor 20 and a voltage supply node of the high side driver 34; a second bootstrap capacitor 32 coupled between the second end of the inductor 20 and a voltage supply node of the low side driver 36; and a first diode 40 coupled between the voltage supply node of the high side driver 34 and the voltage supply node of the low side driver 36. The two bootstrap capacitors 30 and 32 are employed on both sides of inductor 20 to provide gate voltage to high side input switch 22 through high side driver 34 in any mode of operation. This allows the regulator to work in three modes of operation without different external components or configurations depending on the mode.
摘要翻译：具有自举技术的多模开关调节器包括电感器20; 耦合到电感器20的第一端的高侧输入开关22; 耦合到电感器20的第一端的低侧输入开关24; 耦合到高侧输入开关22的控制节点的高侧驱动器34; 耦合到低侧输入开关24的控制节点的低侧驱动器36; 耦合到电感器20的第二端的高侧输出开关26; 耦合到电感器20的第二端的低侧输出开关28; 耦合在电感器20的第一端和高侧驱动器34的电压供应节点之间的第一自举电容器30; 耦合在电感器20的第二端和低侧驱动器36的电压供应节点之间的第二自举电容器32; 以及耦合在高侧驱动器34的电压供应节点和低侧驱动器36的电压供应节点之间的第一二极管40.两个自举电容器30和32用于电感器20的两侧以将栅极电压提供到高电平在任何操作模式下通过高侧驱动器34进行侧面输入开关22。这允许调节器在三种工作模式下工作，而不需要不同的外部组件或配置，这取决于模式。

10. 发明申请

US20090054023A1 AUDIO AMPLIFIER AND METHODS OF GENERATING AUDIO SIGNALS 有权
标题翻译：音频放大器和音频信号的生成方法
公开(公告)号：US20090054023A1
公开(公告)日：2009-02-26
申请号：US11844860
申请日：2007-08-24
申请人： Ronnie A. Bean , Roy Clifton Jones, III , David J. Baldwin
发明人： Ronnie A. Bean , Roy Clifton Jones, III , David J. Baldwin
IPC分类号： H04B1/16
CPC分类号： H03F3/2173
摘要： Audio amplifiers and methods of generating audio signals are disclosed. A disclosed example amplifier comprises a first driver to receive a first signal; a second driver to receive a second signal; a configurable signal delivery circuit; and a mode selector in communication with the first and second drivers to selectively configure the signal delivery circuit in a voltage boost mode or a voltage buck-boost mode based on a characteristic of the input signal.
摘要翻译：公开了音频放大器和产生音频信号的方法。公开的示例放大器包括：第一驱动器，用于接收第一信号; 接收第二信号的第二驱动器; 可配置信号传送电路; 以及与所述第一和第二驱动器通信的模式选择器，以基于所述输入信号的特性选择性地将所述信号传递电路配置为升压模式或电压降压 - 升压模式。

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