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1. 发明授权

US07516037B2 Method evaluating threshold level of a data cell in a memory device 有权
标题翻译：方法评估存储器件中数据单元的阈值水平
公开(公告)号：US07516037B2
公开(公告)日：2009-04-07
申请号：US11755891
申请日：2007-05-31
申请人： David John Baldwin , Eric Blackall , Joseph Devore , Ross E. Teggatz
发明人： David John Baldwin , Eric Blackall , Joseph Devore , Ross E. Teggatz
IPC分类号： G06F15/00
CPC分类号： G11C16/34
摘要： A method evaluating threshold of a data cell in a memory device including a programming locus coupled with the data cell for receiving a programming signal setting a stored signal level in the data cell and responding to a read signal to indicate the stored signal at a read locus; includes the steps of: (a) in no particular order; (1) selecting a test threshold signal; and (2) setting a read signal at a non-read level; (b) applying the test threshold signal to the programming locus; (c) cycling the read signal between a read level and a non-read level while applying the test threshold signal to the programming locus to present at least two test signals at the read locus when the read signal is at the read level; and (d) while cycling, observing whether the at least two test signals manifest a difference greater than a predetermined amount.
摘要翻译：一种评估存储器件中的数据单元的阈值的方法，包括与所述数据单元耦合的编程轨迹，用于接收在所述数据单元中设置存储的信号电平的编程信号，并且响应于读取信号以指示所读取的位置处存储的信号 ; 包括以下步骤：（a）没有特别的顺序; （1）选择测试阈值信号; 和（2）以非读取级别设置读取信号; （b）将测试阈值信号应用于编程轨迹; （c）在读取电平和非读取电平之间循环读取信号，同时当读取信号处于读取电平时，将测试阈值信号施加到编程轨迹，以在读取轨迹处呈现至少两个测试信号; 和（d）循环时，观察至少两个测试信号是否表现出大于预定量的差。

2. 发明授权

US06563284B2 Single wire digital width modulation for fan control with tachometer feedback 有权
公开(公告)号：US06563284B2
公开(公告)日：2003-05-13
申请号：US09989065
申请日：2001-11-21
申请人： Alexander Noam Teutsch , Zbigniew Jan Lata , David John Baldwin , Ross E. Teggatz
发明人： Alexander Noam Teutsch , Zbigniew Jan Lata , David John Baldwin , Ross E. Teggatz
IPC分类号： G05B1128
CPC分类号： G05B11/28 , H02P6/085
摘要： The present invention relates to a motor drive system which comprises a fan controller circuit operable to generate a PWM control signal for control of a motor speed. The fan controller circuit comprises a current detection circuit and a motor speed determination circuit. The system further comprises a fan driver circuit operable to drive a motor at a duty cycle based on the PWM control signal from the fan controller circuit. The fan driver circuit comprises a current sink circuit operable to draw current from the PWM control signal when the PWM control signal is high and when the motor reaches a predetermined position. In the addition, the current detection circuit is operable to detect the current draw on the PWM control signal and provide an indication signal to the fan speed determination circuit associated with such detection. Further, the motor speed determination circuit is operable to determine the speed of the motor based upon a timing associated with successive current draw detections. The present invention also relates to a method of determining a motor speed which comprises driving a motor at a duty cycle dictated by a PWM control signal and detecting a predetermined rotor position of the motor. The method further comprises generating a current pulse based on the rotor position, wherein the current pulse is convolved with the PWM control signal, detecting the current pulse, and determining the motor speed using successive detected current pulses.

3. 发明授权

US5892283A Connection of active circuitry via wire bonding procedure 失效
标题翻译：通过接线方法连接有源电路
公开(公告)号：US5892283A
公开(公告)日：1999-04-06
申请号：US991118
申请日：1997-12-16
申请人： David John Baldwin , Ross E. Teggatz
发明人： David John Baldwin , Ross E. Teggatz
IPC分类号： H01L21/66 , H01L21/60 , H01L23/485 , H01L23/58 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/05 , H01L22/32 , H01L2224/05554 , H01L2224/05599 , H01L2224/05624 , H01L2224/05647 , H01L2224/05666 , H01L2224/05684 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/05042 , H01L2924/12035 , H01L2924/14
摘要： A method of fabricating a bond and the bond. The process includes providing a lower level (M1,13, 15) of electrically conductive metal disposed on a substrate having a pair of spaced apart sections. An electrically insulating layer (11) is then disposed over the lower level and vias (23) are formed in the electrically insulating layer, individual ones of the vias extending to one of the spaced apart section of the lower level. An upper level of electrically conductive metal (M2, 17, 19) is disposed on the electrically insulating layer, the upper level having a pair of spaced apart sections, each coupled to one of the sections of the lower level through a via. One of the pair of spaced apart sections of the lower level is preferably essentially U-shaped (13) and the other section (15) of the lower level is essentially rectangular shaped and extends into the open end of the "U". One of the pair of spaced apart section of the upper level is essentially rectangular (17) with a rectangular aperture at its central region and the other section of the upper level (19) is essentially rectangular and disposed within the rectangular aperture. A bond (23) is formed completely enclosing the spaced apart sections of the upper level.
摘要翻译：一种制造键和键的方法。该方法包括提供设置在具有一对间隔开的部分的基底上的较低级别的导电金属（M1,13,15）。然后将电绝缘层（11）设置在下层上，并且通孔（23）形成在电绝缘层中，各个通孔延伸到下层的间隔开的部分之一。导电金属（M2,17,19）的上层设置在电绝缘层上，上层具有一对间隔开的部分，每个部分通过通孔连接到下层的一个部分。较低级别的一对间隔开的部分之一优选地基本上为U形（13），并且下层的另一部分（15）基本上为矩形并且延伸到“U”的开口端。上层的一对间隔开的部分基本上是矩形（17），在其中心区域具有矩形孔，而上层（19）的另一部分基本上是矩形的并且设置在矩形孔内。形成完全包围上层间隔开的部分的粘结（23）。

4. 发明授权

US07269528B2 Method evaluating threshold level of a data cell in a memory device 有权
标题翻译：方法评估存储器件中数据单元的阈值水平
公开(公告)号：US07269528B2
公开(公告)日：2007-09-11
申请号：US11139172
申请日：2005-05-28
申请人： David John Baldwin , Eric Blackall , Joseph Devore , Ross E. Teggatz
发明人： David John Baldwin , Eric Blackall , Joseph Devore , Ross E. Teggatz
IPC分类号： G06F15/00
CPC分类号： G11C16/34
摘要： A method evaluating threshold of a data cell in a memory device including a programming locus coupled with the data cell for receiving a programming signal setting a stored signal level in the data cell and responding to a read signal to indicate the stored signal at a read locus; includes the steps of: (a) in no particular order: (1) selecting a test threshold signal; and (2) setting a read signal at a non-read level; (b) applying the test threshold signal to the programming locus; (c) cycling the read signal between a read level and a non-read level while applying the test threshold signal to the programming locus to present at least two test signals at the read locus when the read signal is at the read level; and (d) while cycling, observing whether the at least two test signals manifest a difference greater than a predetermined amount.
摘要翻译：一种评估存储器件中的数据单元的阈值的方法，包括与所述数据单元耦合的编程轨迹，用于接收在所述数据单元中设置存储的信号电平的编程信号，并且响应于读取信号以指示所读取的位置处存储的信号 ; 包括以下步骤：（a）没有特定的顺序：（1）选择测试阈值信号; 和（2）以非读取级别设置读取信号; （b）将测试阈值信号应用于编程轨迹; （c）在读取电平和非读取电平之间循环读取信号，同时当读取信号处于读取电平时，将测试阈值信号施加到编程轨迹，以在读取轨迹处呈现至少两个测试信号; 和（d）循环时，观察至少两个测试信号是否表现出大于预定量的差。

5. 发明授权

US06674621B2 IC PMOS Schottky reverse bias protection structure 有权
标题翻译： IC PMOS肖特基反向偏置保护结构
公开(公告)号：US06674621B2
公开(公告)日：2004-01-06
申请号：US09989066
申请日：2001-11-21
申请人： Alexander Noam Teutsch , Zbigniew Jan Lata , David John Baldwin , Ross E. Teggatz
发明人： Alexander Noam Teutsch , Zbigniew Jan Lata , David John Baldwin , Ross E. Teggatz
IPC分类号： F21V704
CPC分类号： H01L27/0255 , H02H11/003
摘要： The present invention relates to a reverse bias protection structure which comprises a PMOS transistor structure having a drain portion, a gate portion, a source portion and a backgate portion, wherein the gate portion is coupled to a first voltage potential, the source portion is selectively coupleable to a power supply, and the drain portion is selectively coupleable to a circuit needing power to be supplied thereto from the power supply. The reverse bias protection structure further comprises a Schottky diode structure having an anode coupled to the source portion of the PMOS transistor structure, and a cathode coupled to the backgate portion of the PMOS structure. Under forward bias conditions, the PMOS transistor conducts and exhibits a small voltage drop thereacross. Under reverse bias conditions, the PMOS transistor is off and the Schottky structure is reverse biased, thus preventing current through the protection structure.
摘要翻译：本发明涉及一种反偏置保护结构，其包括具有漏极部分，栅极部分，源极部分和后栅极部分的PMOS晶体管结构，其中栅极部分耦合到第一电压电位，源极部分选择性地可与电源连接，并且漏极部分选择性地耦合到需要从电源供给的电力的电路。反向偏置保护结构还包括具有耦合到PMOS晶体管结构的源极部分的阳极的肖特基二极管结构以及耦合到PMOS结构的背栅极部分的阴极。在正向偏置条件下，PMOS晶体管导通并呈现出小的电压降。在反向偏置条件下，PMOS晶体管截止，肖特基结构反向偏置，从而防止电流通过保护结构。

6. 发明授权

US09530555B2 Wireless power transmittal 有权
标题翻译：无线功率传输
公开(公告)号：US09530555B2
公开(公告)日：2016-12-27
申请号：US13434807
申请日：2012-03-29
申请人： Ross E. Teggatz , Wayne T. Chen
发明人： Ross E. Teggatz , Wayne T. Chen
IPC分类号： H01F38/00 , H01F38/14 , H02J5/00
CPC分类号： H01F38/14 , H02J5/005 , H02J7/025 , H02J50/12 , H02J50/50 , H02J50/80 , H02J50/90
摘要： Wireless power transmittal apparatus and systems are disclosed in which transmitter and receiver inductors, or coils, are coupled in configurations for wirelessly transferring power and/or data among them. In preferred implementations, a plurality of non-coplanar primary side coils are provided in power transmittal apparatus for transmitting power, or power and data.
摘要翻译：公开了无线电力传输装置和系统，其中发射机和接收机电感器或线圈以用于在它们之间无线传输功率和/或数据的配置耦合。在优选实施方案中，在功率传输装置中提供多个非共面初级侧线圈，用于发射功率或功率和数据。

7. 发明授权

US09343988B2 Current mode regulator 有权
标题翻译：电流模式调节器
公开(公告)号：US09343988B2
公开(公告)日：2016-05-17
申请号：US13567039
申请日：2012-08-04
申请人： Ross E. Teggatz , David D. Briggs , Amer H. Atrash , Wayne T. Chen
发明人： Ross E. Teggatz , David D. Briggs , Amer H. Atrash , Wayne T. Chen
IPC分类号： H02M3/24 , H02M3/338 , H02M1/42 , H02M1/00
CPC分类号： H02M3/33507 , H02M1/08 , H02M1/14 , H02M1/42 , H02M1/4225 , H02M3/3387 , H02M2001/0006 , H02M2001/0009 , H02M2001/0032 , H05B33/0815 , H05B33/0851 , Y02B70/126 , Y02B70/16
摘要： Circuits, systems, and methods of current mode regulation include a primary side for receiving an input signal and a secondary for outputting an output signal. A regulator spans the primary and secondary sides in a configuration by which the input signal may be rectified and thereafter provided to the output node as an output signal. A current monitor is provided at the output node for comparing the output signal to a reference. A communication link is included for providing feedback to the primary side of the regulator for use in regulating the signal.
摘要翻译：电流模式调节的电路，系统和方法包括用于接收输入信号的初级侧和用于输出输出信号的次级。调节器跨越主要和次要侧面，通过该配置可以对输入信号进行整流，此后将其提供给输出节点作为输出信号。在输出节点处提供电流监视器，用于将输出信号与参考值进行比较。包括通信链路，用于向调节器的初级侧提供反馈信号以用于调节信号。

8. 发明申请

US20130062967A1 TUNABLE SYNCHRONOUS RECTIFIER 有权
标题翻译：同步同步整流器（TUNABLE SYNCHRONOUS RECTIFIER）
公开(公告)号：US20130062967A1
公开(公告)日：2013-03-14
申请号：US13616726
申请日：2012-09-14
申请人： Ross E. Teggatz , Amer H. Atrash , Jonathan R. Knight
发明人： Ross E. Teggatz , Amer H. Atrash , Jonathan R. Knight
IPC分类号： H01F38/14
CPC分类号： H02J50/12 , H01F38/14 , H02J5/005 , H02J50/80
摘要： A system for power transfer is provided. In one exemplary embodiment, the system includes an inductive power device, such as a device that transmits or receives power over an inductive coupling. For example, an adjustable impedance is coupled to the inductive power device, where the adjustable impedance is used for dynamically controlling the power gain in the inductive power device, such as by damping power generated by circuit impedances, such as inductances, capacitances or resistances, and combinations thereof.
摘要翻译：提供电力传输系统。在一个示例性实施例中，系统包括感应功率器件，例如通过感应耦合发送或接收功率的器件。例如，可调阻抗耦合到感应功率器件，其中可调阻抗用于动态地控制感应功率器件中的功率增益，例如通过阻抗由电路阻抗（例如电感，电容或电阻）产生的功率，及其组合。

9. 发明申请

US20120087187A1 Method for Programming a Floating Gate 有权
标题翻译：浮动门编程方法
公开(公告)号：US20120087187A1
公开(公告)日：2012-04-12
申请号：US13327364
申请日：2011-12-15
申请人： Ross E. Teggatz , Wayne T. Chen , Brett Smith , Eric Blackall
发明人： Ross E. Teggatz , Wayne T. Chen , Brett Smith , Eric Blackall
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C16/10 , G11C16/0408 , G11C16/3468 , G11C27/005
摘要： The invention provides methods for programming a floating gate. A floating gate tunneling device is used with an analog comparing device in a circuit having a floating reference node and an offset-mitigating feedback loop for iteratively programming a floating gate, or multiple floating gates.
摘要翻译：本发明提供了编程浮动栅极的方法。在具有浮置参考节点和偏移减轻反馈环路的电路中使用浮动栅极隧道装置与模拟比较装置，用于迭代地编程浮动栅极或多个浮动栅极。

10. 再颁专利

USRE42494E1 Preventing drain to body forward bias in a MOS transistor 有权
标题翻译：防止在MOS晶体管中排出体内正向偏置
公开(公告)号：USRE42494E1
公开(公告)日：2011-06-28
申请号：US11800071
申请日：2007-05-03
申请人： Ross E. Teggatz
发明人： Ross E. Teggatz
IPC分类号： H03K5/003
CPC分类号： H03K5/003
摘要： A voltage level shifting circuit (FIG. 4) has a plurality of PMOS transistors M1, M2, M3 connected in parallel for respectively driving a capacitive load CL with a selected different voltage level V1, V2 or V3. Transistors M1, M2, M3 are controlled so that one of them is placed in the ON condition, with the others in the OFF condition, to connect one of the voltages V1, V2 or V3 to charge the load CL. The largest voltage transistor M3 has its body connected to its source. The lower voltage transistors M1, M2 have their bodies respectively connected to switches S1, S2, which connect the bodies to the sources when the transistors are placed in the ON condition and connect the bodies to the highest voltage V3 when the transistors are placed in the OFF condition.
摘要翻译：电压电平移动电路（图4）具有并联连接的多个PMOS晶体管M1，M2，M3，分别驱动具有所选择的不同电压电平V1，V2或V3的电容性负载CL。控制晶体管M1，M2，M3，使其中的一个被置于ON状态，其他的处于OFF状态，以连接电压V1，V2或V3中的一个来对负载CL充电。最大的电压晶体管M3的主体连接到其源极。低电压晶体管M1，M2的主体分别连接到开关S1，S2，开关S1，S2将晶体管置于ON状态时将主体连接到源极，并将晶体管放置在 OFF状态。

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