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51. 发明申请

US20090134451A1 Semiconductor device and method of fabricating the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20090134451A1
公开(公告)日：2009-05-28
申请号：US12292543
申请日：2008-11-20
申请人： Seung-Jae Baik , Jin-Tae Noh , Hong-Suk Kim , In-Sun Yi , Si-Young Choi , Ki-Hyun Hwang
发明人： Seung-Jae Baik , Jin-Tae Noh , Hong-Suk Kim , In-Sun Yi , Si-Young Choi , Ki-Hyun Hwang
IPC分类号： H01L29/792
CPC分类号： H01L29/7881 , B82Y10/00 , G11C2216/06 , H01L27/115 , H01L27/11521 , H01L27/11565 , H01L27/11568 , H01L29/42332 , H01L29/42348 , H01L29/792
摘要： An example embodiment of a non-volatile memory device and an example embodiment of a method of fabricating the same are provided. The non-volatile memory devices includes a tunnel insulation layer on a semiconductor substrate, a charge storage layer on the tunnel insulation layer, a blocking insulation layer including at least one nano dot on the charge storage layer, and a control gate electrode on the blocking insulation layer.
摘要翻译：提供非易失性存储器件的示例性实施例及其制造方法的示例性实施例。非易失性存储器件包括在半导体衬底上的隧道绝缘层，隧道绝缘层上的电荷存储层，在电荷存储层上包括至少一个纳米点的阻挡绝缘层，以及阻挡层上的控制栅电极绝缘层。

52. 发明申请

US20090045448A1 Non-volatile memory device and methods of forming the same 有权
标题翻译：非易失性存储器件及其形成方法
公开(公告)号：US20090045448A1
公开(公告)日：2009-02-19
申请号：US12222568
申请日：2008-08-12
申请人： Seung-Jae Baik , Si-Young Choi , Ki-Hyun Hwang
发明人： Seung-Jae Baik , Si-Young Choi , Ki-Hyun Hwang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7923 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/42348 , H01L29/42352
摘要： Example embodiments provide a non-volatile memory device and methods of forming the same. The non-volatile memory device may define an active region in a semiconductor substrate, and may include a device isolation layer extending in a first direction, bit lines in the semiconductor substrate, the bit lines extending in a second direction which intersects the first direction; word lines extending in the first direction and covering the active region; and charge storage patterns between the word lines and active region, wherein the charge storage patterns may be in pairs on both edges of the bit lines, and a pair of charge storage patterns may be spaced apart from each other by the word lines.
摘要翻译：示例性实施例提供非易失性存储器件及其形成方法。非易失性存储器件可以在半导体衬底中限定有源区，并且可以包括沿第一方向延伸的器件隔离层，半导体衬底中的位线，沿与第一方向相交的第二方向延伸的位线; 字线在第一方向上延伸并覆盖有源区; 并且对字线和有源区域之间的存储模式进行充电，其中电荷存储模式可以在位线的两个边缘上成对配对，并且一对电荷存储模式可以通过字线彼此间隔开。

53. 发明申请

US20050127036A1 Method of cleaning a reaction chamber 审中-公开
标题翻译：清洁反应室的方法
公开(公告)号：US20050127036A1
公开(公告)日：2005-06-16
申请号：US10989754
申请日：2004-11-16
申请人： Young-Jin Kim , Jin-Kuk Kim , Won-Sik Shin , Byung-Ho Ahn , Jae-Chul Lee , Ki-Hyun Hwang
发明人： Young-Jin Kim , Jin-Kuk Kim , Won-Sik Shin , Byung-Ho Ahn , Jae-Chul Lee , Ki-Hyun Hwang
IPC分类号： H01L21/3065 , B08B7/00 , C23C14/56 , C23F1/00 , H01J37/32
CPC分类号： C23C14/564 , B08B7/00 , B08B7/0035 , H01J37/32412 , H01J37/32862
摘要： A method of cleaning a reaction chamber is provided. In the method, a wafer is removed from the reaction chamber, and a nitrogen triflouride (NF3) gas or NF3 plasma is implanted into the reaction chamber. The NF3 gas or NF3 plasma reacts with a phosphorous polymer located in the reaction chamber, and the phosphorus polymer is removed from the reaction chamber.
摘要翻译：提供一种清洁反应室的方法。在该方法中，将晶片从反应室中取出，并将氮三氟化氮（NF 3 3）气体或者NF 3等离子体注入到反应室中。 NF 3气体或NF 3 N 3等离子体与位于反应室中的磷聚合物反应，并将磷聚合物从反应室中除去。

54. 发明授权

US06730570B2 Method for forming a self-aligned contact of a semiconductor device and method for manufacturing a semiconductor device using the same 有权
标题翻译：用于形成半导体器件的自对准接触的方法和使用其制造半导体器件的方法
公开(公告)号：US06730570B2
公开(公告)日：2004-05-04
申请号：US10348017
申请日：2003-01-22
申请人： Seung-Mok Shin , Jae-Jong Han , Ki-Hyun Hwang
发明人： Seung-Mok Shin , Jae-Jong Han , Ki-Hyun Hwang
IPC分类号： H01L21336
CPC分类号： H01L21/76897 , H01L21/76831 , H01L29/6656
摘要： A method for forming a self-aligned contact in a semiconductor device which can reduce process failures and a method for manufacturing a semiconductor device that includes the self-aligned contact are provided. A self-aligned contact hole is formed in an interlayer dielectric film to expose a portion of the substrate between conductive structures formed thereon. A buffer layer is formed on a sidewall of the self-aligned contact hole, on the bottom of the self-aligned contact hole, and on the interlayer dielectric film such that the thickness of the buffer layer at an upper portion of the self-aligned contact hole is greater than the thickness of the buffer layer at the bottom of the self-aligned contact hole. After removing the portion of the buffer layer on the bottom of the self-aligned contact hole, a contact is formed in the self-aligned contact hole to make contact with the substrate.
摘要翻译：提供了一种用于在可以减少工艺故障的半导体器件中形成自对准接触的方法以及包括自对准接触的半导体器件的制造方法。在层间电介质膜中形成自对准接触孔，以在其上形成的导电结构之间露出基板的一部分。在自对准接触孔的侧壁，自对准接触孔的底部和层间电介质膜上形成缓冲层，使得缓冲层在自对准的上部的厚度接触孔大于自对准接触孔底部缓冲层的厚度。在自对准接触孔的底部上移除缓冲层的部分之后，在自对准接触孔中形成接触以与衬底接触。

55. 发明授权

US06700153B2 One-cylinder stack capacitor and method for fabricating the same 有权
公开(公告)号：US06700153B2
公开(公告)日：2004-03-02
申请号：US10136385
申请日：2002-05-02
申请人： Jung-Hwan Oh , Ki-Hyun Hwang , Jae-Young Park , In-Seak Hwang , Young-Wook Park
发明人： Jung-Hwan Oh , Ki-Hyun Hwang , Jae-Young Park , In-Seak Hwang , Young-Wook Park
IPC分类号： H01L27108
CPC分类号： H01L28/91 , H01L27/10855 , Y10T29/5111
摘要： An etch stop layer is formed over a surface of an interlayer insulating layer and over a surface of a conductive plug extending at a depth from the surface of the interlayer insulating layer. A lower mold layer is deposited over the etch stop layer, and a wet etch rate of the lower mold layer is adjusted by adding dopants to the lower mold layer during formation of the lower mold layer, and by annealing the lower mold layer. An upper mold layer is then deposited over the surface of the lower mold layer, such that a wet etch rate of the upper mold layer is less than the adjusted wet etch rate of the lower mold layer. The upper mold layer, the lower mold layer and the etch stop layer are then subjected to dry etching to form an opening therein which exposes at least a portion of the surface of the contact plug. Then a wet etching of the upper mold layer and the lower mold layer is performed so as to increase a size of the opening at the lower mold layer and so at to expose a surface portion of the etch stop layer adjacent the surface of the conductive plug. A conductive material is then deposited over the surface of the opening in the upper and lower mold layers to define a capacitor electrode.

56. 发明授权

US09111897B2 Methods of forming a polysilicon layer and methods of manufacturing semiconductor devices 有权
标题翻译：形成多晶硅层的方法和制造半导体器件的方法
公开(公告)号：US09111897B2
公开(公告)日：2015-08-18
申请号：US13716859
申请日：2012-12-17
申请人： Jung-Geun Jee , Jin-Gyun Kim , Ji-Hoon Choi , Ki-Hyun Hwang
发明人： Jung-Geun Jee , Jin-Gyun Kim , Ji-Hoon Choi , Ki-Hyun Hwang
IPC分类号： H01L21/336 , H01L21/36 , H01L29/66 , H01L21/02 , H01L27/108 , H01L27/115 , H01L21/285 , H01L21/768 , C23C16/24
CPC分类号： H01L21/36 , C23C16/24 , H01L21/02381 , H01L21/0245 , H01L21/02488 , H01L21/02494 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/02595 , H01L21/0262 , H01L21/02639 , H01L21/28525 , H01L21/28556 , H01L21/76876 , H01L21/76877 , H01L27/10888 , H01L27/11582 , H01L29/66666
摘要： A method of forming a polysilicon layer includes providing a silicon precursor onto an object loaded in a process chamber to form a seed layer. The silicon precursor includes a nitrogen containing silicon precursor and a chlorine containing silicon precursor. The method further includes providing a silicon source on the seed layer.
摘要翻译：形成多晶硅层的方法包括将硅前体提供到加载在处理室中的物体上以形成种子层。硅前体包括含氮的硅前体和含氯的硅前体。该方法还包括在种子层上提供硅源。

57. 发明授权

US08614476B2 Nonvolatile memory devices and fabricating methods thereof 有权
标题翻译：非易失存储器件及其制造方法
公开(公告)号：US08614476B2
公开(公告)日：2013-12-24
申请号：US13564992
申请日：2012-08-02
申请人： Hong-Suk Kim , Yong-Seok Kim , Hun-Hyeong Lim , Ki-Hyun Hwang
发明人： Hong-Suk Kim , Yong-Seok Kim , Hun-Hyeong Lim , Ki-Hyun Hwang
IPC分类号： H01L29/788
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/42336 , H01L29/66825 , H01L29/7881
摘要： Non-volatile memory devices, and fabricating methods thereof, include a floating gate over a substrate, a lower barrier layer including a first lower barrier layer on the upper surface of the floating gate, and a second lower barrier layer on a side surface of the floating gate to have a thickness smaller than a thickness of the first lower barrier layer, an inter-gate dielectric layer over the lower barrier layer, and a control gate over the inter-gate dielectric layer.
摘要翻译：非易失性存储器件及其制造方法包括在衬底上的浮置栅极，在浮置栅极的上表面上包括第一下阻挡层的下势垒层和位于浮置栅极的侧表面上的第二下势垒层浮栅的厚度小于第一下阻挡层的厚度，下阻挡层上的栅极间电介质层和栅极间电介质层上的控制栅极。

58. 发明申请

US20120187470A1 GATE STRUCTURES 有权
标题翻译：门结构
公开(公告)号：US20120187470A1
公开(公告)日：2012-07-26
申请号：US13340968
申请日：2011-12-30
申请人： Jung-Hwan KIM , Sung-Ho Heo , Jae-Ho Choi , Hun-Hyeong Lim , Ki-Hyun Hwang , Woo-Sung Lee
发明人： Jung-Hwan KIM , Sung-Ho Heo , Jae-Ho Choi , Hun-Hyeong Lim , Ki-Hyun Hwang , Woo-Sung Lee
IPC分类号： H01L29/788
CPC分类号： H01L21/28273 , H01L27/11531
摘要： A method of forming a gate structure includes forming a tunnel insulation layer pattern on a substrate, forming a floating gate on the tunnel insulation layer pattern, forming a dielectric layer pattern on the floating gate, the dielectric layer pattern including a first oxide layer pattern, a nitride layer pattern on the first oxide layer pattern, and a second oxide layer pattern on the nitride layer pattern, the second oxide layer pattern being formed by performing an anisotropic plasma oxidation process on the nitride layer, such that a first portion of the second oxide layer pattern on a top surface of the floating gate has a larger thickness than a second portion of the second oxide layer pattern on a sidewall of the floating gate, and forming a control gate on the second oxide layer.
摘要翻译：形成栅极结构的方法包括在衬底上形成隧道绝缘层图案，在隧道绝缘层图案上形成浮栅，在浮栅上形成电介质层图案，电介质层图案包括第一氧化层图案，所述第一氧化物层图案上的氮化物层图案和所述氮化物层图案上的第二氧化物层图案，所述第二氧化物层图案通过在所述氮化物层上进行各向异性等离子体氧化处理而形成，使得所述第二氧化物层图案的第二部分在浮置栅极的顶表面上的氧化物层图案具有比浮置栅极的侧壁上的第二氧化物层图案的第二部分更大的厚度，并且在第二氧化物层上形成控制栅极。

59. 发明申请

US20120115293A1 METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120115293A1
公开(公告)日：2012-05-10
申请号：US13287509
申请日：2011-11-02
申请人： Jin-Tae NOH , Hun-Hyeong Lim , Ki-Hyun Hwang , Jin-Gyun Kim , Sang-Ryol Yang
发明人： Jin-Tae NOH , Hun-Hyeong Lim , Ki-Hyun Hwang , Jin-Gyun Kim , Sang-Ryol Yang
IPC分类号： H01L21/336 , H01L21/8234 , B82Y40/00
CPC分类号： H01L27/1157 , H01L27/10855 , H01L27/11582
摘要： In a method of manufacturing a semiconductor device, a plurality of sacrificial layers and a plurality of insulating interlayers are repeatedly and alternately on a substrate. The insulating interlayers include a different material from a material of the sacrificial layers. At least one opening through the insulating interlayers and the sacrificial layers are formed. The at least one opening exposes the substrate. The seed layer is formed on an inner wall of the at least one opening using a first silicon source gas. A polysilicon channel is formed in the at least one opening by growing the seed layer. The sacrificial layers are removed to form a plurality of grooves between the insulating interlayers. A plurality of gate structures is formed in the grooves, respectively.
摘要翻译：在制造半导体器件的方法中，多个牺牲层和多个绝缘中间层在衬底上重复交替。绝缘夹层包括与牺牲层的材料不同的材料。通过绝缘夹层和牺牲层形成至少一个开口。至少一个开口露出基板。种子层使用第一硅源气体形成在至少一个开口的内壁上。通过种植种子层在至少一个开口中形成多晶硅沟道。去除牺牲层以在绝缘夹层之间形成多个凹槽。在槽中分别形成有多个栅极结构。

60. 发明授权

US08008154B2 Methods of forming impurity containing insulating films and flash memory devices including the same 失效
标题翻译：形成含杂质的绝缘膜的方法和包括其的闪存器件的方法
公开(公告)号：US08008154B2
公开(公告)日：2011-08-30
申请号：US12188482
申请日：2008-08-08
申请人： Young-Jin Noh , Bon-Young Koo , Si-Young Choi , Ki-Hyun Hwang , Chul-Sung Kim , Sung-Kweon Baek , Jin-Hwa Heo
发明人： Young-Jin Noh , Bon-Young Koo , Si-Young Choi , Ki-Hyun Hwang , Chul-Sung Kim , Sung-Kweon Baek , Jin-Hwa Heo
IPC分类号： H01L21/336
CPC分类号： H01L29/42324 , H01L21/0214 , H01L21/02238 , H01L21/02255 , H01L21/02332 , H01L21/02337 , H01L21/28273 , H01L21/3145 , H01L21/31662
摘要： Methods of forming an insulating film include forming an insulating film on a substrate. A first impurity is injected into the insulating film using a thermal process under a first set of processing conditions to form a first impurity concentration peak in a lower portion of the insulating film. A second impurity is injected into the insulating film using the thermal process under a second set of processing conditions, different from the first set of processing conditions, to form a second impurity concentration peak in an upper portion of the insulating film. Injecting the first impurity and injecting the second impurity may be carried out without using plasma and the first impurity concentration peak may be higher than the second impurity concentration peak.
摘要翻译：形成绝缘膜的方法包括在基板上形成绝缘膜。使用第一组处理条件下的热处理将第一杂质注入绝缘膜，以在绝缘膜的下部形成第一杂质浓度峰。在与第一组处理条件不同的第二组处理条件下，使用热处理将第二杂质注入到绝缘膜中，以在绝缘膜的上部形成第二杂质浓度峰。注入第一杂质并注入第二杂质可以在不使用等离子体的情况下进行，并且第一杂质浓度峰可以高于第二杂质浓度峰。

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