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51. 发明申请

US20110049574A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20110049574A1
公开(公告)日：2011-03-03
申请号：US12917994
申请日：2010-11-02
申请人： Hiroaki UENO , Manabu Yanagihara , Yasuhiro Uemoto , Tsuyoshi Tanaka
发明人： Hiroaki UENO , Manabu Yanagihara , Yasuhiro Uemoto , Tsuyoshi Tanaka
IPC分类号： H01L29/778
CPC分类号： H01L29/7786 , H01L29/1066 , H01L29/2003 , H01L29/452
摘要： A semiconductor device includes a first group III-V nitride semiconductor layer, a second group III-V nitride semiconductor layer having a larger band gap than the first group III-V nitride semiconductor layer and at least one ohmic electrode successively formed on a substrate. The ohmic electrode is formed so as to have a base portion penetrating the second group III-V nitride semiconductor layer and reaching a portion of the first group III-V nitride semiconductor layer disposed beneath a two-dimensional electron gas layer. An impurity doped layer is formed in portions of the first group III-V nitride semiconductor layer and the second group III-V nitride semiconductor layer in contact with the ohmic electrode.
摘要翻译：半导体器件包括第一III-V族氮化物半导体层，具有比第一III-V族氮化物半导体层更大的带隙的第二III-V族氮化物半导体层和在衬底上依次形成的至少一个欧姆电极。欧姆电极形成为具有穿透第二III-V族氮化物半导体层并且到达设置在二维电子气体层下方的第一III-V族氮化物半导体层的一部分的基极部分。在与欧姆电极接触的第一III-V族氮化物半导体层和第二III-V族氮化物半导体层的部分中形成杂质掺杂层。

52. 发明授权

US07332754B2 Semiconductor switch 有权
标题翻译：半导体开关
公开(公告)号：US07332754B2
公开(公告)日：2008-02-19
申请号：US11022814
申请日：2004-12-28
申请人： Takashi Uno , Manabu Yanagihara , Hidetoshi Ishida , Tsuyoshi Tanaka
发明人： Takashi Uno , Manabu Yanagihara , Hidetoshi Ishida , Tsuyoshi Tanaka
IPC分类号： H01L29/80
CPC分类号： H01L27/1203 , H01L29/8126
摘要： In the semiconductor switch of the present invention, the gate electrode, source electrode and drain electrode are formed such that the distance between the gate and the drain of an MESFET, assuming a shunt FET, is longer than the distance between the gate and the drain of an MESFET, assuming a through FET, so that the gate breakdown voltage of the MESFET, assuming a shunt FET, is increased without changing the gate breakdown voltage of the MESFET, assuming a through FET.
摘要翻译：在本发明的半导体开关中，栅电极，源电极和漏极形成为使得MESFET的栅极和漏极之间的距离（假设分流FET）比栅极和漏极之间的距离长假定通过FET，MESFET的假定为通过FET的MESFET的栅极击穿电压在不改变MESFET的栅极击穿电压的情况下增加，并且假定为通过FET，所以增加了MESFET的栅极击穿电压。

53. 发明申请

US20060273347A1 Field-effect transistor and method for fabricating the same 有权
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US20060273347A1
公开(公告)日：2006-12-07
申请号：US11433734
申请日：2006-05-15
申请人： Masahiro Hikita , Tetsuzo Ueda , Manabu Yanagihara , Yasuhiro Uemoto , Tsuyoshi Tanaka
发明人： Masahiro Hikita , Tetsuzo Ueda , Manabu Yanagihara , Yasuhiro Uemoto , Tsuyoshi Tanaka
IPC分类号： H01L31/00
CPC分类号： H01L29/7786 , H01L29/0843 , H01L29/1066 , H01L29/2003 , H01L29/432 , H01L29/66462 , H01L29/7783
摘要： An AlN buffer layer, an undoped GaN layer, an undoped AlGaN layer, a p-type GaN layer and a heavily doped p-type GaN layer are formed in this order. A gate electrode forms an Ohmic contact with the heavily doped p-type GaN layer. A source electrode and a drain electrode are provided on the undoped AlGaN layer. A pn junction is formed in a gate region by a two dimensional electron gas generated at an interface between the undoped AlGaN layer and the undoped GaN layer and the p-type GaN layer, so that a gate voltage can be increased.
摘要翻译：依次形成AlN缓冲层，未掺杂的GaN层，未掺杂的AlGaN层，p型GaN层和重掺杂的p型GaN层。栅电极与重掺杂的p型GaN层形成欧姆接触。源电极和漏电极设置在未掺杂的AlGaN层上。通过在未掺杂的AlGaN层和未掺杂的GaN层和p型GaN层之间的界面处产生的二维电子气在栅极区域中形成pn结，从而可以提高栅极电压。

54. 发明申请

US20060060895A1 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060060895A1
公开(公告)日：2006-03-23
申请号：US11193417
申请日：2005-08-01
申请人： Masahiro Hikita , Hiroaki Ueno , Yutaka Hirose , Manabu Yanagihara , Yasuhiro Uemoto , Tsuyoshi Tanaka
发明人： Masahiro Hikita , Hiroaki Ueno , Yutaka Hirose , Manabu Yanagihara , Yasuhiro Uemoto , Tsuyoshi Tanaka
IPC分类号： H01L31/112 , H01L29/20 , H01L29/80
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/402 , H01L29/4175
摘要： In the structure of a semiconductor device of the present invention, a first source electrode is connected to a conductive substrate through a via hole, and a second source electrode is formed. Thus, even if a high reverse voltage is applied between a gate electrode and a drain electrode, electric field concentration likely to occur at an edge of the gate electrode closer to the drain electrode can be effectively dispersed or relaxed. Moreover, the conductive substrate is used as a substrate for forming element formation layers, so that a via hole penetrating the substrate to reach the backside thereof does not have to be formed in the conductive substrate. Thus, with the strength necessary for the conductive substrate maintained, the first source electrode can be electrically connected to a backside electrode.
摘要翻译：在本发明的半导体器件的结构中，第一源极通过通孔与导电性基板连接，形成第二源电极。因此，即使在栅电极和漏极之间施加高的反向电压，也可以有效地分散或放松在栅电极的靠近漏电极的边缘处可能发生的电场集中。此外，导电性基板用作形成元件形成层的基板，从而不必在导电性基板上形成贯穿基板到达其背面的通路孔。因此，由于保持导电基板所需的强度，第一源电极可以电连接到背面电极。

55. 发明申请

US20050151208A1 Semiconductor switch 有权
标题翻译：半导体开关
公开(公告)号：US20050151208A1
公开(公告)日：2005-07-14
申请号：US11022814
申请日：2004-12-28
申请人： Takashi Uno , Manabu Yanagihara , Hidetoshi Ishida , Tsuyoshi Tanaka
发明人： Takashi Uno , Manabu Yanagihara , Hidetoshi Ishida , Tsuyoshi Tanaka
IPC分类号： H01L27/095 , H01L27/12 , H01L29/812 , H01L21/336 , H01L29/94
CPC分类号： H01L27/1203 , H01L29/8126
摘要： In the semiconductor switch of the present invention, the gate electrode, source electrode and drain electrode are formed such that the distance between the gate and the drain of an MESFET, assuming a shunt FET, is longer than the distance between the gate and the drain of an MESFET, assuming a through FET, so that the gate breakdown voltage of the MESFET, assuming a shunt FET, is increased without changing the gate breakdown voltage of the MESFET, assuming a through FET.
摘要翻译：在本发明的半导体开关中，栅电极，源电极和漏极形成为使得MESFET的栅极和漏极之间的距离（假设分流FET）比栅极和漏极之间的距离长假定通过FET，MESFET的假定为通过FET的MESFET的栅极击穿电压在不改变MESFET的栅极击穿电压的情况下增加，并且假定为通过FET，所以增加了MESFET的栅极击穿电压。

56. 发明授权

US06852580B2 Method of fabricating semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06852580B2
公开(公告)日：2005-02-08
申请号：US10150326
申请日：2002-05-20
申请人： Manabu Yanagihara , Tsuyoshi Tanaka , Akihisa Sugimura
发明人： Manabu Yanagihara , Tsuyoshi Tanaka , Akihisa Sugimura
IPC分类号： H01L21/328 , G05F3/20 , H03F1/30 , H01L21/338
CPC分类号： H03F1/302 , G05F3/205
摘要： The invention provides a bias circuit for suppressing change with temperature of an idle current of a power transistor and a semiconductor device including the bias circuit. The bias circuit includes a first bipolar transistor having an emitter, a base and a collector, and at least one Schottky diode connected to the base of the first bipolar transistor, and the at least one Schottky diode is provided for supplying a base potential for suppressing a collector current of the first bipolar transistor from changing in accordance with temperature change.
摘要翻译：本发明提供一种用于抑制功率晶体管的空载电流随温度变化的偏置电路和包括该偏置电路的半导体器件。偏置电路包括具有发射极，基极和集电极的第一双极晶体管和连接到第一双极晶体管的基极的至少一个肖特基二极管，并且提供至少一个肖特基二极管以提供用于抑制的基极电位第一双极晶体管的集电极电流根据温度变化而变化。

57. 发明授权

US08598628B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08598628B2
公开(公告)日：2013-12-03
申请号：US13231514
申请日：2011-09-13
申请人： Masahiro Hikita , Manabu Yanagihara
发明人： Masahiro Hikita , Manabu Yanagihara
IPC分类号： H01L29/72
CPC分类号： H01L29/42316 , H01L29/1066 , H01L29/2003 , H01L29/518 , H01L29/7786
摘要： A normally off semiconductor device with a reduced off-state leakage current, which is applicable to a power switching element, includes: a substrate; an undoped GaN layer formed above the substrate; an undoped AlGaN layer formed on the undoped GaN layer; a source electrode and a drain electrode, formed on the undoped GaN layer or the undoped AlGaN layer; a P-type GaN layer formed on the undoped AlGaN layer and disposed between the source electrode and the drain electrode; and a gate electrode formed on the P-type GaN layer, wherein the undoped GaN layer includes an active region including a channel and an inactive region not including the channel, and the P-type GaN layer is disposed to surround the source electrode.
摘要翻译：具有减小的截止状态漏电流的常闭半导体器件，其适用于功率开关元件，包括：衬底; 在衬底上形成未掺杂的GaN层; 在未掺杂的GaN层上形成未掺杂的AlGaN层; 源电极和漏电极，形成在未掺杂的GaN层或未掺杂的AlGaN层上; 形成在未掺杂的AlGaN层上并设置在源电极和漏电极之间的P型GaN层; 以及形成在所述P型GaN层上的栅电极，其中所述未掺杂的GaN层包括包括沟道的有源区和不包括所述沟道的非活性区，并且所述P型GaN层设置为围绕所述源电极。

58. 发明授权

US08497553B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08497553B2
公开(公告)日：2013-07-30
申请号：US12905801
申请日：2010-10-15
申请人： Hiroto Yamagiwa , Shingo Hashizume , Ayanori Ikoshi , Manabu Yanagihara , Yasuhiro Uemoto
发明人： Hiroto Yamagiwa , Shingo Hashizume , Ayanori Ikoshi , Manabu Yanagihara , Yasuhiro Uemoto
IPC分类号： H01L23/62 , H01L29/66 , H01L31/06 , H01L21/338 , H02H3/00 , H02H9/02
CPC分类号： H01L29/7786 , H01L27/0266 , H01L27/0605 , H01L29/1066 , H01L29/2003 , H01L29/41758 , H01L29/42364 , H01L29/8124 , H01L29/861
摘要： A semiconductor device includes a first transistor formed on a first element region, and a first protecting element including a second transistor formed on a second element region. A second protecting element ohmic electrode is connected to a first gate electrode, a first protecting element ohmic electrode is connected to a first ohmic electrode, and a first protecting element gate electrode is connected to at least one of the first protecting element ohmic electrode and the second protecting element ohmic electrode. The second element region is smaller in area than the first element region.
摘要翻译：半导体器件包括形成在第一元件区上的第一晶体管和包括形成在第二元件区上的第二晶体管的第一保护元件。第二保护元件欧姆电极连接到第一栅电极，第一保护元件欧姆电极连接到第一欧姆电极，第一保护元件栅电极连接至第一保护元件欧姆电极和第二保护元件欧姆电极。第二元件区域的面积小于第一元件区域。

59. 发明申请

US20110305054A1 BI-DIRECTIONAL SWITCH, ALTERNATING-CURRENT TWO-WIRE SWITCH, SWITCHING POWER SOURCE CIRCUIT, AND METHOD OF DRIVING BI-DIRECTIONAL SWITCH 有权
标题翻译：双向开关，交替电流二线开关，开关电源电路以及驱动双向开关的方法
公开(公告)号：US20110305054A1
公开(公告)日：2011-12-15
申请号：US13158934
申请日：2011-06-13
申请人： Hiroto YAMAGIWA , Shingo Hashizume , Manabu Yanagihara , Ayanori Ikoshi
发明人： Hiroto YAMAGIWA , Shingo Hashizume , Manabu Yanagihara , Ayanori Ikoshi
IPC分类号： H02M7/02 , H03K17/94 , H03K17/687
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/42316 , H03K17/6871 , H03K2017/6875 , H03K2217/0009
摘要： A semiconductor device 101 in a bi-directional switch includes: a first electrode 109A, a second electrode 109B, a first gate electrode 112A, and a second gate electrode 112B. In a transition period: when the potential of the first electrode 109A is higher than the potential of the second electrode 109B, a voltage lower than the first threshold voltage is applied to the first gate electrode 112A and a voltage higher than the second threshold value voltage is applied to the second gate electrode 112B; and otherwise, a voltage higher than the first threshold value voltage is applied to the first gate electrode, and a voltage lower than the second threshold value voltage is applied to the second gate electrode.
摘要翻译：双向开关中的半导体器件101包括：第一电极109A，第二电极109B，第一栅电极112A和第二栅电极112B。在过渡期间：当第一电极109A的电位高于第二电极109B的电位时，将低于第一阈值电压的电压施加到第一栅电极112A，并且施加高于第二阈值电压施加到第二栅电极112B; 否则，将高于第一阈值电压的电压施加到第一栅电极，并且将低于第二阈值电压的电压施加到第二栅电极。

60. 发明授权

US4965650A Bipolar transistor and method of producing the same 失效
标题翻译：双极晶体管及其制造方法
公开(公告)号：US4965650A
公开(公告)日：1990-10-23
申请号：US420656
申请日：1989-10-11
申请人： Masanori Inada , Kazuo Eda , Yorito Ota , Atsushi Nakagawa , Manabu Yanagihara
发明人： Masanori Inada , Kazuo Eda , Yorito Ota , Atsushi Nakagawa , Manabu Yanagihara
IPC分类号： H01L21/331 , H01L29/08 , H01L29/417 , H01L29/737
CPC分类号： H01L29/66318 , H01L29/0804 , H01L29/41708 , H01L29/7371 , Y10S148/01 , Y10S148/072
摘要： A dummy emitter (a dummy collector, in an inverted type) is formed in the portion corresponding to an emitter (a collector, in the inverted type) region, on a multiplayer structural material including layers for forming emitter, base and collector, and using it as mask, an external base region is exposed by etching, and a projection of the emitter (the collector, in the inverted type) region is formed, while the dummy emitter (the dummy collector, in the inverted type) is inverted into an emitter (a collector, in the inverted type) electrode, thereby forming an emitter (a collector, in the inverted type) electrode metal layer covering the whole upper surface of the emitter (the collector, in the inverted type). Using the thus formed emitter (the collector, in the inverted type) electrode metal layer, a base electrode metal layer is formed, by self-alignment, adjacent to the emitter (the collector, in the inverted type). In another method, on a multilayer structural material, impurities are introduced outside the portion corresponding to the base region of a bipolar transistor in order to insulate, at least, a portion of the layer forming the base, and if necessary a portion of the layer forming the emitter and a portion of the layer forming the collector. Further, an extension layers and the layer forming the collector, and an extension type dummy emitter (a dummy collector, in the inverted type) is formed which extends from the emitter (the collector, in the inverted type) on the base portion to the insulating region formed by transforming from the semiconductor material forming the base, and using it as mask, the external base region is exposed to form an emitter-including layer and the dummy emitter (the dummy collector, in the inverted type) is replaced by an emitter (a collector, in the inverted type) electrode metal layer covering the whole upper surface of the emitter-including layer.

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