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1. 发明申请

US20110049574A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20110049574A1
公开(公告)日：2011-03-03
申请号：US12917994
申请日：2010-11-02
申请人： Hiroaki UENO , Manabu Yanagihara , Yasuhiro Uemoto , Tsuyoshi Tanaka
发明人： Hiroaki UENO , Manabu Yanagihara , Yasuhiro Uemoto , Tsuyoshi Tanaka
IPC分类号： H01L29/778
CPC分类号： H01L29/7786 , H01L29/1066 , H01L29/2003 , H01L29/452
摘要： A semiconductor device includes a first group III-V nitride semiconductor layer, a second group III-V nitride semiconductor layer having a larger band gap than the first group III-V nitride semiconductor layer and at least one ohmic electrode successively formed on a substrate. The ohmic electrode is formed so as to have a base portion penetrating the second group III-V nitride semiconductor layer and reaching a portion of the first group III-V nitride semiconductor layer disposed beneath a two-dimensional electron gas layer. An impurity doped layer is formed in portions of the first group III-V nitride semiconductor layer and the second group III-V nitride semiconductor layer in contact with the ohmic electrode.
摘要翻译：半导体器件包括第一III-V族氮化物半导体层，具有比第一III-V族氮化物半导体层更大的带隙的第二III-V族氮化物半导体层和在衬底上依次形成的至少一个欧姆电极。欧姆电极形成为具有穿透第二III-V族氮化物半导体层并且到达设置在二维电子气体层下方的第一III-V族氮化物半导体层的一部分的基极部分。在与欧姆电极接触的第一III-V族氮化物半导体层和第二III-V族氮化物半导体层的部分中形成杂质掺杂层。

2. 发明授权

US07528423B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07528423B2
公开(公告)日：2009-05-05
申请号：US11681408
申请日：2007-03-02
申请人： Hiroaki Ueno , Tetsuzo Ueda , Yasuhiro Uemoto , Daisuke Ueda , Tsuyoshi Tanaka , Manabu Yanagihara , Yutaka Hirose , Masahiro Hikita
发明人： Hiroaki Ueno , Tetsuzo Ueda , Yasuhiro Uemoto , Daisuke Ueda , Tsuyoshi Tanaka , Manabu Yanagihara , Yutaka Hirose , Masahiro Hikita
IPC分类号： H01L31/072 , H01L31/109
CPC分类号： H01L29/7786 , H01L29/2003
摘要： It is an object of the present invention to provide a semiconductor device, which can simultaneously achieve a normally-off mode of HFET and an improvement in Imax, and further achieve an improvement in gm and a reduction in gate leakage current. In order to keep a thin barrier layer 13 on an operation layer 12 of a substrate 11 directly under a gate electrode for mostly contributing to achieve the normally-off mode and also implement the high Imax, it is configured in such a way that a thickness of the barrier layer 13 can be increased by the semiconductor layer 17 between gate and source regions and between gate and drain regions. It is therefore possible to achieve the normally-off mode and an improvement in Imax as compared with an FET in which a thickness of the barrier layer is designed so as to be uniform. An insulating film 18 with a dielectric constant higher than that of the barrier layer is further inserted between a gate electrode 16 and the barrier layers 13, so that an improvement in gm and a reduction in gate leakage current can be achieved.
摘要翻译：本发明的一个目的是提供一种可以同时实现HFET的常闭模式和改进Imax的半导体器件，并进一步实现gm的改善和栅极漏电流的减小。为了在栅电极正下方的基板11的操作层12上保持薄的阻挡层13，主要用于实现常关模式并且还实现了高的Imax，它被配置成使得厚度可以通过栅极和源极区域之间以及栅极和漏极区域之间的半导体层17来增加阻挡层13。因此，与设置阻挡层的厚度均匀的FET相比，可以实现常闭模式和Imax的改善。介电常数高于阻挡层的绝缘膜18进一步插入在栅电极16和阻挡层13之间，从而可以实现gm的改善和栅极漏电流的减小。

3. 发明申请

US20070210332A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20070210332A1
公开(公告)日：2007-09-13
申请号：US11681408
申请日：2007-03-02
申请人： Hiroaki UENO , Tetsuzo Ueda , Yasuhiro Uemoto , Daisuke Ueda , Tsuyoshi Tanaka , Manabu Yanagihara , Yutaka Hirose , Masahiro Hikita
发明人： Hiroaki UENO , Tetsuzo Ueda , Yasuhiro Uemoto , Daisuke Ueda , Tsuyoshi Tanaka , Manabu Yanagihara , Yutaka Hirose , Masahiro Hikita
IPC分类号： H01L31/00
CPC分类号： H01L29/7786 , H01L29/2003
摘要： It is an object of the present invention to provide a semiconductor device, which can simultaneously achieve a normally-off mode of HFET and an improvement in Imax, and further achieve an improvement in gm and a reduction in gate leakage current. In order to keep a thin barrier layer 13 on an operation layer 12 of a substrate 11 directly under a gate electrode for mostly contributing to achieve the normally-off mode and also implement the high Imax, it is configured in such a way that a thickness of the barrier layer 13 can be increased by the semiconductor layer 17 between gate and source regions and between gate and drain regions. It is therefore possible to achieve the normally-off mode and an improvement in Imax as compared with an FET in which a thickness of the barrier layer is designed so as to be uniform. An insulating film 18 with a dielectric constant higher than that of the barrier layer is further inserted between a gate electrode 16 and the barrier layers 13, so that an improvement in gm and a reduction in gate leakage current can be achieved.
摘要翻译：本发明的一个目的是提供一种半导体器件，其可以同时实现HFET的常闭模式和改进的最大值，并进一步实现gm的改善和栅极漏电流的减小。为了在栅电极正下方的基板11的操作层12上保持薄势垒层13，主要用于实现常关模式并且还实现高I max，配置成使得栅极和源极区域之间以及栅极和漏极区域之间的半导体层17可以增加阻挡层13的厚度。因此与阻挡层的厚度被设计为均匀的FET相比，可以实现常关模式和I 的改善。介电常数高于阻挡层的绝缘膜18进一步插入在栅电极16和阻挡层13之间，从而改善gm和栅极漏电流的减小可以实现。

4. 发明申请

US20060157729A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060157729A1
公开(公告)日：2006-07-20
申请号：US11325340
申请日：2006-01-05
申请人： Hiroaki Ueno , Tetsuzo Ueda , Yasuhiro Uemoto , Daisuke Ueda , Tsuyoshi Tanaka , Manabu Yanagihara , Yutaka Hirose , Masahiro Hikita
发明人： Hiroaki Ueno , Tetsuzo Ueda , Yasuhiro Uemoto , Daisuke Ueda , Tsuyoshi Tanaka , Manabu Yanagihara , Yutaka Hirose , Masahiro Hikita
IPC分类号： H01L33/00
CPC分类号： H01L29/7786 , H01L29/2003
摘要： It is an object of the present invention to provide a semiconductor device, which can simultaneously achieve a normally-off mode of HFET and an improvement in Imax, and further achieve an improvement in gm and a reduction in gate leakage current. In order to keep a thin barrier layer 13 on an operation layer 12 of a substrate 11 directly under a gate electrode for mostly contributing to achieve the normally-off mode and also implement the high Imax, it is configured in such a way that a thickness of the barrier layer 13 can be increased by the semiconductor layer 17 between gate and source regions and between gate and drain regions. It is therefore possible to achieve the normally-off mode and an improvement in Imax as compared with an FET in which a thickness of the barrier layer is designed so as to be uniform. An insulating film 18 with a dielectric constant higher than that of the barrier layer is further inserted between a gate electrode 16 and the barrier layers 13, so that an improvement in gm and a reduction in gate leakage current can be achieved.
摘要翻译：本发明的一个目的是提供一种半导体器件，其可以同时实现HFET的常闭模式和改进的最大值，并进一步实现gm的改善和栅极漏电流的减小。为了在栅电极正下方的基板11的操作层12上保持薄势垒层13，主要用于实现常关模式并且还实现高I max，配置成使得栅极和源极区域之间以及栅极和漏极区域之间的半导体层17可以增加阻挡层13的厚度。因此与阻挡层的厚度被设计为均匀的FET相比，可以实现常关模式和I 的改善。介电常数高于阻挡层的绝缘膜18进一步插入在栅电极16和阻挡层13之间，从而改善gm和栅泄漏电流的降低可以实现。

5. 发明申请

US20060060895A1 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060060895A1
公开(公告)日：2006-03-23
申请号：US11193417
申请日：2005-08-01
申请人： Masahiro Hikita , Hiroaki Ueno , Yutaka Hirose , Manabu Yanagihara , Yasuhiro Uemoto , Tsuyoshi Tanaka
发明人： Masahiro Hikita , Hiroaki Ueno , Yutaka Hirose , Manabu Yanagihara , Yasuhiro Uemoto , Tsuyoshi Tanaka
IPC分类号： H01L31/112 , H01L29/20 , H01L29/80
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/402 , H01L29/4175
摘要： In the structure of a semiconductor device of the present invention, a first source electrode is connected to a conductive substrate through a via hole, and a second source electrode is formed. Thus, even if a high reverse voltage is applied between a gate electrode and a drain electrode, electric field concentration likely to occur at an edge of the gate electrode closer to the drain electrode can be effectively dispersed or relaxed. Moreover, the conductive substrate is used as a substrate for forming element formation layers, so that a via hole penetrating the substrate to reach the backside thereof does not have to be formed in the conductive substrate. Thus, with the strength necessary for the conductive substrate maintained, the first source electrode can be electrically connected to a backside electrode.
摘要翻译：在本发明的半导体器件的结构中，第一源极通过通孔与导电性基板连接，形成第二源电极。因此，即使在栅电极和漏极之间施加高的反向电压，也可以有效地分散或放松在栅电极的靠近漏电极的边缘处可能发生的电场集中。此外，导电性基板用作形成元件形成层的基板，从而不必在导电性基板上形成贯穿基板到达其背面的通路孔。因此，由于保持导电基板所需的强度，第一源电极可以电连接到背面电极。

6. 发明授权

US07605441B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07605441B2
公开(公告)日：2009-10-20
申请号：US11730422
申请日：2007-04-02
申请人： Kazushi Nakazawa , Hiroaki Ueno , Manabu Yanagihara , Yasuhiro Uemoto , Tsuyoshi Tanaka
发明人： Kazushi Nakazawa , Hiroaki Ueno , Manabu Yanagihara , Yasuhiro Uemoto , Tsuyoshi Tanaka
IPC分类号： H01L27/095 , H01L21/28 , H01L29/47
CPC分类号： H01L29/872 , H01L29/2003 , H01L29/66212
摘要： A semiconductor device includes: a semiconductor layer made of a group-III nitride semiconductor and having a first surface and a second surface opposed to the first surface; a Schottky electrode formed on the first surface of the semiconductor layer; and an ohmic electrode electrically connected to the second surface of the semiconductor layer. The semiconductor layer has, in at least the upper portion thereof, highly-resistive regions selectively formed to have a high resistance.
摘要翻译：半导体器件包括：由III族氮化物半导体制成并具有与第一表面相对的第一表面和第二表面的半导体层; 形成在半导体层的第一表面上的肖特基电极; 以及与半导体层的第二表面电连接的欧姆电极。半导体层至少在其上部具有选择性地形成为具有高电阻的高电阻区域。

7. 发明申请

US20090121775A1 TRANSISTOR AND METHOD FOR OPERATING THE SAME 有权
标题翻译：晶体管及其操作方法
公开(公告)号：US20090121775A1
公开(公告)日：2009-05-14
申请号：US11995040
申请日：2006-06-27
申请人： Daisuke Ueda , Tsuyoshi Tanaka , Yasuhiro Uemoto , Tetsuzo Ueda , Manabu Yanagihara , Masahiro Hikita , Hiroaki Ueno
发明人： Daisuke Ueda , Tsuyoshi Tanaka , Yasuhiro Uemoto , Tetsuzo Ueda , Manabu Yanagihara , Masahiro Hikita , Hiroaki Ueno
IPC分类号： H01L29/207 , H03K17/687
CPC分类号： H01L29/739 , H01L29/1066 , H01L29/2003 , H01L29/4175 , H01L29/7786
摘要： In a transistor, an AlN buffer layer 102, an undoped GaN layer 103, an undoped AlGaN layer 104, a p-type control layer 105, and a p-type contact layer 106 are formed in this order on a sapphire substrate 101. The transistor further includes a gate electrode 110 in ohmic contact with the p-type contact layer 106, and a source electrode 108 and a drain electrode 109 provided on the undoped AlGaN layer 104. By applying a positive voltage to the p-type control layer 105, holes are injected into a channel to increase a current flowing in the channel.
摘要翻译：在晶体管中，在蓝宝石衬底101上依次形成AlN缓冲层102，未掺杂的GaN层103，未掺杂的AlGaN层104，p型控制层105和p型接触层106。晶体管还包括与p型接触层106欧姆接触的栅电极110以及设置在未掺杂的AlGaN层104上的源电极108和漏极109.通过向p型控制层105施加正电压，孔被注入到通道中以增加在通道中流动的电流。

8. 发明申请

US20070126115A1 Package substrate 审中-公开
标题翻译：封装衬底
公开(公告)号：US20070126115A1
公开(公告)日：2007-06-07
申请号：US11593617
申请日：2006-11-07
申请人： Manabu Yanagihara , Hiroaki Ueno , Yasuhiro Uemoto , Tsuyoshi Tanaka
发明人： Manabu Yanagihara , Hiroaki Ueno , Yasuhiro Uemoto , Tsuyoshi Tanaka
IPC分类号： H01L23/34
CPC分类号： H05K3/28 , H01L21/563 , H01L23/3732 , H01L24/45 , H01L24/48 , H01L2224/13144 , H01L2224/16 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/83951 , H01L2224/8592 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01079 , H01L2924/1306 , H01L2924/13091 , H01L2924/15153 , H01L2924/1517 , H05K1/0209 , H05K2201/0179 , H05K2201/0323 , H05K2201/09045 , H01L2924/00 , H01L2224/85399 , H01L2224/05599
摘要： A package substrate has a substrate body on which an electronic component is mounted. The substrate body is formed at its top or back surface with a diamond film, a diamond-like carbon film or a carbon film.
摘要翻译：封装基板具有安装电子部件的基板主体。基板主体在其顶部或背面形成有金刚石膜，类金刚石碳膜或碳膜。

9. 发明授权

US07217960B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07217960B2
公开(公告)日：2007-05-15
申请号：US11325340
申请日：2006-01-05
申请人： Hiroaki Ueno , Tetsuzo Ueda , Yasuhiro Uemoto , Daisuke Ueda , Tsuyoshi Tanaka , Manabu Yanagihara , Yutaka Hirose , Masahiro Hikita
发明人： Hiroaki Ueno , Tetsuzo Ueda , Yasuhiro Uemoto , Daisuke Ueda , Tsuyoshi Tanaka , Manabu Yanagihara , Yutaka Hirose , Masahiro Hikita
IPC分类号： H01L33/00
CPC分类号： H01L29/7786 , H01L29/2003
摘要： It is an object of the present invention to provide a semiconductor device, which can simultaneously achieve a normally-off mode of HFET and an improvement in Imax, and further achieve an improvement in gm and a reduction in gate leakage current. In order to keep a thin barrier layer 13 on an operation layer 12 of a substrate 11 directly under a gate electrode for mostly contributing to achieve the normally-off mode and also implement the high Imax, it is configured in such a way that a thickness of the barrier layer 13 can be increased by the semiconductor layer 17 between gate and source regions and between gate and drain regions. It is therefore possible to achieve the normally-off mode and an improvement in Imax as compared with an FET in which a thickness of the barrier layer is designed so as to be uniform. An insulating film 18 with a dielectric constant higher than that of the barrier layer is further inserted between a gate electrode 16 and the barrier layers 13, so that an improvement in gm and a reduction in gate leakage current can be achieved.
摘要翻译：本发明的一个目的是提供一种半导体器件，其可以同时实现HFET的常闭模式和改进的最大值，并进一步实现gm的改善和栅极漏电流的减小。为了在栅电极正下方的基板11的操作层12上保持薄势垒层13，主要用于实现常关模式并且还实现高I max，配置成使得栅极和源极区域之间以及栅极和漏极区域之间的半导体层17可以增加阻挡层13的厚度。因此与阻挡层的厚度被设计为均匀的FET相比，可以实现常关模式和I 的改善。介电常数高于阻挡层的绝缘膜18进一步插入在栅电极16和阻挡层13之间，从而改善gm和栅极漏电流的减小可以实现。

10. 发明授权

US08203376B2 Semiconductor device and method for driving the same 有权
标题翻译：半导体装置及其驱动方法
公开(公告)号：US08203376B2
公开(公告)日：2012-06-19
申请号：US12445390
申请日：2007-11-20
申请人： Tatsuo Morita , Manabu Yanagihara , Hidetoshi Ishida , Yasuhiro Uemoto , Hiroaki Ueno , Tsuyoshi Tanaka , Daisuke Ueda
发明人： Tatsuo Morita , Manabu Yanagihara , Hidetoshi Ishida , Yasuhiro Uemoto , Hiroaki Ueno , Tsuyoshi Tanaka , Daisuke Ueda
IPC分类号： H03K17/687
CPC分类号： H01L29/7787 , H01L27/0605 , H01L29/0619 , H01L29/1066 , H01L29/2003 , H01L29/432 , H01L29/739 , H01L29/8124
摘要： A semiconductor device includes a semiconductor layer stack 13 formed on a substrate 11 and having a channel region, a first electrode 16A and a second electrode 16B formed spaced apart from each other on the semiconductor layer stack 13, a first gate electrode 18A formed between the first electrode 16A and the second electrode 16B, and a second gate electrode 18B formed between the first gate electrode 18A and the second electrode 16B. A first control layer 19A having a p-type conductivity is formed between the semiconductor layer stack 13 and the first gate electrode 18A.
摘要翻译：半导体器件包括形成在衬底11上并具有沟道区的半导体层堆叠13，在半导体层叠层13上彼此隔开形成的第一电极16A和第二电极16B，形成在第一栅电极18A之间的第一栅电极18A 第一电极16A和第二电极16B，以及形成在第一栅电极18A和第二电极16B之间的第二栅电极18B。在半导体层堆叠13和第一栅电极18A之间形成具有p型导电性的第一控制层19A。

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