专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US08741730B2 Bi-directional self-aligned FET capacitor 有权
标题翻译：双向自对准FET电容
公开(公告)号：US08741730B2
公开(公告)日：2014-06-03
申请号：US13565294
申请日：2012-08-02
申请人： Leland Chang , Brian L. Ji , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Leland Chang , Brian L. Ji , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L29/94 , H01L21/8242
CPC分类号： H01L27/0811 , H01L21/26586 , H01L21/823418 , H01L21/84 , H01L27/1203 , H01L29/66181 , H01L29/94
摘要： A method of forming a field effect transistor (FET) capacitor includes forming a channel region; forming a gate stack over the channel region; forming a first extension region on a first side of the gate stack, the first extension region being formed by implanting a first doping material at a first angle such that a shadow region exists on a second side of the gate stack; and forming a second extension region on the second side of the gate stack, the second extension region being formed by implanting a second doping material at a second angle such that a shadow region exists on the first side of the gate stack.
摘要翻译：形成场效应晶体管（FET）电容器的方法包括：形成沟道区; 在沟道区上形成栅叠层; 在所述栅极堆叠的第一侧上形成第一延伸区域，所述第一延伸区域通过以第一角度注入第一掺杂材料形成，使得阴极区域存在于所述栅极叠层的第二侧上; 以及在所述栅极堆叠的第二侧上形成第二延伸区域，所述第二延伸区域通过以第二角度注入第二掺杂材料形成，使得阴极区域存在于所述栅极叠层的第一侧上。

52. 发明授权

US08395438B2 Switched capacitor voltage converters 有权
标题翻译：开关电容电压转换器
公开(公告)号：US08395438B2
公开(公告)日：2013-03-12
申请号：US13532986
申请日：2012-06-26
申请人： Robert H. Dennard , Brian L. Ji , Robert K. Montoye
发明人： Robert H. Dennard , Brian L. Ji , Robert K. Montoye
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G11C5/145 , H02M3/07
摘要： An on-chip voltage conversion apparatus for integrated circuits includes a first capacitor; a first NFET device configured to selectively couple a first electrode of the first capacitor to a low side voltage rail of a first voltage domain; a first PFET device configured to selectively couple the first electrode of the first capacitor to a high side voltage rail of the first voltage domain; a second NFET device configured to selectively couple a second electrode of the first capacitor to a low side voltage rail of a second voltage domain, wherein the low side voltage rail of the second voltage domain corresponds to the high side voltage rail of the first voltage domain; and a second PFET device configured to selectively couple the second electrode of the first capacitor to a high side voltage rail of the second voltage domain.
摘要翻译：集成电路的片上电压转换装置包括第一电容器; 第一NFET器件被配置为选择性地将第一电容器的第一电极耦合到第一电压域的低侧电压轨; 第一PFET器件，被配置为选择性地将第一电容器的第一电极耦合到第一电压域的高侧电压轨; 第二NFET器件，被配置为选择性地将第一电容器的第二电极耦合到第二电压域的低侧电压轨，其中第二电压域的低侧电压轨对应于第一电压域的高侧电压轨 ; 以及第二PFET器件，被配置为选择性地将第一电容器的第二电极耦合到第二电压域的高侧电压轨。

53. 发明申请

US20120292678A1 BI-DIRECTIONAL SELF-ALIGNED FET CAPACITOR 有权
标题翻译：双向自对准FET电容器
公开(公告)号：US20120292678A1
公开(公告)日：2012-11-22
申请号：US13565294
申请日：2012-08-02
申请人： Leland Chang , Chung-Hsun Lin , Brian L. Ji , Jeffrey W. Sleight
发明人： Leland Chang , Chung-Hsun Lin , Brian L. Ji , Jeffrey W. Sleight
IPC分类号： H01L29/94 , H01L21/02
CPC分类号： H01L27/0811 , H01L21/26586 , H01L21/823418 , H01L21/84 , H01L27/1203 , H01L29/66181 , H01L29/94
摘要： A method of forming a field effect transistor (FET) capacitor includes forming a channel region; forming a gate stack over the channel region; forming a first extension region on a first side of the gate stack, the first extension region being formed by implanting a first doping material at a first angle such that a shadow region exists on a second side of the gate stack; and forming a second extension region on the second side of the gate stack, the second extension region being formed by implanting a second doping material at a second angle such that a shadow region exists on the first side of the gate stack.
摘要翻译：形成场效应晶体管（FET）电容器的方法包括：形成沟道区; 在沟道区上形成栅叠层; 在所述栅极堆叠的第一侧上形成第一延伸区域，所述第一延伸区域通过以第一角度注入第一掺杂材料形成，使得阴极区域存在于所述栅极叠层的第二侧上; 以及在所述栅极堆叠的第二侧上形成第二延伸区域，所述第二延伸区域通过以第二角度注入第二掺杂材料形成，使得阴极区域存在于所述栅极叠层的第一侧上。

54. 发明授权

US08309445B2 Bi-directional self-aligned FET capacitor 有权
标题翻译：双向自对准FET电容
公开(公告)号：US08309445B2
公开(公告)日：2012-11-13
申请号：US12616861
申请日：2009-11-12
申请人： Leland Chang , Brian L. Ji , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Leland Chang , Brian L. Ji , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L21/336 , H01L21/425 , H01L29/94
CPC分类号： H01L27/0811 , H01L21/26586 , H01L21/823418 , H01L21/84 , H01L27/1203 , H01L29/66181 , H01L29/94
摘要： A method of forming a field effect transistor (FET) capacitor includes forming a channel region; forming a gate stack over the channel region; forming a first extension region on a first side of the gate stack, the first extension region being formed by implanting a first doping material at a first angle such that a shadow region exists on a second side of the gate stack; and forming a second extension region on the second side of the gate stack, the second extension region being formed by implanting a second doping material at a second angle such that a shadow region exists on the first side of the gate stack.
摘要翻译：形成场效应晶体管（FET）电容器的方法包括：形成沟道区; 在沟道区上形成栅叠层; 在所述栅极堆叠的第一侧上形成第一延伸区域，所述第一延伸区域通过以第一角度注入第一掺杂材料形成，使得阴极区域存在于所述栅极叠层的第二侧上; 以及在所述栅极堆叠的第二侧上形成第二延伸区域，所述第二延伸区域通过以第二角度注入第二掺杂材料形成，使得阴极区域存在于所述栅极叠层的第一侧上。

55. 发明申请

US20110051485A1 CONTENT ADDRESSABLE MEMORY ARRAY WRITING 审中-公开
标题翻译：内容可寻址存储阵列写
公开(公告)号：US20110051485A1
公开(公告)日：2011-03-03
申请号：US12549761
申请日：2009-08-28
申请人： Leland Chang , Gary S. Ditlow , Brian L. Ji , Robert K. Montoye
发明人： Leland Chang , Gary S. Ditlow , Brian L. Ji , Robert K. Montoye
IPC分类号： G11C15/00 , G11C7/00 , G11C11/00
CPC分类号： G11C15/00 , G11C13/0004 , G11C15/02 , G11C15/046
摘要： A memory system for storing one or more addresses includes a transposable memory having word lines, bit lines, transposed word lines and transposed bit lines and that receives and stores an input array having dimensions M by N and a content addressable memory (CAM) that reads the transposed word lines of the transposable memory to form input words and that stores the input words in an N by M array.
摘要翻译：用于存储一个或多个地址的存储器系统包括具有字线，位线，转置字线和转置位线的可转位存储器，并且接收并存储尺寸为M×N的输入阵列和读取的内容可寻址存储器（CAM）转置存储器的转置字线，以形成输入字，并将输入字存储在N乘M阵列中。

56. 发明申请

US20110051483A1 CONTENT ADDRESSABLE MEMORY ARRAY 有权
标题翻译：内容可寻址存储阵列
公开(公告)号：US20110051483A1
公开(公告)日：2011-03-03
申请号：US12549752
申请日：2009-08-28
申请人： Leland Chang , Gary S. Ditlow , Brian L. Ji , Robert K. Montoye
发明人： Leland Chang , Gary S. Ditlow , Brian L. Ji , Robert K. Montoye
IPC分类号： G11C15/00 , G11C11/00 , G11C8/00 , G11C7/00 , G11C11/56
CPC分类号： G11C15/046 , G11C7/1006 , G11C11/5678 , G11C13/0004
摘要： A memory device for storing one or more addresses includes a match line and first and second memory cells that form a 2-bit memory cell. Each memory cell includes two memory elements coupled to a match line and selection lines coupled thereto. The selection lines provide a signal representative of a logical combination of at least two different inputs.
摘要翻译：用于存储一个或多个地址的存储器件包括匹配线和形成2位存储器单元的第一和第二存储器单元。每个存储器单元包括耦合到匹配线的两个存储器元件和与其耦合的选择线。选择线提供表示至少两个不同输入的逻辑组合的信号。

57. 发明申请

US20100226161A1 TERNARY CONTENT ADDRESSABLE MEMORY USING PHASE CHANGE DEVICES 有权
标题翻译：使用相位变更设备的内容可寻址存储器
公开(公告)号：US20100226161A1
公开(公告)日：2010-09-09
申请号：US12399346
申请日：2009-03-06
申请人： Brian L. Ji , Chung H. Lam , Robert K. Montoye , Bipin Rajendran
发明人： Brian L. Ji , Chung H. Lam , Robert K. Montoye , Bipin Rajendran
IPC分类号： G11C15/00 , G11C11/00 , G11C11/56
CPC分类号： G11C15/046 , G11C13/0004
摘要： A content addressable memory device with a plurality of memory cells storing ternary data values of high, low, and don't care. An aspect of the content addressable memory device is the use of first memory elements and second memory elements in the memory cells. The first and second memory elements are electrically coupled in parallel circuit to a match-line. The first memory elements are coupled to first word-lines and the second memory elements are coupled to second word-lines. The first memory elements are configured to store low resistance states if the ternary data value is low and high resistance states if the ternary data value is either high or don't care. The second memory elements are configured to store the low resistance states if the ternary data value is high and the high resistance states if the ternary data value is either low or don't care.
摘要翻译：一种具有多个存储单元的内容可寻址存储器件，其存储高，低和不关心的三进制数据值。内容可寻址存储器件的一个方面是在存储器单元中使用第一存储器元件和第二存储器元件。第一和第二存储器元件以并联电路电耦合到匹配线。第一存储器元件耦合到第一字线，并且第二存储器元件耦合到第二字线。如果三进制数据值低，则第一存储器元件被配置为存储低电阻状态，并且如果三进制数据值高或不在乎，则高电阻状态。如果三进制数据值高，则第二存储器元件被配置为存储低电阻状态，并且如果三进制数据值为低或不关心，则存在高电阻状态。

58. 发明申请

US20100214014A1 SWITCHED CAPACITOR VOLTAGE CONVERTERS 有权
标题翻译：开关电容电压转换器
公开(公告)号：US20100214014A1
公开(公告)日：2010-08-26
申请号：US12392476
申请日：2009-02-25
申请人： Robert H. Dennard , Brian L. Ji , Robert K. Montoye
发明人： Robert H. Dennard , Brian L. Ji , Robert K. Montoye
IPC分类号： G05F3/02
CPC分类号： G11C5/145 , H02M3/07
摘要： An on-chip voltage conversion apparatus for integrated circuits includes a first capacitor; a first NFET device configured to selectively couple a first electrode of the first capacitor to a low side voltage rail of a first voltage domain; a first PFET device configured to selectively couple the first electrode of the first capacitor to a high side voltage rail of the first voltage domain; a second NFET device configured to selectively couple a second electrode of the first capacitor to a low side voltage rail of a second voltage domain, wherein the low side voltage rail of the second voltage domain corresponds to the high side voltage rail of the first voltage domain; and a second PFET device configured to selectively couple the second electrode of the first capacitor to a high side voltage rail of the second voltage domain.
摘要翻译：集成电路的片上电压转换装置包括第一电容器; 第一NFET器件被配置为选择性地将第一电容器的第一电极耦合到第一电压域的低侧电压轨; 第一PFET器件，被配置为选择性地将第一电容器的第一电极耦合到第一电压域的高侧电压轨; 第二NFET器件，被配置为选择性地将第一电容器的第二电极耦合到第二电压域的低侧电压轨，其中第二电压域的低侧电压轨对应于第一电压域的高侧电压轨 ; 以及第二PFET器件，被配置为选择性地将第一电容器的第二电极耦合到第二电压域的高侧电压轨。

59. 发明授权

US07675342B2 On-chip electrically alterable resistor 有权
标题翻译：片上电可变电阻
公开(公告)号：US07675342B2
公开(公告)日：2010-03-09
申请号：US12060889
申请日：2008-04-02
申请人： Louis C. Hsu , Brian L. Ji , Chung H. Lam
发明人： Louis C. Hsu , Brian L. Ji , Chung H. Lam
IPC分类号： H03L5/00
CPC分类号： H03H11/24
摘要： A programmable, electrically alterable (EA) resistor, an integrated circuit (IC) chip including the EA resistor and integrated analog circuits using on-chip EA resistors. Phase change storage media form resistors (EA resistors) on an IC that may be formed in an array of parallel EA resistors to set variable circuit bias conditions for circuits on the IC and in particular, bias on-chip analog circuits. The bias resistance is changed by changing EA resistor phase. Parallel connection of the parallel EA resistors may be dynamically alterable, switching one or more parallel resistors in and out digitally.
摘要翻译：一个可编程的，电气可变的（EA）电阻器，集成电路（IC）芯片，其中包括EA电阻器和使用片上EA电阻器的集成模拟电路。相变存储介质在IC上形成电阻器（EA电阻器），其可以形成在并联EA电阻器阵列中，以设置IC上的电路的可变电路偏置条件，特别是片上模拟电路偏置。通过改变EA电阻相位来改变偏置电阻。并联EA电阻器的并联连接可以是动态可变的，以数字方式切换一个或多个并联电阻器。

60. 发明申请

US20080298520A1 High-speed multi-mode receiver 失效
标题翻译：高速多模接收机
公开(公告)号：US20080298520A1
公开(公告)日：2008-12-04
申请号：US12218272
申请日：2008-07-14
申请人： Louis C. Hsu , Brian L. Ji , James S. Mason , Karl D. Selander , Michael A. Soma , Steven J. Zier
发明人： Louis C. Hsu , Brian L. Ji , James S. Mason , Karl D. Selander , Michael A. Soma , Steven J. Zier
IPC分类号： H04L27/08
CPC分类号： H04L25/085 , H03F1/3241 , H04L25/0278 , H04L25/0292 , H04L25/03343 , H04L25/061 , H04L2025/0349 , H04L2025/03566 , H04L2025/03617 , H04L2025/03808
摘要： A data receiver is provided which is operable to receive a signal controllably pre-distorted and transmitted by a transmitter, to generate information for adjusting the pre-distortion applied to the signal transmitted by the transmitter, and to transmit the information to the transmitter. The receiver is further operable to perform adaptive equalization to receive the signal transmitted by the transmitter.
摘要翻译：提供了一种数据接收器，其可操作以接收由发射机可控地预失真和发送的信号，以产生用于调整应用于由发射机发送的信号的预失真的信息，并将该信息发送到发射机。接收机还可操作以执行自适应均衡以接收由发射机发送的信号。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式