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1. 发明申请

US20120120701A1 TERNARY CONTENT ADDRESSABLE MEMORY USING PHASE CHANGE DEVICES 审中-公开
标题翻译：使用相位变更设备的内容可寻址存储器
公开(公告)号：US20120120701A1
公开(公告)日：2012-05-17
申请号：US13350823
申请日：2012-01-16
申请人： Brian L. Ji , Chung H. Lam , Robert K. Montoye , Bipin Rajendran
发明人： Brian L. Ji , Chung H. Lam , Robert K. Montoye , Bipin Rajendran
IPC分类号： G11C15/00
CPC分类号： G11C15/046 , G11C13/0004
摘要： A content addressable memory device with a plurality of memory cells storing ternary data values of high, low, and don't care. An aspect of the content addressable memory device is the use of first memory elements and second memory elements in the memory cells. The first and second memory elements are electrically coupled in parallel circuit to a match-line. The first memory elements are coupled to first word-lines and the second memory elements are coupled to second word-lines. The first memory elements are configured to store low resistance states if the ternary data value is low and high resistance states if the ternary data value is either high or don't care. The second memory elements are configured to store the low resistance states if the ternary data value is high and the high resistance states if the ternary data value is either low or don't care.
摘要翻译：一种具有多个存储单元的内容可寻址存储器件，其存储高，低和不关心的三进制数据值。内容可寻址存储器件的一个方面是在存储器单元中使用第一存储器元件和第二存储器元件。第一和第二存储器元件以并联电路电耦合到匹配线。第一存储器元件耦合到第一字线，并且第二存储器元件耦合到第二字线。如果三进制数据值低，则第一存储器元件被配置为存储低电阻状态，并且如果三进制数据值高或不在乎，则高电阻状态。如果三进制数据值高，则第二存储器元件被配置为存储低电阻状态，并且如果三进制数据值为低或不关心，则存在高电阻状态。

2. 发明授权

US07751217B2 Content addressable memory using phase change devices 有权
标题翻译：内容可寻址内存使用相变设备
公开(公告)号：US07751217B2
公开(公告)日：2010-07-06
申请号：US12166311
申请日：2008-07-01
申请人： Chung H. Lam , Brian L. Ji , Robert K. Montoye , Bipin Rajendran
发明人： Chung H. Lam , Brian L. Ji , Robert K. Montoye , Bipin Rajendran
IPC分类号： G11C15/00
CPC分类号： G11C13/0004 , G11C15/046
摘要： Content addressable memory device utilizing phase change devices. An aspect of the content addressable memory device is the use of a comparatively lower power search-line access element and a comparatively higher power word-line access element. The word-line access element is only utilized during write operations and the search-line access element is only utilized during search operations. The word-line access element being electrically coupled to a second end of a phase change memory element and a word-line. The search-line access element also being electrically coupled to the second end of the phase change memory element and a search-line. The search-line being electrically coupled to a match-line. A bit-line is electrically coupled to a first end of the phase change memory element. Additionally, a complementary set of access elements, a complementary phase change memory element, a complementary search-line, and a complementary bit-line are also included in the content addressable memory device.
摘要翻译：使用相变装置的内容寻址存储装置。内容可寻址存储器件的一个方面是使用相对较低功率的搜索线访问元件和相对较高功率的字线访问元件。字线访问元件仅在写入操作期间使用，并且搜索线访问元件仅在搜索操作期间被使用。字线访问元件电耦合到相变存储器元件的第二端和字线。搜索线访问元件还电耦合到相变存储元件的第二端和搜索线。搜索线电耦合到匹配线。位线电耦合到相变存储元件的第一端。此外，内容可寻址存储器件中还包括互补的一组存取元件，互补相变存储器元件，互补搜索线和互补位线。

3. 发明授权

US08120937B2 Ternary content addressable memory using phase change devices 有权
标题翻译：使用相变装置的三元内容可寻址存储器
公开(公告)号：US08120937B2
公开(公告)日：2012-02-21
申请号：US12399346
申请日：2009-03-06
申请人： Brian L. Ji , Chung H. Lam , Robert K. Montoye , Bipin Rajendran
发明人： Brian L. Ji , Chung H. Lam , Robert K. Montoye , Bipin Rajendran
IPC分类号： G11C10/00 , G11C11/00 , G11C11/56
CPC分类号： G11C15/046 , G11C13/0004
摘要： A content addressable memory device with a plurality of memory cells storing ternary data values of high, low, and don't care. An aspect of the content addressable memory device is the use of first memory elements and second memory elements in the memory cells. The first and second memory elements are electrically coupled in parallel circuit to a match-line. The first memory elements are coupled to first word-lines and the second memory elements are coupled to second word-lines. The first memory elements are configured to store low resistance states if the ternary data value is low and high resistance states if the ternary data value is either high or don't care. The second memory elements are configured to store the low resistance states if the ternary data value is high and the high resistance states if the ternary data value is either low or don't care.
摘要翻译：一种具有多个存储单元的内容可寻址存储器件，其存储高，低和不关心的三进制数据值。内容可寻址存储器件的一个方面是在存储器单元中使用第一存储器元件和第二存储器元件。第一和第二存储器元件以并联电路电耦合到匹配线。第一存储器元件耦合到第一字线，并且第二存储器元件耦合到第二字线。如果三进制数据值低，则第一存储器元件被配置为存储低电阻状态，并且如果三进制数据值高或不在乎，则高电阻状态。如果三进制数据值高，则第二存储器元件被配置为存储低电阻状态，并且如果三进制数据值为低或不关心，则存在高电阻状态。

4. 发明申请

US20100002481A1 CONTENT ADDRESSABLE MEMORY USING PHASE CHANGE DEVICES 有权
标题翻译：使用相位变更设备的内容可寻址存储器
公开(公告)号：US20100002481A1
公开(公告)日：2010-01-07
申请号：US12166311
申请日：2008-07-01
申请人： Chung H. Lam , Brian L. Ji , Robert K. Montoye , Bipin Rajendran
发明人： Chung H. Lam , Brian L. Ji , Robert K. Montoye , Bipin Rajendran
IPC分类号： G11C15/00 , G11C11/00
CPC分类号： G11C13/0004 , G11C15/046
摘要： Content addressable memory device utilizing phase change devices. An aspect of the content addressable memory device is the use of a comparatively lower power search-line access element and a comparatively higher power word-line access element. The word-line access element is only utilized during write operations and the search-line access element is only utilized during search operations. The word-line access element being electrically coupled to a second end of a phase change memory element and a word-line. The search-line access element also being electrically coupled to the second end of the phase change memory element and a search-line. The search-line being electrically coupled to a match-line. A bit-line is electrically coupled to a first end of the phase change memory element. Additionally, a complementary set of access elements, a complementary phase change memory element, a complementary search-line, and a complementary bit-line are also included in the content addressable memory device.
摘要翻译：使用相变装置的内容寻址存储装置。内容可寻址存储器件的一个方面是使用相对较低功率的搜索线访问元件和相对较高功率的字线访问元件。字线访问元件仅在写入操作期间使用，并且搜索线访问元件仅在搜索操作期间被使用。字线访问元件电耦合到相变存储器元件的第二端和字线。搜索线访问元件还电耦合到相变存储元件的第二端和搜索线。搜索线电耦合到匹配线。位线电耦合到相变存储元件的第一端。此外，内容可寻址存储器件中还包括互补的一组存取元件，互补相变存储器元件，互补搜索线和互补位线。

5. 发明申请

US20100226161A1 TERNARY CONTENT ADDRESSABLE MEMORY USING PHASE CHANGE DEVICES 有权
标题翻译：使用相位变更设备的内容可寻址存储器
公开(公告)号：US20100226161A1
公开(公告)日：2010-09-09
申请号：US12399346
申请日：2009-03-06
申请人： Brian L. Ji , Chung H. Lam , Robert K. Montoye , Bipin Rajendran
发明人： Brian L. Ji , Chung H. Lam , Robert K. Montoye , Bipin Rajendran
IPC分类号： G11C15/00 , G11C11/00 , G11C11/56
CPC分类号： G11C15/046 , G11C13/0004
摘要： A content addressable memory device with a plurality of memory cells storing ternary data values of high, low, and don't care. An aspect of the content addressable memory device is the use of first memory elements and second memory elements in the memory cells. The first and second memory elements are electrically coupled in parallel circuit to a match-line. The first memory elements are coupled to first word-lines and the second memory elements are coupled to second word-lines. The first memory elements are configured to store low resistance states if the ternary data value is low and high resistance states if the ternary data value is either high or don't care. The second memory elements are configured to store the low resistance states if the ternary data value is high and the high resistance states if the ternary data value is either low or don't care.
摘要翻译：一种具有多个存储单元的内容可寻址存储器件，其存储高，低和不关心的三进制数据值。内容可寻址存储器件的一个方面是在存储器单元中使用第一存储器元件和第二存储器元件。第一和第二存储器元件以并联电路电耦合到匹配线。第一存储器元件耦合到第一字线，并且第二存储器元件耦合到第二字线。如果三进制数据值低，则第一存储器元件被配置为存储低电阻状态，并且如果三进制数据值高或不在乎，则高电阻状态。如果三进制数据值高，则第二存储器元件被配置为存储低电阻状态，并且如果三进制数据值为低或不关心，则存在高电阻状态。

6. 发明申请

US20120259804A1 RECONFIGURABLE AND CUSTOMIZABLE GENERAL-PURPOSE CIRCUITS FOR NEURAL NETWORKS 有权
公开(公告)号：US20120259804A1
公开(公告)日：2012-10-11
申请号：US13083414
申请日：2011-04-08
申请人： Bernard V. Brezzo , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
发明人： Bernard V. Brezzo , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
IPC分类号： G06N3/04 , G06N3/08
CPC分类号： G06N3/063 , G06N3/04 , G06N3/049 , G06N3/082
摘要： A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.

7. 发明申请

US20110134676A1 RESISTIVE MEMORY DEVICES HAVING A NOT-AND (NAND) STRUCTURE 有权
标题翻译：具有非和（非）结构的电阻式存储器件
公开(公告)号：US20110134676A1
公开(公告)日：2011-06-09
申请号：US12631310
申请日：2009-12-04
申请人： Matthew J. Breitwisch , Gary S. Ditlow , Michele M. Franceschini , Luis A. Lastras-Montano , Robert K. Montoye , Bipin Rajendran
发明人： Matthew J. Breitwisch , Gary S. Ditlow , Michele M. Franceschini , Luis A. Lastras-Montano , Robert K. Montoye , Bipin Rajendran
IPC分类号： G11C15/00 , G11C11/00 , G11C7/00
CPC分类号： G11C15/046 , G11C13/0004 , G11C13/003 , G11C13/0069 , G11C16/0483 , G11C2013/0088 , G11C2013/0092 , G11C2213/75
摘要： Resistive memories having a not-and (NAND) structure including a resistive memory cell. The resistive memory cell includes a resistive memory element for storing a resistance value and a memory element access device for controlling access to the resistive memory element. The memory element access device is connected in parallel to the resistive memory element.
摘要翻译：具有包括电阻存储单元的非 - 和（NAND）结构的电阻存储器。电阻性存储单元包括用于存储电阻值的电阻性存储器元件和用于控制对电阻式存储器元件的访问的存储元件访问器件。存储元件存取装置与电阻式存储元件并联连接。

8. 发明授权

US08107276B2 Resistive memory devices having a not-and (NAND) structure 有权
标题翻译：具有非 - 和（NAND）结构的电阻式存储器件
公开(公告)号：US08107276B2
公开(公告)日：2012-01-31
申请号：US12631310
申请日：2009-12-04
申请人： Matthew J. Breitwisch , Gary S. Ditlow , Michele M. Franceschini , Luis A. Lastras-Montano , Robert K. Montoye , Bipin Rajendran
发明人： Matthew J. Breitwisch , Gary S. Ditlow , Michele M. Franceschini , Luis A. Lastras-Montano , Robert K. Montoye , Bipin Rajendran
IPC分类号： G11C11/00
CPC分类号： G11C15/046 , G11C13/0004 , G11C13/003 , G11C13/0069 , G11C16/0483 , G11C2013/0088 , G11C2013/0092 , G11C2213/75
摘要： Resistive memories having a not-and (NAND) structure including a resistive memory cell. The resistive memory cell includes a resistive memory element for storing a resistance value and a memory element access device for controlling access to the resistive memory element. The memory element access device is connected in parallel to the resistive memory element.
摘要翻译：具有包括电阻存储单元的非 - 和（NAND）结构的电阻存储器。电阻性存储单元包括用于存储电阻值的电阻性存储器元件和用于控制对电阻式存储器元件的访问的存储元件访问器件。存储元件存取装置与电阻式存储元件并联连接。

9. 发明授权

US08898097B2 Reconfigurable and customizable general-purpose circuits for neural networks 有权
标题翻译：可重构和可定制的神经网络通用电路
公开(公告)号：US08898097B2
公开(公告)日：2014-11-25
申请号：US13587594
申请日：2012-08-16
申请人： Bernard V. Brezzo , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
发明人： Bernard V. Brezzo , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
IPC分类号： G06N3/063 , G06N3/04
CPC分类号： G06N3/063 , G06N3/04 , G06N3/049 , G06N3/082
摘要： A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.
摘要翻译：提供可重构神经网络电路。可重构神经网络电路包括电子突触阵列，其包括互连多个数字电子神经元的多个突触。每个神经元包括积分器，其对输入尖峰进行积分，并且当集成输入超过阈值时产生信号。电路还包括用于重新配置突触阵列的控制模块。控制模块包括控制电路操作的定时的全局最终状态机，以及允许加标神经元依次访问突触阵列的优先编码器。

10. 发明授权

US08856055B2 Reconfigurable and customizable general-purpose circuits for neural networks 有权
公开(公告)号：US08856055B2
公开(公告)日：2014-10-07
申请号：US13083414
申请日：2011-04-08
申请人： Bernard V. Brezzo , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
发明人： Bernard V. Brezzo , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
IPC分类号： G06N3/063 , G06N3/04
CPC分类号： G06N3/063 , G06N3/04 , G06N3/049 , G06N3/082
摘要： A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.

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