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1. 发明授权

US08059438B2 Content addressable memory array programmed to perform logic operations 有权
标题翻译：内容可寻址存储器阵列被编程为执行逻辑运算
公开(公告)号：US08059438B2
公开(公告)日：2011-11-15
申请号：US12549740
申请日：2009-08-28
申请人： Leland Chang , Gary S. Ditlow , Brian L. Ji , Robert K. Montoye
发明人： Leland Chang , Gary S. Ditlow , Brian L. Ji , Robert K. Montoye
IPC分类号： G11C15/00
CPC分类号： G11C15/046 , G11C7/1006 , G11C13/0004
摘要： A memory device for performing logical operations on two or more input variables includes a match line and first and second memory cells. The first and second memory cells collectively include a first, second, third and fourth memory element. The first, second, third and fourth memory elements may have either a first value or a second value programmed therein and wherein the first, second, third and fourth memory elements are programmed to either the high or low resistive values based on a particular logic function to be performed.
摘要翻译：用于对两个或多个输入变量执行逻辑运算的存储器件包括匹配线和第一和第二存储器单元。第一和第二存储单元集体地包括第一，第二，第三和第四存储元件。第一，第二，第三和第四存储器元件可以具有在其中编程的第一值或第二值，并且其中基于特定逻辑功能将第一，第二，第三和第四存储器元件编程为高电阻值或低电阻值被执行。

2. 发明授权

US07948782B2 Content addressable memory reference clock 有权
标题翻译：内容可寻址内存参考时钟
公开(公告)号：US07948782B2
公开(公告)日：2011-05-24
申请号：US12549772
申请日：2009-08-28
申请人： Leland Chang , Gary S. Ditlow , Brian L. Ji , Robert K. Montoye
发明人： Leland Chang , Gary S. Ditlow , Brian L. Ji , Robert K. Montoye
IPC分类号： G11C15/00
CPC分类号： G11C15/046 , G11C13/0004
摘要： A memory system includes a content addressable memory (CAM) including a plurality of match lines, each match line having a plurality of memory cells coupled thereto. The system also includes a match detector coupled to the CAM and a reference match line having a plurality of reference memory cells coupled thereto, the reference memory cells being of the same type and the memory cells. The system also includes a match line sensor coupled to the reference match line and the match detector that determines a characteristic of the reference match line and provides a timing signal to the match detector based on the characteristic.
摘要翻译：存储器系统包括包括多个匹配线的内容可寻址存储器（CAM），每个匹配线具有耦合到其上的多个存储器单元。该系统还包括耦合到CAM的匹配检测器和具有耦合到其上的多个参考存储器单元的参考匹配线，参考存储器单元是相同类型的存储器单元。该系统还包括耦合到参考匹配线的匹配线传感器和匹配检测器，其确定参考匹配线的特性，并且基于该特性向匹配检测器提供定时信号。

3. 发明授权

US08054662B2 Content addressable memory array 有权
标题翻译：内容可寻址存储器阵列
公开(公告)号：US08054662B2
公开(公告)日：2011-11-08
申请号：US12549752
申请日：2009-08-28
申请人： Leland Chang , Gary S. Ditlow , Brian L. Ji , Robert K. Montoye
发明人： Leland Chang , Gary S. Ditlow , Brian L. Ji , Robert K. Montoye
IPC分类号： G11C15/00
CPC分类号： G11C15/046 , G11C7/1006 , G11C11/5678 , G11C13/0004
摘要： A memory device for storing one or more addresses includes a match line and first and second memory cells that form a 2-bit memory cell. Each memory cell includes two memory elements coupled to a match line and selection lines coupled thereto. The selection lines provide a signal representative of a logical combination of at least two different inputs.
摘要翻译：用于存储一个或多个地址的存储器件包括匹配线和形成2位存储器单元的第一和第二存储器单元。每个存储器单元包括耦合到匹配线的两个存储器元件和与其耦合的选择线。选择线提供表示至少两个不同输入的逻辑组合的信号。

4. 发明申请

US20110051486A1 CONTENT ADDRESSABLE MEMORY REFERENCE CLOCK 有权
标题翻译：内容可寻址内存参考时钟
公开(公告)号：US20110051486A1
公开(公告)日：2011-03-03
申请号：US12549772
申请日：2009-08-28
申请人： Leland Chang , Gary S. Ditlow , Brian L. Ji , Robert K. Montoye
发明人： Leland Chang , Gary S. Ditlow , Brian L. Ji , Robert K. Montoye
IPC分类号： G11C15/00 , G11C11/00 , G11C7/02
CPC分类号： G11C15/046 , G11C13/0004
摘要： A memory system includes a content addressable memory (CAM) including a plurality of match lines, each match line having a plurality of memory cells coupled thereto. The system also includes a match detector coupled to the CAM and a reference match line having a plurality of reference memory cells coupled thereto, the reference memory cells being of the same type and the memory cells. The system also includes a match line sensor coupled to the reference match line and the match detector that determines a characteristic of the reference match line and provides a timing signal to the match detector based on the characteristic.
摘要翻译：存储器系统包括包括多个匹配线的内容可寻址存储器（CAM），每个匹配线具有耦合到其上的多个存储器单元。该系统还包括耦合到CAM的匹配检测器和具有耦合到其上的多个参考存储器单元的参考匹配线，参考存储器单元是相同类型的存储器单元。该系统还包括耦合到参考匹配线的匹配线传感器和匹配检测器，其确定参考匹配线的特性，并且基于该特性向匹配检测器提供定时信号。

5. 发明申请

US20110051482A1 CONTENT ADDRESSABLE MEMORY ARRAY PROGRAMMED TO PERFORM LOGIC OPERATIONS 有权
标题翻译：内容可寻址的存储阵列编程执行逻辑操作
公开(公告)号：US20110051482A1
公开(公告)日：2011-03-03
申请号：US12549740
申请日：2009-08-28
申请人： Leland Chang , Gary S. Ditlow , Brian L. Ji , Robert K. Montoye
发明人： Leland Chang , Gary S. Ditlow , Brian L. Ji , Robert K. Montoye
IPC分类号： G11C15/00 , G11C11/00 , G11C7/00
CPC分类号： G11C15/046 , G11C7/1006 , G11C13/0004
摘要： A memory device for performing logical operations on two or more input variables includes a match line and first and second memory cells. The first and second memory cells collectively include a first, second, third and fourth memory element. The first, second, third and fourth memory elements may have either a first value or a second value programmed therein and wherein the first, second, third and fourth memory elements are programmed to either the high or low resistive values based on a particular logic function to be performed.
摘要翻译：用于对两个或多个输入变量执行逻辑运算的存储器件包括匹配线和第一和第二存储器单元。第一和第二存储单元集体地包括第一，第二，第三和第四存储元件。第一，第二，第三和第四存储器元件可以具有在其中编程的第一值或第二值，并且其中基于特定逻辑功能将第一，第二，第三和第四存储器元件编程为高电阻值或低电阻值被执行。

6. 发明申请

US20110051485A1 CONTENT ADDRESSABLE MEMORY ARRAY WRITING 审中-公开
标题翻译：内容可寻址存储阵列写
公开(公告)号：US20110051485A1
公开(公告)日：2011-03-03
申请号：US12549761
申请日：2009-08-28
申请人： Leland Chang , Gary S. Ditlow , Brian L. Ji , Robert K. Montoye
发明人： Leland Chang , Gary S. Ditlow , Brian L. Ji , Robert K. Montoye
IPC分类号： G11C15/00 , G11C7/00 , G11C11/00
CPC分类号： G11C15/00 , G11C13/0004 , G11C15/02 , G11C15/046
摘要： A memory system for storing one or more addresses includes a transposable memory having word lines, bit lines, transposed word lines and transposed bit lines and that receives and stores an input array having dimensions M by N and a content addressable memory (CAM) that reads the transposed word lines of the transposable memory to form input words and that stores the input words in an N by M array.
摘要翻译：用于存储一个或多个地址的存储器系统包括具有字线，位线，转置字线和转置位线的可转位存储器，并且接收并存储尺寸为M×N的输入阵列和读取的内容可寻址存储器（CAM）转置存储器的转置字线，以形成输入字，并将输入字存储在N乘M阵列中。

7. 发明申请

US20110051483A1 CONTENT ADDRESSABLE MEMORY ARRAY 有权
标题翻译：内容可寻址存储阵列
公开(公告)号：US20110051483A1
公开(公告)日：2011-03-03
申请号：US12549752
申请日：2009-08-28
申请人： Leland Chang , Gary S. Ditlow , Brian L. Ji , Robert K. Montoye
发明人： Leland Chang , Gary S. Ditlow , Brian L. Ji , Robert K. Montoye
IPC分类号： G11C15/00 , G11C11/00 , G11C8/00 , G11C7/00 , G11C11/56
CPC分类号： G11C15/046 , G11C7/1006 , G11C11/5678 , G11C13/0004
摘要： A memory device for storing one or more addresses includes a match line and first and second memory cells that form a 2-bit memory cell. Each memory cell includes two memory elements coupled to a match line and selection lines coupled thereto. The selection lines provide a signal representative of a logical combination of at least two different inputs.
摘要翻译：用于存储一个或多个地址的存储器件包括匹配线和形成2位存储器单元的第一和第二存储器单元。每个存储器单元包括耦合到匹配线的两个存储器元件和与其耦合的选择线。选择线提供表示至少两个不同输入的逻辑组合的信号。

8. 发明申请

US20110298440A1 LOW VOLTAGE SIGNALING 有权
标题翻译：低电压信号
公开(公告)号：US20110298440A1
公开(公告)日：2011-12-08
申请号：US12794995
申请日：2010-06-07
申请人： Leland Chang , Robert H. Dennard , Brian L. Ji , Wing K. Luk , Robert K. Montoye
发明人： Leland Chang , Robert H. Dennard , Brian L. Ji , Wing K. Luk , Robert K. Montoye
IPC分类号： G05F5/00
CPC分类号： H02M3/07 , H02M2003/072
摘要： A low voltage signaling system for integrated circuits includes a first voltage domain operating at a nominal integrated circuit (IC) power supply voltage (Vdd) swing level at a signal transmitting end of a first chip, a second voltage domain having one or more transmission interconnect lines operating at a reduced voltage swing level with respect to the first voltage domain, and a third voltage domain at a signal receiving end of a second chip, the third voltage domain operating at the Vdd swing level; wherein an input signal originating from the first voltage domain is down converted to operate at the reduced voltage swing level for transmission over the second voltage domain, and wherein the third voltage domain senses the input signal transmitted over the second voltage domain and generates an output signal operating back up at the Vdd swing level.
摘要翻译：用于集成电路的低电压信号系统包括在第一芯片的信号发射端处以标称集成电路（IC）电源电压（Vdd）摆幅电平操作的第一电压域，具有一个或多个传输互连的第二电压域以相对于第一电压域的降低的电压摆动电平工作的线路，以及在第二芯片的信号接收端的第三电压域，以Vdd摆动电平工作的第三电压域; 其中源自所述第一电压域的输入信号被降频转换以在所述降低的电压摆幅电平下工作以在所述第二电压域上传输，并且其中所述第三电压域检测在所述第二电压域上传输的输入信号，并产生输出信号以Vdd摆动水平运行。

9. 发明授权

US08629705B2 Low voltage signaling 有权
标题翻译：低电压信号
公开(公告)号：US08629705B2
公开(公告)日：2014-01-14
申请号：US12794995
申请日：2010-06-07
申请人： Leland Chang , Robert H. Dennard , Brian L. Ji , Wing K. Luk , Robert K. Montoye
发明人： Leland Chang , Robert H. Dennard , Brian L. Ji , Wing K. Luk , Robert K. Montoye
IPC分类号： H03L5/00
CPC分类号： H02M3/07 , H02M2003/072
摘要： A low voltage signaling system for integrated circuits includes a first voltage domain operating at a nominal integrated circuit (IC) power supply voltage (Vdd) swing level at a signal transmitting end of a first chip, a second voltage domain having one or more transmission interconnect lines operating at a reduced voltage swing level with respect to the first voltage domain, and a third voltage domain at a signal receiving end of a second chip, the third voltage domain operating at the Vdd swing level; wherein an input signal originating from the first voltage domain is down converted to operate at the reduced voltage swing level for transmission over the second voltage domain, and wherein the third voltage domain senses the input signal transmitted over the second voltage domain and generates an output signal operating back up at the Vdd swing level.
摘要翻译：用于集成电路的低电压信号系统包括在第一芯片的信号发射端处以标称集成电路（IC）电源电压（Vdd）摆幅电平操作的第一电压域，具有一个或多个传输互连的第二电压域以相对于第一电压域的降低的电压摆动电平工作的线路，以及在第二芯片的信号接收端的第三电压域，以Vdd摆动电平工作的第三电压域; 其中源自所述第一电压域的输入信号被降频转换以在所述降低的电压摆幅电平下工作以在所述第二电压域上传输，并且其中所述第三电压域检测在所述第二电压域上传输的输入信号，并产生输出信号以Vdd摆动水平运行。

10. 发明授权

US08687398B2 Sense scheme for phase change material content addressable memory 有权
标题翻译：相变材料内容可寻址存储器的感应方案
公开(公告)号：US08687398B2
公开(公告)日：2014-04-01
申请号：US13407813
申请日：2012-02-29
申请人： Leland Chang , Chung H. Lam , Jing Li , Robert K. Montoye
发明人： Leland Chang , Chung H. Lam , Jing Li , Robert K. Montoye
IPC分类号： G11C15/00
CPC分类号： G11C15/00
摘要： A sensing circuit and method for sensing match lines in content addressable memory. The sensing circuit includes an inverter electrically coupled in a feedback loop to a match line. The inverter includes an inverting threshold of the match line. The match line is charged to substantially a first voltage threshold during a pre-charge phase. An evaluation phase occurs when the match line voltage drops from substantially the first voltage threshold to substantially the second voltage threshold.
摘要翻译：一种用于感测内容可寻址存储器中匹配线的感测电路和方法。感测电路包括电反馈回路中电耦合到匹配线的反相器。逆变器包括匹配线的反相阈值。在预充电阶段期间，将匹配线充电至基本上第一电压阈值。当匹配线电压从基本上从第一电压阈值下降到基本上第二电压阈值时，发生评估阶段。

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