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51. 发明授权

US07405990B2 Method and apparatus for in-system redundant array repair on integrated circuits 有权
公开(公告)号：US07405990B2
公开(公告)日：2008-07-29
申请号：US11872085
申请日：2007-10-15
申请人： Arthur A. Bright , Paul G. Crumley , Marc B. Dombrowa , Steven M. Douskey , Rudolf A. Haring , Steven F. Oakland , Michael R. Ouellette , Scott A. Strissel
发明人： Arthur A. Bright , Paul G. Crumley , Marc B. Dombrowa , Steven M. Douskey , Rudolf A. Haring , Steven F. Oakland , Michael R. Ouellette , Scott A. Strissel
IPC分类号： G11C17/18 , G11C7/10 , G11C8/00 , H03K19/003 , H03K19/00
CPC分类号： G11C29/4401 , G11C29/802
摘要： Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

52. 发明授权

US07397709B2 Method and apparatus for in-system redundant array repair on integrated circuits 有权
标题翻译：用于集成电路系统内冗余阵列修复的方法和装置
公开(公告)号：US07397709B2
公开(公告)日：2008-07-08
申请号：US11872088
申请日：2007-10-15
申请人： Arthur A. Bright , Paul G. Crumley , Marc B. Dombrowa , Steven M. Douskey , Rudolf A. Haring , Steven F. Oakland , Michael R. Ouellette , Scott A. Strissel
发明人： Arthur A. Bright , Paul G. Crumley , Marc B. Dombrowa , Steven M. Douskey , Rudolf A. Haring , Steven F. Oakland , Michael R. Ouellette , Scott A. Strissel
IPC分类号： G11C7/10 , G11C29/00 , G11C17/18 , H03K19/003 , G06F11/00
CPC分类号： G11C29/4401 , G11C29/802
摘要： Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.
摘要翻译：公开了一种修复包括多个存储器阵列的类型的集成电路的方法，以及用于控制用于控制阵列的冗余逻辑的控制数据的保险丝盒。该方法包括以下步骤：向集成电路提供控制数据选择器，用于将控制数据从保险丝盒传送到存储器阵列; 提供备用控制数据源，集成电路外部; 并将替代控制数据源连接到控制数据选择器。该方法还包括在给定时间，通过控制数据选择器将备用控制数据从其源传递到存储器阵列以控制存储器阵列的冗余逻辑的步骤。

53. 发明授权

US07210085B2 Method and apparatus for test and repair of marginally functional SRAM cells 失效
标题翻译：用于边缘功能SRAM单元的测试和修复的方法和装置
公开(公告)号：US07210085B2
公开(公告)日：2007-04-24
申请号：US10725668
申请日：2003-12-02
申请人： Ciaran J. Brennan , Steven M. Eustis , Michael T. Fragano , Michael R. Ouellette , Neelesh G. Pai , Jeremy P. Rowland , Kevin M. Tompsett , David J. Wager
发明人： Ciaran J. Brennan , Steven M. Eustis , Michael T. Fragano , Michael R. Ouellette , Neelesh G. Pai , Jeremy P. Rowland , Kevin M. Tompsett , David J. Wager
IPC分类号： G01R31/28
CPC分类号： G11C29/4401 , G11C11/41 , G11C29/44 , G11C29/70 , G11C2029/0401
摘要： A method of manufacturing a device having embedded memory including a plurality of memory cells. During manufacturing test, a first test stress is applied to selected cells of the plurality of memory cells with a built-in self test. At least one weak memory cell is identified. The at least one weak memory cell is repaired. A second test stress is applied to the selected cells and the repaired cells with the built-in self test.
摘要翻译：一种制造具有包括多个存储单元的嵌入式存储器的装置的方法。在制造测试期间，通过内置的自我测试将第一测试应力施加到多个存储单元的选定单元。识别至少一个弱记忆体单元。至少一个弱记忆体被修复。第二个测试应力应用于所选择的细胞和修复的细胞与内置的自我测试。

54. 发明授权

US07089132B2 Method and system for providing quality control on wafers running on a manufacturing line 失效
标题翻译：用于对在生产线上运行的晶片提供质量控制的方法和系统
公开(公告)号：US07089132B2
公开(公告)日：2006-08-08
申请号：US10709805
申请日：2004-05-28
申请人： Jeanne P. Bickford , Vernon R. Norman , Michael R. Ouellette , Mark S. Styduhar , Brian Worth
发明人： Jeanne P. Bickford , Vernon R. Norman , Michael R. Ouellette , Mark S. Styduhar , Brian Worth
IPC分类号： G01N37/00 , G01R31/26
CPC分类号： G01R31/2831 , H01L22/14
摘要： A method for providing quality control on wafers running on a manufacturing line is disclosed. The resistances on a group of manufacturing test structures within a wafer running on a wafer manufacturing line are initially measured. Then, an actual distribution value is obtained based on the result of the measured resistances on the group of manufacturing test structures. The difference between the actual distribution value and a predetermined distribution value is recorded. Next, the resistances on a group of design test structures within the wafer are measured. The measured resistances of the group of design test structures are correlated to the measured resistances of the group of manufacturing test structures in order to obtain an offset value. The resistance of an adjustable resistor circuit within the wafer and subsequent wafers running on the wafer manufacturing line are adjusted according to the offset value.
摘要翻译：公开了一种用于对在生产线上运行的晶片进行质量控制的方法。初始测量在晶片生产线上运行的晶片内的一组制造测试结构的电阻。然后，基于制造试验结构体的测定电阻的结果，求出实际的分布值。记录实际分布值与预定分布值之间的差。接下来，测量晶片内的一组设计测试结构的电阻。设计测试结构组的测量电阻与制造测试结构组的测量电阻相关，以获得偏移值。根据偏移值调整晶片内的可调节电阻电路和在晶片生产线上运行的随后的晶片的电阻。

55. 发明授权

US06766468B2 Memory BIST and repair 有权
标题翻译：记忆BIST和修复
公开(公告)号：US06766468B2
公开(公告)日：2004-07-20
申请号：US09682023
申请日：2001-07-11
申请人： John E. Barth, Jr. , Jeffrey H. Dreibelbis , Michael R. Ouellette
发明人： John E. Barth, Jr. , Jeffrey H. Dreibelbis , Michael R. Ouellette
IPC分类号： H02H305
CPC分类号： G11C29/44 , G11C29/72 , G11C2029/1208
摘要： A method of memory BIST (Built-In Self Test) and memory repair that stores a redundancy calculation on-chip, as opposed to scanning this data off-chip for later use. This method no longer requires level-sensitive scan design (LSSD) scanning of memory redundancy data off-chip to the tester, and therefore does not require re-contacting of the chip for electrical fuse blow.
摘要翻译：内存BIST（内置自检）和内存修复方法，用于存储片上冗余计算，而不是将数据片外扫描以备以后使用。该方法不再需要对测试仪进行片外存储器冗余数据的电平敏感扫描设计（LSSD）扫描，因此不需要再次接触芯片进行电熔丝熔断。

56. 发明授权

US06249470B1 Bi-directional differential low power sense amp and memory system 有权
标题翻译：双向差分低功率检测放大器和存储器系统
公开(公告)号：US06249470B1
公开(公告)日：2001-06-19
申请号：US09454265
申请日：1999-12-03
申请人： John E. Andersen , Michael R. Ouellette
发明人： John E. Andersen , Michael R. Ouellette
IPC分类号： G11C702
CPC分类号： G11C11/419 , G11C7/065
摘要： According to the preferred embodiment, a device and method is provided for reducing power consumption in memory devices. The preferred embodiment reduces power consumption by providing a sense amplifier that reduces power consumption while providing high performance. In the preferred embodiment, the sense amplifier comprises a bi-directional sense amp that is configurable for use on low power static random access memory (SRAM) devices. The bi-directional sense amp allows the same sense amp to be used for both read and write operations on the memory cells. The preferred embodiment sense amp facilitates the use of differential data buses, further reducing power consumption while providing high performance. Thus, the preferred embodiment bi-directional differential sense amp reduces the device size and complexity, reducing power consumption while providing high performance memory access.
摘要翻译：根据优选实施例，提供了一种用于降低存储器件中的功耗的装置和方法。优选实施例通过提供在提供高性能的同时降低功耗的读出放大器来降低功耗。在优选实施例中，读出放大器包括可配置用于低功率静态随机存取存储器（SRAM）器件的双向读出放大器。双向读出放大器允许将相同的感测放大器用于存储器单元上的读取和写入操作。优选实施例的感测放大器有助于使用差分数据总线，进一步降低功耗，同时提供高性能。因此，优选实施例的双向差分检测放大器降低了器件尺寸和复杂性，降低了功耗，同时提供了高性能的存储器访问。

57. 发明授权

US08661399B1 Built-in-self-test (BIST) organizational file generation 有权
标题翻译：内置自检（BIST）组织文件生成
公开(公告)号：US08661399B1
公开(公告)日：2014-02-25
申请号：US13567127
申请日：2012-08-06
申请人： Craig M. Monroe , Michael R. Ouellette , Douglas E. Sprague
发明人： Craig M. Monroe , Michael R. Ouellette , Douglas E. Sprague
IPC分类号： G06F17/50
CPC分类号： G11C29/54 , G11C5/04 , G11C29/12
摘要： Aspects of the invention provide for creating a built-in-self-test (BIST) organizational file for an integrated circuit (IC) chip. In one embodiment, a method includes: receiving a design file including a hierarchy of memory modules, each module including a plurality of memory wrappers; scanning each memory wrapper in each hierarchical level of memory modules for a BIST type; creating, based on the hierarchical level and the BIST type, an ordered list of memory wrappers; adding, based on the BIST type, a BIST engine for each memory wrapper listed in the ordered list; and adding a plurality of references statements to the ordered list to create the BIST organizational file.
摘要翻译：本发明的方面提供了用于为集成电路（IC）芯片创建内置自测（BIST）组织文件。在一个实施例中，一种方法包括：接收包括存储器模块层级的设计文件，每个模块包括多个存储器包装器; 在BIST类型的每个层级的内存模块中扫描每个内存包装器; 基于层次级别和BIST类型创建存储器包装器的有序列表; 根据BIST类型添加一个BIST引擎，用于在有序列表中列出的每个内存包装器; 并将多个引用语句添加到有序列表以创建BIST组织文件。

58. 发明授权

US08595678B2 Validating interconnections between logic blocks in a circuit description 失效
标题翻译：验证电路描述中的逻辑块之间的互连
公开(公告)号：US08595678B2
公开(公告)日：2013-11-26
申请号：US13365370
申请日：2012-02-03
申请人： Craig M. Monroe , Michael R. Ouellette , Douglas E. Sprague , Michael A. Ziegerhofer
发明人： Craig M. Monroe , Michael R. Ouellette , Douglas E. Sprague , Michael A. Ziegerhofer
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/14
摘要： Disclosed is a program for creating a checking-statement which can be subsequently used to validate interconnections between logic blocks in a circuit design. The checking-statement is created by taking a description of how logic blocks in a circuit design are associated to one another (if at all), and cross referencing the description with rule statements specific to each logic block defining the allowable connections between the specific logic block and other logic blocks.
摘要翻译：公开了一种用于创建检查语句的程序，其可以随后用于验证电路设计中的逻辑块之间的互连。检查语句是通过描述电路设计中的逻辑块如何相互关联（如果有的话）来创建的，并且将描述与对每个逻辑块特定的规则语句进行交叉引用，以定义特定逻辑之间的允许连接块和其他逻辑块。

59. 发明申请

US20130205268A1 VALIDATING INTERCONNECTIONS BETWEEN LOGIC BLOCKS IN A CIRCUIT DESCRIPTION 失效
标题翻译：验证电路中逻辑块之间的互连
公开(公告)号：US20130205268A1
公开(公告)日：2013-08-08
申请号：US13365370
申请日：2012-02-03
申请人： Craig M. Monroe , Michael R. Ouellette , Douglas E. Sprague , Michael A. Ziegerhofer
发明人： Craig M. Monroe , Michael R. Ouellette , Douglas E. Sprague , Michael A. Ziegerhofer
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/14
摘要： Disclosed is a program for creating a checking-statement which can be subsequently used to validate interconnections between logic blocks in a circuit design. The checking-statement is created by taking a description of how logic blocks in a circuit design are associated to one another (if at all), and cross referencing the description with rule statements specific to each logic block defining the allowable connections between the specific logic block and other logic blocks.
摘要翻译：公开了一种用于创建检查语句的程序，其可以随后用于验证电路设计中的逻辑块之间的互连。检查语句是通过描述电路设计中的逻辑块如何相互关联（如果有的话）来创建的，并且将描述与对每个逻辑块特定的规则语句进行交叉引用，以定义特定逻辑之间的允许连接块和其他逻辑块。

60. 发明申请

US20120062300A1 CIRCUIT AND METHOD FOR ASYNCHRONOUS PIPELINE PROCESSING WITH VARIABLE REQUEST SIGNAL DELAY 有权
标题翻译：具有可变请求信号延迟的异步管道加工的电路和方法
公开(公告)号：US20120062300A1
公开(公告)日：2012-03-15
申请号：US12882425
申请日：2010-09-15
申请人： Michael R. Ouellette , Faraydon Pakbaz , Jack R. Smith , Sebastian T. Ventrone
发明人： Michael R. Ouellette , Faraydon Pakbaz , Jack R. Smith , Sebastian T. Ventrone
IPC分类号： H03H11/26
CPC分类号： G06F5/10 , G06F2205/104
摘要： Disclosed are embodiments of an asynchronous pipeline circuit. In each stage of the circuit, a variable delay line is incorporated into the request signal path. A tap encoder monitors data entering the stage to detect any state changes occurring in specific data bits. Based on the results of this monitoring (i.e., based on which of the specific data bits, if any, exhibit state changes), the tap encoder enables a specific tap in the variable delay line and, thereby, automatically adjusts the delay of a request signal transmitted along the request signal path. Using a variable request signal delay allows data from a transmitting stage to be captured by a receiving stage prior to the expiration of the maximum possible processing time associated with the transmitting stage, thereby minimizing overall processing time. Also disclosed are embodiments of methods for asynchronous pipeline processing with variable request signal delay and for incorporating variable request signal delay into an asynchronous pipeline circuit design.
摘要翻译：公开了异步管线电路的实施例。在电路的每个阶段，可变延迟线被并入到请求信号路径中。抽头编码器监视进入阶段的数据，以检测在特定数据位中发生的任何状态变化。基于该监视的结果（即，基于特定数据位中的哪一个，如果有的话，表现出状态改变），则分接编码器在可变延迟线中启用特定抽头，从而自动调整请求的延迟信号沿请求信号路径传输。使用可变请求信号延迟允许在与发送级相关联的最大可能处理时间到期之前由接收级捕获来自发送级的数据，从而最小化整个处理时间。还公开了用于具有可变请求信号延迟的异步流水线处理的方法的实施例，并且将可变请求信号延迟并入到异步管线电路设计中。

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