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1. 发明授权

US07089132B2 Method and system for providing quality control on wafers running on a manufacturing line 失效
标题翻译：用于对在生产线上运行的晶片提供质量控制的方法和系统
公开(公告)号：US07089132B2
公开(公告)日：2006-08-08
申请号：US10709805
申请日：2004-05-28
申请人： Jeanne P. Bickford , Vernon R. Norman , Michael R. Ouellette , Mark S. Styduhar , Brian Worth
发明人： Jeanne P. Bickford , Vernon R. Norman , Michael R. Ouellette , Mark S. Styduhar , Brian Worth
IPC分类号： G01N37/00 , G01R31/26
CPC分类号： G01R31/2831 , H01L22/14
摘要： A method for providing quality control on wafers running on a manufacturing line is disclosed. The resistances on a group of manufacturing test structures within a wafer running on a wafer manufacturing line are initially measured. Then, an actual distribution value is obtained based on the result of the measured resistances on the group of manufacturing test structures. The difference between the actual distribution value and a predetermined distribution value is recorded. Next, the resistances on a group of design test structures within the wafer are measured. The measured resistances of the group of design test structures are correlated to the measured resistances of the group of manufacturing test structures in order to obtain an offset value. The resistance of an adjustable resistor circuit within the wafer and subsequent wafers running on the wafer manufacturing line are adjusted according to the offset value.
摘要翻译：公开了一种用于对在生产线上运行的晶片进行质量控制的方法。初始测量在晶片生产线上运行的晶片内的一组制造测试结构的电阻。然后，基于制造试验结构体的测定电阻的结果，求出实际的分布值。记录实际分布值与预定分布值之间的差。接下来，测量晶片内的一组设计测试结构的电阻。设计测试结构组的测量电阻与制造测试结构组的测量电阻相关，以获得偏移值。根据偏移值调整晶片内的可调节电阻电路和在晶片生产线上运行的随后的晶片的电阻。

2. 发明申请

US20080120838A1 Impedance Calibration for Source Series Terminated Serial Link Transmitter 失效
标题翻译：源串联终端串行链路发射机的阻抗校准
公开(公告)号：US20080120838A1
公开(公告)日：2008-05-29
申请号：US12028439
申请日：2008-02-08
申请人： Steven M. Clements , William P. Cornwell , Carrie E. Cox , Hayden C. Cranford , Vernon R. Norman
发明人： Steven M. Clements , William P. Cornwell , Carrie E. Cox , Hayden C. Cranford , Vernon R. Norman
IPC分类号： H01R43/00
CPC分类号： G01R35/007 , Y10T29/49004 , Y10T29/4913 , Y10T29/49147 , Y10T29/49155 , Y10T29/49169 , Y10T29/49174
摘要： Substantially-accurate calibration of output impedance of a device-under-test (DUT) to within a predetermined range of allowable impedance. The DUT is part of a source series terminated (SST) serial link transmitter, in which two branches of parallel transistors each provide an impedance value when particular transistors of the parallel branch are turned on. The impedance value is added to a series-connected resistor to provide the output impedance. The DUT consists of one branch of parallel transistors in series with a resistor. Output impedance of the DUT is compared to the resistance of a reference resistor, and the comparator provides a control signal based on whether the output impedance falls within the pre-set percentage variance of the reference resistance. The control signal is processed by a FSM (finite state machine) that individually turns on or off the transistors within the parallel branch until the DUT impedance value falls within the desired range.
摘要翻译：将被测器件（DUT）的输出阻抗基本上精确地校准到允许阻抗的预定范围内。 DUT是源极串行端接（SST）串行链路发射机的一部分，其中当并联支路的特定晶体管导通时，并联晶体管的两个分支都提供阻抗值。将阻抗值加到串联电阻器上以提供输出阻抗。 DUT由与电阻器串联的并行晶体管的一个分支组成。将DUT的输出阻抗与参考电阻的电阻进行比较，并且比较器根据输出阻抗是否落在参考电阻的预设百分比方差内提供控制信号。控制信号由FSM（有限状态机）进行处理，FSM单独打开或关闭并联支路内的晶体管，直到DUT阻抗值落在所需范围内。

3. 发明授权

US07368902B2 Impedance calibration for source series terminated serial link transmitter 有权
标题翻译：源串联端接串行链路发射机的阻抗校准
公开(公告)号：US07368902B2
公开(公告)日：2008-05-06
申请号：US11262101
申请日：2005-10-28
申请人： Steven M. Clements , William P. Cornwell , Carrie E. Cox , Hayden C. Cranford, Jr. , Vernon R. Norman
发明人： Steven M. Clements , William P. Cornwell , Carrie E. Cox , Hayden C. Cranford, Jr. , Vernon R. Norman
IPC分类号： G01R35/00 , H03K19/003 , G06F19/00
CPC分类号： G01R35/007 , Y10T29/49004 , Y10T29/4913 , Y10T29/49147 , Y10T29/49155 , Y10T29/49169 , Y10T29/49174
摘要： Substantially-accurate calibration of output impedance of a device-under-test (DUT) to within a predetermined range of allowable impedance. The DUT is part of a source series terminated (SST) serial link transmitter, in which two branches of parallel transistors each provide an impedance value when particular transistors of the parallel branch are turned on. The impedance value is added to a series-connected resistor to provide the output impedance. The DUT consists of one branch of parallel transistors in series with a resistor. Output impedance of the DUT is compared to the resistance of a reference resistor, and the comparator provides a control signal based on whether the output impedance falls within the pre-set percentage variance of the reference resistance. The control signal is processed by a FSM (finite state machine) that individually turns on or off the transistors within the parallel branch until the DUT impedance value falls within the desired range.
摘要翻译：将被测器件（DUT）的输出阻抗基本上精确地校准到允许阻抗的预定范围内。 DUT是源极串行端接（SST）串行链路发射机的一部分，其中当并联支路的特定晶体管导通时，并联晶体管的两个分支都提供阻抗值。将阻抗值加到串联电阻器上以提供输出阻抗。 DUT由与电阻器串联的并行晶体管的一个分支组成。将DUT的输出阻抗与参考电阻的电阻进行比较，并且比较器根据输出阻抗是否落在参考电阻的预设百分比方差内提供控制信号。控制信号由FSM（有限状态机）进行处理，FSM单独打开或关闭并联支路内的晶体管，直到DUT阻抗值落在所需范围内。

4. 发明授权

US07340660B2 Method and system for using statistical signatures for testing high-speed circuits 有权
标题翻译：统计特征用于测试高速电路的方法和系统
公开(公告)号：US07340660B2
公开(公告)日：2008-03-04
申请号：US10680679
申请日：2003-10-07
申请人： Hayden C. Cranford, Jr. , Vernon R. Norman , Martin L. Schmatz
发明人： Hayden C. Cranford, Jr. , Vernon R. Norman , Martin L. Schmatz
IPC分类号： G01R31/3193 , G01R31/316
CPC分类号： G01R31/31901 , G01R31/31707
摘要： A method and system for testing a high-speed circuit is disclosed. The method and system include obtaining a high-speed statistical signature of the high-speed circuit using a conventional tester. The method and system further include comparing the high-speed statistical signature of the high-speed circuit to an expected signature. Consequently, it can be determined whether the high-speed circuit functions within the desired parameters.
摘要翻译：公开了一种用于测试高速电路的方法和系统。该方法和系统包括使用常规测试仪获得高速电路的高速统计特征。该方法和系统还包括将高速电路的高速统计签名与预期签名进行比较。因此，可以确定高速电路是否在期望的参数内起作用。

5. 发明授权

US07295604B2 Method for determining jitter of a signal in a serial link and high speed serial link 有权
标题翻译：用于确定串行链路和高速串行链路中的信号抖动的方法
公开(公告)号：US07295604B2
公开(公告)日：2007-11-13
申请号：US10720974
申请日：2003-11-24
申请人： Hayden C. Cranford, Jr. , Marcel A. Kossel , Vernon R. Norman , Martin L. Schmatz
发明人： Hayden C. Cranford, Jr. , Marcel A. Kossel , Vernon R. Norman , Martin L. Schmatz
IPC分类号： H04B3/46
CPC分类号： H04L25/068 , H04B3/462 , H04L1/205
摘要： The method for determining jitter of a signal in a serial link according to the invention comprising the following steps: First, a section of the signal transmitted via a transmission channel is sampled at different sampling times. The total number of edges in the section is determined. The neighboring sample values are analyzed and from that a statistical value is formed. From the statistical value and the total number of edges a figure of merit is determined. Finally, by means of a look-up table or a jitter-versus-figure of merit curve, the total jitter corresponding to the figure of merit is derived.
摘要翻译：根据本发明的用于确定串行链路中的信号的抖动的方法包括以下步骤：首先，经由传输信道发送的信号的一部分在不同的采样时间被采样。确定该部分中的边缘总数。分析相邻的样本值，并从中形成统计值。从统计值和边缘总数确定品质因数。最后，通过查询表或优点曲线的抖动对数值，推导出与品质因数对应的总抖动。

6. 发明授权

US5142530A Multi-frame stripping protocol for token ring networks 失效
标题翻译：多功能吊环网络协议
公开(公告)号：US5142530A
公开(公告)日：1992-08-25
申请号：US422168
申请日：1989-10-16
申请人： Joel E. Geyer , Joseph K. Lee , Vernon R. Norman , Kenneth T. Wilson
发明人： Joel E. Geyer , Joseph K. Lee , Vernon R. Norman , Kenneth T. Wilson
IPC分类号： H04L12/433
CPC分类号： H04L12/433
摘要： A multi-frame stripping method for use in a token ring network utilizing early token release with multiple frames transmitted by multiple stations circulating around the ring. The method recovers the ring with minimum loss of data after detection of an error condition resulting in frame corruption. The transmitting station is responsible for removing its own frames from the ring. With one or more of its frames corrupted, a station terminates frame removal after the transmitter has finished transmitting when a frame is received from another station without code violation errors in the frame header if the frame counter has returned to its initial value. The station terminates stripping when only a single frame is transmitted and then becomes corrupted if an isolated ending delimiter is detected at the station. The station also terminates stripping in the multi-frame case when the ending delimiter of the last frame transmitted by the source station is received without code violation error in the I-bit, if each preceding ending delimiter is correctly detected regardless of data corruption occurring in any frame header. The method is applicable to the IEEE 802.5 and ANSI X3T9.5 (FDDI) standards.

7. 发明授权

US07698802B2 Method for manufacturing a calibration device 失效
标题翻译：校准装置的制造方法
公开(公告)号：US07698802B2
公开(公告)日：2010-04-20
申请号：US12028439
申请日：2008-02-08
申请人： Steven M. Clements , William P. Cornwell , Carrie E. Cox , Hayden C. Cranford, Jr. , Vernon R. Norman
发明人： Steven M. Clements , William P. Cornwell , Carrie E. Cox , Hayden C. Cranford, Jr. , Vernon R. Norman
IPC分类号： G01R31/28
CPC分类号： G01R35/007 , Y10T29/49004 , Y10T29/4913 , Y10T29/49147 , Y10T29/49155 , Y10T29/49169 , Y10T29/49174
摘要： A method for manufacturing a calibration device for an active circuit on a chip, comprises: providing an active circuit that is capable of exhibiting a desired electrical characteristic; and providing a calibration mechanism on-chip with the active circuit. The calibration mechanism generates a control output and comprises a device under test (DUT) configured as a replica of at least one segment of the active circuit, and which generates a test output that causes finite adjustments to the control output, based on a comparison of the electrical characteristics exhibited by the DUT with a known electrical characteristic. The method further comprises: attaching to each control input terminal of the active circuit a corresponding control output from the calibration mechanism. The control output of the calibration mechanism dynamically adjusts control input applied to devices of the active circuit to force the active circuit to exhibit the desired electrical characteristic.
摘要翻译：一种用于制造芯片上的有源电路的校准装置的方法，包括：提供能够呈现所需电特性的有源电路; 并且提供与有源电路片上的校准机制。所述校准机构产生控制输出，并且包括被配置为所述有源电路的至少一个段的复制品的被测器件（DUT），并且基于所述被测器件的比较，产生对所述控制输出进行有限调整的测试输出具有已知电特性的DUT所呈现的电特性。该方法还包括：将有源电路的每个控制输入端连接到校准机构的相应控制输出。校准机构的控制输出动态调整施加到有源电路的器件的控制输入，以迫使有源电路呈现所需的电特性。

8. 发明授权

US07418069B2 Clock data recovering system with external early/late input 有权
标题翻译：具有外部早/晚输入的时钟数据恢复系统
公开(公告)号：US07418069B2
公开(公告)日：2008-08-26
申请号：US11966438
申请日：2007-12-28
申请人： Martin Schmatz , Hayden C. Cranford , Vernon R. Norman
发明人： Martin Schmatz , Hayden C. Cranford , Vernon R. Norman
IPC分类号： H04L7/00
CPC分类号： H03L7/091 , H03L7/0814 , H03L7/089 , H04L7/0331
摘要： The invention is directed to a clock data recovery system for resampling a clock signal according to an incoming data signal. The clock data recovery system comprises a clock generator for generating the clock signal and a phase adjustment unit for generating sampling phases dependent on a phase adjustment control signal. It also comprises a data sampling unit operable to generate a stream of input samples and an edge detector for generating therefrom an internal early signal and an internal late signal. A phase adjustment control unit is disposed for generating under use of the early signal and the late signal the phase adjustment control signal. The phase adjustment control unit is feedable with an external early/late signal and/or comprises an output for delivering an export early/late signal.
摘要翻译：本发明涉及一种用于根据输入数据信号重新采样时钟信号的时钟数据恢复系统。时钟数据恢复系统包括用于产生时钟信号的时钟发生器和用于根据相位调整控制信号产生采样相位的相位调整单元。它还包括可操作以产生输入样本流的数据采样单元和用于从其产生内部早期信号和内部迟滞信号的边缘检测器。设置相位调整控制单元，用于在早期信号的使用下产生相位调整控制信号，并且延迟信号。相位调整控制单元可以用外部早/晚信号进给，和/或包括用于传送出口早/晚信号的输出。

9. 发明授权

US07349498B2 Method and system for data and edge detection with correlation tables 有权
标题翻译：具有相关表的数据和边缘检测方法和系统
公开(公告)号：US07349498B2
公开(公告)日：2008-03-25
申请号：US10265981
申请日：2002-10-07
申请人： Hayden C Cranford, Jr. , Vernon R. Norman , Martin L. Schmatz
发明人： Hayden C Cranford, Jr. , Vernon R. Norman , Martin L. Schmatz
IPC分类号： H04L27/06 , H03D27/06
CPC分类号： H04L7/0338 , H03K5/1534
摘要： A system and method is disclosed for evaluating a data group of oversampled bits to detect edge transitions and for improving use of information available from a sampled data while maintaining acceptable noise rejection. An edge detection system for receiving a serial data stream includes a sampler for collecting a sample pattern from the serial data stream, the sample pattern including a succession of a plurality of data samples from the data stream with the plurality of data samples including multiple samples during a bit time associated with the data stream; a memory, coupled to the sampler, for storing one or more successive sample patterns; and a correlator, coupled to the memory, for producing a sample condition signal using a set of predefined patterns by comparing the stored sampled patterns to the predefined patterns.
摘要翻译：公开了一种系统和方法，用于评估过采样比特的数据组以检测边缘转换并改善对采样数据可用信息的使用，同时保持可接受的噪声抑制。用于接收串行数据流的边缘检测系统包括：采样器，用于从串行数据流收集采样模式，样本模式包括来自数据流的多个数据样本的一系列，其中多个数据样本包括多个样本与数据流相关联的一段时间; 耦合到采样器的存储器，用于存储一个或多个连续的采样图案; 以及耦合到存储器的相关器，用于通过将所存储的采样图案与预定义图案进行比较，使用一组预定义图案来产生采样条件信号。

10. 发明授权

US07149269B2 Receiver for clock and data recovery and method for calibrating sampling phases in a receiver for clock and data recovery 失效
标题翻译：用于时钟和数据恢复的接收器以及用于校准接收机中的采样相位以用于时钟和数据恢复的方法
公开(公告)号：US07149269B2
公开(公告)日：2006-12-12
申请号：US10375286
申请日：2003-02-27
申请人： Hayden C. Cranford, Jr. , Vernon R. Norman , Martin Schmatz
发明人： Hayden C. Cranford, Jr. , Vernon R. Norman , Martin Schmatz
IPC分类号： H03D3/24
CPC分类号： H03L7/07 , H03L7/091 , H03L7/0998 , H04L7/0025 , H04L7/0337
摘要： A receiver for clock and data recovery includes n sampling latches (SL1 . . . SLn) for determining n sample values (SV1 . . . SVn) of a reference signal (Ref2) at n sampling phases (φ1a . . . (φna) having sampling latch inputs and sampling latch outputs. The receiver further includes a phase position analyzer (5) connected to the sampling latch outputs for generating an adjusting signal (AS) for adjusting the sampling phase (φ1a . . . φna), if the sample value (SV1 . . . SVn) deviates from a set point and a phase interpolator (9) for generating sampling phases (φ1u . . . φnu). A sampling phase adjusting unit (6) connected with its inputs to the phase position analyzer (5) and the phase interpolator (9) and with its outputs to the sampling latches (SL1 . . . SLn) is provided for generating adjusted sampling phases (φ1a . . . φna) depending on the sampling phases (φ1u . . . φnu) and said adjusting signal (AS).
摘要翻译：用于时钟和数据恢复的接收机包括n个采样锁存器（SL1 ... SLn），用于确定n个采样相位（参见图1a）上的参考信号（Ref 2）的n个采样值（SV1 ... SVn）。（phina）具有采样锁存输入和采样锁存输出，接收器还包括连接到采样锁存器输出的相位位置分析器（5），用于产生调整信号（AS），用于调整采样相位（phi 1 a。如果采样值（SV1 ... SVn）偏离设定点，则产生采样相位（phi 1 u。。phinu）的相位插值器（9），连接的采样相位调整单元（6）其相位位置分析器（5）和相位插值器（9）的输入及其对采样锁存器（SL1 ... SLn）的输出被提供用于产生经调整的采样相位（phi1，...）取决于采样相位（phi 1 u。。phinu）和所述调整信号（AS）。

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