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51. 发明授权

US06891227B2 Self-aligned nanotube field effect transistor and method of fabricating same 有权
公开(公告)号：US06891227B2
公开(公告)日：2005-05-10
申请号：US10102365
申请日：2002-03-20
申请人： Joerg Appenzeller , Phaedon Avouris , Kevin K. Chan , Richard Martel , Hon-Sum Philip Wong , Philip G. Collins
发明人： Joerg Appenzeller , Phaedon Avouris , Kevin K. Chan , Richard Martel , Hon-Sum Philip Wong , Philip G. Collins
IPC分类号： H01L51/00 , H01L51/05 , H01L51/30 , H01L29/76 , H01L29/06 , H01L29/94
CPC分类号： H01L51/0516 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L51/0048 , H01L51/0052 , H01L51/0545 , Y10S977/842 , Y10S977/938 , Y10S977/94
摘要： A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the carbon-nanotube, respectively, and a gate formed substantially over a portion of the carbon-nanotube, separated from the carbon-nanotube by a dielectric film.

52. 发明授权

US06444578B1 Self-aligned silicide process for reduction of Si consumption in shallow junction and thin SOI electronic devices 有权
标题翻译：用于减少浅结和薄SOI电子器件中Si消耗的自对准硅化物工艺
公开(公告)号：US06444578B1
公开(公告)日：2002-09-03
申请号：US09791024
申请日：2001-02-21
申请人： Cyril Cabral, Jr. , Roy Arthur Carruthers , Kevin K. Chan , Guy M. Cohen , Kathryn Wilder Guarini , James M. Harper , Christian Lavoie , Paul M. Solomon
发明人： Cyril Cabral, Jr. , Roy Arthur Carruthers , Kevin K. Chan , Guy M. Cohen , Kathryn Wilder Guarini , James M. Harper , Christian Lavoie , Paul M. Solomon
IPC分类号： H01L2144
CPC分类号： H01L21/28518
摘要： The present invention relates to a method of reducing Si consumption during a self-aligned silicide process which employs a M—Si or M—Si—Ge alloy, where M is Co, Ni or CoNi and a blanket layer of Si. The present invention is particularly useful in minimizing Si consumption in shallow junction and thin silicon-on-insulator (SOI) electronic devices.
摘要翻译：本发明涉及在采用M-Si或M-Si-Ge合金的自对准硅化物工艺中降低Si消耗的方法，其中M是Co，Ni或CoNi以及Si的覆盖层。本发明特别可用于最大限度地减少浅结和薄绝缘体上硅（SOI）电子器件中的Si消耗。

53. 发明授权

US06238737B1 Method for protecting refractory metal thin film requiring high temperature processing in an oxidizing atmosphere and structure formed thereby 失效
$Method for protecting refractory metal thin film requiring high temperature processing in an oxidizing atmosphere and structure formed thereby$
标题翻译：用于保护在氧化气氛中需要高温处理的难熔金属薄膜和由此形成的结构的方法
公开(公告)号：US06238737B1
公开(公告)日：2001-05-29
申请号：US09337550
申请日：1999-06-22
申请人： Kevin K. Chan , Erin C. Jones , Fenton R. McFeely , Paul M. Solomon , John J. Yurkas
发明人： Kevin K. Chan , Erin C. Jones , Fenton R. McFeely , Paul M. Solomon , John J. Yurkas
IPC分类号： C23C1634
CPC分类号： C23C16/56 , H01L21/28008 , H01L21/32053 , H01L21/3211 , H01L29/4908 , Y10T428/12576 , Y10T428/12583 , Y10T428/12674 , Y10T428/1284 , Y10T428/265
摘要： A method of treating structures (and the structure formed thereby), so as to prevent or retard the oxidation of a metal film, and/or prevent its delamination a substrate, includes providing a structure including a refractory metal film formed on a substrate, placing the structure into a vessel having a base pressure below approximately 10−7 torr, exposing the structure to a silane gas at a sufficiently high predetermined temperature and predetermined pressure to cause formation of a metal silicide layer on the refractory metal film, and exposing the structure to a second gas at a sufficiently high temperature and pressure to nitride the metal silicide layer into a nitrided layer.
摘要翻译：一种处理结构（及其形成的结构）的方法，以防止或延缓金属膜的氧化和/或防止其基板的分层，包括提供包括在基板上形成的难熔金属膜的结构，将将结构转换成基本压力低于约10 -7乇的容器，将结构暴露于足够高的预定温度和预定压力下的硅烷气体，以在难熔金属膜上形成金属硅化物层，并使结构暴露以足够高的温度和压力将第二气体氮化成氮化层。

54. 发明授权

US5634973A Low temperature selective growth of silicon or silicon alloys 失效
标题翻译：硅或硅合金的低温选择性生长
公开(公告)号：US5634973A
公开(公告)日：1997-06-03
申请号：US587029
申请日：1996-01-16
申请人： Cyril Cabral, Jr. , Kevin K. Chan , Jack O. Chu , James M. E. Harper
发明人： Cyril Cabral, Jr. , Kevin K. Chan , Jack O. Chu , James M. E. Harper
IPC分类号： C30B29/06 , C23C14/08 , C23C16/04 , H01L21/20 , H01L21/203 , H01L21/205 , C30B33/06
CPC分类号： H01L21/02642 , H01L21/02373 , H01L21/02488 , H01L21/02532 , H01L21/02631 , Y10S148/106 , Y10S438/945
摘要： Epitaxial and polycrystalline layers of silicon and silicon-germanium alloys are selectively grown on a semiconductor substrate or wafer by forming over the wafer a thin film masking layer of an oxide of an element selected from scandium, yttrium, lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium; and then growing the epitaxial layer over the wafer at temperatures below 650.degree. C. The epitaxial and polycrystalline layers do not grow on the masking layer. The invention overcomes the problem of forming epitaxial layers at temperatures above 650.degree. C. by providing a lower temperature process.
摘要翻译：通过在晶片上形成选自钪，钇，镧，铈，镨，钕，钕，钕等的元素的氧化物的薄膜掩蔽层，选择性地在半导体衬底或晶片上生长硅和硅 - 锗合金的外延和多晶层，钐，铕，钆，铽，镝，钬，铒，ium，镱和镥; 然后在低于650℃的温度下在晶片上生长外延层。外延层和多晶层不会在掩模层上生长。本发明克服了通过提供较低温度的工艺在高于650℃的温度下形成外延层的问题。

55. 发明授权

US5595600A Low temperature selective growth of silicon or silicon alloys 失效
公开(公告)号：US5595600A
公开(公告)日：1997-01-21
申请号：US469650
申请日：1995-06-06
申请人： Cyril Cabral, Jr. , Kevin K. Chan , Jack O. Chu , James M. E. Harper
发明人： Cyril Cabral, Jr. , Kevin K. Chan , Jack O. Chu , James M. E. Harper
IPC分类号： C30B29/06 , C23C14/08 , C23C16/04 , H01L21/20 , H01L21/203 , H01L21/205
CPC分类号： H01L21/02642 , H01L21/02373 , H01L21/02488 , H01L21/02532 , H01L21/02631 , Y10S148/106 , Y10S438/945
摘要： Epitaxial and polycrystalline layers of silicon and silicon-germanium alloys are selectively grown on a semiconductor substrate or wafer by forming over the wafer a thin film masking layer of an oxide of an element selected from scandium, yttrium, lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium; and then growing the epitaxial layer over the wafer at temperatures below 650.degree. C. The epitaxial and polycrystalline layers do not grow on the masking layer. The invention overcomes the problem of forming epitaxial layers at temperatures above 650.degree. C. by providing a lower temperature process.

56. 发明授权

US08492794B2 Vertical polysilicon-germanium heterojunction bipolar transistor 有权
公开(公告)号：US08492794B2
公开(公告)日：2013-07-23
申请号：US13048366
申请日：2011-03-15
申请人： Jin Cai , Kevin K. Chan , Wilfried E. Haensch , Tak H. Ning
发明人： Jin Cai , Kevin K. Chan , Wilfried E. Haensch , Tak H. Ning
IPC分类号： H01L29/66
CPC分类号： H01L29/737 , H01L21/76229 , H01L29/0649 , H01L29/0821 , H01L29/165 , H01L29/66242 , H01L29/7375
摘要： A vertical heterojunction bipolar transistor (HBT) includes doped polysilicon having a doping of a first conductivity type as a wide-gap-emitter with an energy bandgap of about 1.12 eV and doped single crystalline Ge having a doping of the second conductivity type as the base having the energy bandgap of about 0.66 eV. Doped single crystalline Ge having of doping of the first conductivity type is employed as the collector. Because the base and the collector include the same semiconductor material, i.e., Ge, having the same lattice constant, there is no lattice mismatch issue between the collector and the base. Further, because the emitter is polycrystalline and the base is single crystalline, there is no lattice mismatch issue between the base and the emitter.

57. 发明申请

US20120228611A1 BIPOLAR JUNCTION TRANSISTOR WITH A SELF-ALIGNED EMITTER AND BASE 有权
标题翻译：具有自对准发射器和基极的双极性JUNCTION TRANSISTOR
公开(公告)号：US20120228611A1
公开(公告)日：2012-09-13
申请号：US13042902
申请日：2011-03-08
申请人： Kevin K. Chan , Erik M. Dahlstrom , Peter B. Gray , David L. Harame , Qizhi Liu
发明人： Kevin K. Chan , Erik M. Dahlstrom , Peter B. Gray , David L. Harame , Qizhi Liu
IPC分类号： H01L29/73 , H01L21/331
CPC分类号： H01L29/73 , H01L21/28518 , H01L29/0821 , H01L29/66272 , H01L29/732 , H01L29/7378
摘要： Methods for fabricating bipolar junction transistors with self-aligned emitter and extrinsic base, bipolar junction transistors made by the methods, and design structures for a BiCMOS integrated circuit. The bipolar junction transistor is fabricated using a sacrificial emitter pedestal that provides a sacrificial mandrel promoting self-alignment between the emitter and the extrinsic base. The sacrificial emitter pedestal is subsequently removed to open an emitter window extending to the intrinsic base. An emitter is formed in the emitter window that lands on the intrinsic base.
摘要翻译：用于制造具有自对准发射极和非本征基极的双极结型晶体管的方法，通过该方法制造的双极结型晶体管以及用于BiCMOS集成电路的设计结构。使用牺牲发射器基座制造双极结型晶体管，该牺牲发射器基座提供牺牲的心轴，以促进发射极和外部基极之间的自对准。随后去除牺牲发射器基座以打开延伸到本征基底的发射器窗口。在发射器窗口中形成发射极，其位于本征基极上。

58. 发明申请

US20120142158A1 Self-Aligned Nanotube Field Effect Transistor and Method of Fabricating Same 有权
标题翻译：自对准纳米管场效应晶体管及其制造方法
公开(公告)号：US20120142158A1
公开(公告)日：2012-06-07
申请号：US13368901
申请日：2012-02-08
申请人： Joerg Appenzeller , Phaedon Avouris , Kevin K. Chan , Philip G. Collins , Richard Martel , Hon-Sum Philip Wong
发明人： Joerg Appenzeller , Phaedon Avouris , Kevin K. Chan , Philip G. Collins , Richard Martel , Hon-Sum Philip Wong
IPC分类号： H01L21/336 , B82Y40/00
CPC分类号： H01L51/0516 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L51/0048 , H01L51/0052 , H01L51/0545 , Y10S977/842 , Y10S977/938 , Y10S977/94
摘要： A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the carbon-nanotube, respectively, and a gate formed substantially over a portion of the carbon-nanotube, separated from the carbon-nanotube by a dielectric film.
摘要翻译：自对准碳纳米管场效应晶体管半导体器件分别包括沉积在基板上的碳纳米管，分别形成在碳纳米管的第一端和第二端的源极和漏极，以及基本上形成的栅极碳纳米管的一部分，通过电介质膜与碳纳米管分离。

59. 发明申请

US20120139009A1 SOI SiGe-Base Lateral Bipolar Junction Transistor 有权
标题翻译： SOI SiGe-Base侧向双极结晶体管
公开(公告)号：US20120139009A1
公开(公告)日：2012-06-07
申请号：US12958647
申请日：2010-12-02
申请人： Tak H. Ning , Kevin K. Chan , Marwan H. Khater
发明人： Tak H. Ning , Kevin K. Chan , Marwan H. Khater
IPC分类号： H01L29/737 , H01L21/8222
CPC分类号： H01L29/7317 , H01L27/0821 , H01L27/1203 , H01L29/0808 , H01L29/165 , H01L29/66265
摘要： A lateral heterojunction bipolar transistor (HBT) is formed on a semiconductor-on-insulator substrate. The HBT includes a base including a doped silicon-germanium alloy base region, an emitter including doped silicon and laterally contacting the base, and a collector including doped silicon and laterally contacting the base. Because the collector current is channeled through the doped silicon-germanium base region, the HBT can accommodate a greater current density than a comparable bipolar transistor employing a silicon channel. The base may also include an upper silicon base region and/or a lower silicon base region. In this case, the collector current is concentrated in the doped silicon-germanium base region, thereby minimizing noise introduced to carrier scattering at the periphery of the base. Further, parasitic capacitance is minimized because the emitter-base junction area is the same as the collector-base junction area.
摘要翻译：在绝缘体上半导体衬底上形成横向异质结双极晶体管（HBT）。 HBT包括基底，其包括掺杂的硅 - 锗合金基底区域，包括掺杂硅并且横向接触基底的发射体，以及包括掺杂硅并且横向接触基底的收集器。因为集电极电流被引导通过掺杂的硅 - 锗基区，所以与使用硅沟道的可比较的双极晶体管相比，HBT可以容纳更大的电流密度。基底还可以包括上硅基区和/或下硅基区。在这种情况下，集电极电流集中在掺杂的硅 - 锗基区域中，从而最小化引入到基极周边的载流子散射的噪声。此外，寄生电容被最小化，因为发射极 - 基极结面积与集电极 - 基极结面积相同。

60. 发明授权

US07955928B2 Structure and method of fabricating FinFET 有权
标题翻译： FinFET的结构和方法
公开(公告)号：US07955928B2
公开(公告)日：2011-06-07
申请号：US12413836
申请日：2009-03-30
申请人： Kevin K. Chan , Zhibin Ren , Xinhui Wang
发明人： Kevin K. Chan , Zhibin Ren , Xinhui Wang
IPC分类号： H01L21/8242
CPC分类号： H01L21/823821 , H01L29/66803
摘要： A CMOS FinFET device and a method of manufacturing the same using a three dimensional doping process is provided. The method of forming the CMOS FinFET includes forming fins on a first side and a second side of a structure and forming spacers of a dopant material having a first dopant type on the fins on the first side of the structure. The method further includes annealing the dopant material such that the first dopant type diffuses into the fins on the first side of the structure. The method further includes protecting the first dopant type from diffusing into the fins on the second side of the structure during the annealing.
摘要翻译：提供了一种使用三维掺杂工艺的CMOS FinFET器件及其制造方法。形成CMOS FinFET的方法包括在结构的第一侧和第二侧上形成翅片，并且在结构的第一侧的翅片上形成具有第一掺杂剂类型的掺杂剂材料的间隔物。该方法还包括退火掺杂剂材料，使得第一掺杂剂类型扩散到结构的第一侧上的翅片。该方法还包括在退火期间保护第一掺杂剂类型不扩散到结构的第二侧上的翅片。

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