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51. 发明申请

US20120090298A1 ENGINE COMBUSTION CONDITION AND EMISSION CONTROLS 审中-公开
标题翻译：发动机燃烧条件和排放控制
公开(公告)号：US20120090298A1
公开(公告)日：2012-04-19
申请号：US13271096
申请日：2011-10-11
申请人： James M. Cleeves
发明人： James M. Cleeves
IPC分类号： F01N3/24 , B23P17/00 , B23P17/04 , F01N3/00
CPC分类号： F02D9/02 , F01N3/005 , F01N3/2821 , F01N2330/36 , F01N2330/38 , F01N2330/48 , F02B25/06 , F02B25/08 , F02M25/03 , Y02T10/121 , Y02T10/20 , Y10T29/49345 , Y10T29/49398
摘要： Features relating to engine efficiency and emissions controls are described. Systems, methods, articles or manufacture and the like can include features relating to integrated muffler and emissions controls for engine exhaust, water-injected internal combustion engine with an asymmetric compression and expansion ratio, controlled combustion durations for HCCI engines, piston shrouding of sleeve valves, low element count bearings, improved ports, and premixing of fuel and exhaust.
摘要翻译：描述了与发动机效率和排放控制相关的特征。系统，方法，制品或制造等可以包括与用于发动机排气的综合消声器和排放控制有关的特征，具有不对称压缩和膨胀比的注水内燃机，HCCI发动机的受控燃烧持续时间，套筒阀的活塞罩，低元素数轴承，改进的端口以及燃料和排气的预混合。

52. 发明申请

US20110220058A1 OVER-COMPRESSED ENGINE 失效
标题翻译：超压发动机
公开(公告)号：US20110220058A1
公开(公告)日：2011-09-15
申请号：US12720457
申请日：2010-03-09
申请人： James M. Cleeves , Nicholas Manov , Michael A. Willcox , Simon David Jackson
发明人： James M. Cleeves , Nicholas Manov , Michael A. Willcox , Simon David Jackson
IPC分类号： F02B17/00 , B21K3/00
CPC分类号： F02P5/1502 , F01L1/182 , F01L3/18 , F01L2001/054 , F02B25/08 , F02B31/02 , F02B75/282 , F02D15/00 , F02D35/027 , F02D41/3011 , F02D41/3017 , F02D2041/0015 , Y02T10/12 , Y02T10/146 , Y02T10/46 , Y10T29/49231
摘要： A system and method are disclosed for fabricating and running an engine in two modes. The first mode is an efficiency mode having a high compression ratio and efficiency for low to medium loads. The second mode is a power mode having high power density for higher loads. The system may use a lean mixture in the efficiency mode, which mixture is made richer for more power in the power mode. The system may also use ignition timing to allow the efficiency mode and the high power mode to be at the same mixture.
摘要翻译：公开了用于以两种模式制造和运行发动机的系统和方法。第一模式是对于中低负载具有高压缩比和效率的效率模式。第二种模式是对较高负载具有高功率密度的功率模式。该系统可以在效率模式下使用贫混合物，该混合物在功率模式下更加丰富，以获得更多功率。系统还可以使用点火正时以使效率模式和高功率模式处于相同的混合状态。

53. 发明申请

US20110156044A1 DENSE ARRAYS AND CHARGE STORAGE DEVICES 审中-公开
标题翻译：渗透阵列和充电存储设备
公开(公告)号：US20110156044A1
公开(公告)日：2011-06-30
申请号：US13027113
申请日：2011-02-14
申请人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Andrew J. Walker , Christopher J. Petti , Igor G. Kouznetzov , Mark G. Johnson , Paul Michael Farmwald , Brad Herner
发明人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Andrew J. Walker , Christopher J. Petti , Igor G. Kouznetzov , Mark G. Johnson , Paul Michael Farmwald , Brad Herner
IPC分类号： H01L29/786 , H01L29/78
CPC分类号： H01L27/11582 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C2211/5612 , H01L21/31053 , H01L21/76819 , H01L21/8221 , H01L23/528 , H01L23/5329 , H01L27/0688 , H01L27/112 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/11558 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L27/11578 , H01L27/1158 , H01L27/12 , H01L27/1203 , H01L29/0626 , H01L29/0661 , H01L29/16 , H01L29/1604 , H01L29/42324 , H01L29/42332 , H01L29/42364 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/7391 , H01L29/78642 , H01L29/7881 , H01L29/7889 , H01L29/792 , H01L29/7926 , H01L29/861 , H01L29/8616
摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.
摘要翻译：提供了一种包括多个器件级的电荷存储器件的单片三维阵列，其中通过化学机械抛光将两个连续的器件级之间的至少一个表面平坦化。

54. 发明申请

US20110041799A1 High Swirl Engine 有权
标题翻译：高旋涡发动机
公开(公告)号：US20110041799A1
公开(公告)日：2011-02-24
申请号：US12860061
申请日：2010-08-20
申请人： James M. Cleeves , Simon D. Jackson , Michael A. Willcox
发明人： James M. Cleeves , Simon D. Jackson , Michael A. Willcox
IPC分类号： F02F3/24
CPC分类号： F02B75/28 , F02B1/02 , F02B25/08 , F02B31/06 , F02F1/186 , F02M35/10262 , Y02T10/12 , Y02T10/146
摘要： An internal combustion engine can include a combustion volume within a cylinder of an internal combustion engine. The combustion volume can be defined at least by a cylinder wall and a first piston in the cylinder. A swirl port can deliver a fluid into the combustion volume via a swirl port outlet such that the delivered fluid is directed around a periphery of the cylinder with a fluid velocity disposed at a predetermined angle away from tangential to a curve of the cylinder wall to generate a swirling motion in the combustion volume.
摘要翻译：内燃机可以包括在内燃机的汽缸内的燃烧量。燃烧体积可以至少由气缸壁和气缸中的第一活塞限定。旋流口可以通过旋流口出口将流体输送到燃烧体积中，使得输送的流体以围绕圆筒壁的切线的预定角度设置的流体速度定向在圆筒的周边上，从而产生在燃烧体积中的旋转运动。

55. 发明授权

US07816188B2 Process for fabricating a dielectric film using plasma oxidation 有权
标题翻译：使用等离子体氧化制造电介质膜的工艺
公开(公告)号：US07816188B2
公开(公告)日：2010-10-19
申请号：US09918853
申请日：2001-07-30
申请人： Michael A. Vyvoda , N. Johan Knall , James M. Cleeves
发明人： Michael A. Vyvoda , N. Johan Knall , James M. Cleeves
IPC分类号： H01L21/00
CPC分类号： H01L27/11206 , C23C8/36 , H01L21/32105 , H01L23/5252 , H01L27/112 , H01L2924/0002 , H01L2924/00
摘要： A high density plasma oxidation process is provided in which a dielectric film is formed having a predetermined thickness. Plasma oxidation conditions are provided such that the growth rate of the dielectric film is limited in order to produce dielectric layer having a precise thickness and uniformity. The high density plasma oxidation process can be used to fabricate gate oxide layers, passivation layers and antifuse layers in semiconductor devices such as semiconductor memory devices and multi-level memory arrays.
摘要翻译：提供了一种高密度等离子体氧化工艺，其中形成具有预定厚度的电介质膜。提供等离子体氧化条件使得电介质膜的生长速度受到限制，以便产生具有精确厚度和均匀性的电介质层。高密度等离子体氧化工艺可用于制造诸如半导体存储器件和多级存储器阵列的半导体器件中的栅极氧化物层，钝化层和反熔丝层。

56. 发明授权

US07768038B2 Post vertical interconnects formed with silicide etch stop and method of making 有权
标题翻译：后置垂直互连形成硅化物蚀刻停止和制造方法
公开(公告)号：US07768038B2
公开(公告)日：2010-08-03
申请号：US11849174
申请日：2007-08-31
申请人： James M. Cleeves
发明人： James M. Cleeves
IPC分类号： H01L23/48
CPC分类号： H01L27/11568 , H01L21/76885 , H01L27/105 , H01L27/115 , H01L27/11578
摘要： A method to form a vertical interconnect advantageous for high-density semiconductor devices. A conductive etch stop layer, preferably of cobalt silicide, is formed. The etch stop layer may be in the form of patterned lines or wires. A layer of contact material is formed on and in contact with the etch stop layer. The layer of contact material is patterned to form posts. Dielectric is deposited over and between the posts, then the dielectric planarized to expose the tops of the posts. The posts can serve as vertical interconnects which electrically connect a next conductive layer formed on and in contact with the vertical interconnects with the underlying etch stop layer. The patterned dimension of vertical interconnects formed according to the present disclosure can be substantially the same as the minimum feature size, even at very small minimum feature size.
摘要翻译：一种形成有利于高密度半导体器件的垂直互连的方法。形成优选硅化钴的导电蚀刻停止层。蚀刻停止层可以是图案化线或线的形式。接触材料层形成在蚀刻停止层上并与蚀刻停止层接触。图案化接触材料层以形成柱。电介质沉积在柱之间和之间，然后将电介质平坦化以暴露柱的顶部。柱可以用作垂直互连，其将形成在垂直互连上的下一个导电层与下面的蚀刻停止层电连接。根据本公开形成的垂直互连的图案化尺寸可以与最小特征尺寸基本相同，即使在非常小的最小特征尺寸。

57. 发明申请

US20080310231A1 OPTIMIZATION OF CRITICAL DIMENSIONS AND PITCH OF PATTERNED FEATURES IN AND ABOVE A SUBSTRATE 有权
标题翻译：关键尺寸的优化和基板上及以上图案特征的优化
公开(公告)号：US20080310231A1
公开(公告)日：2008-12-18
申请号：US12136766
申请日：2008-06-10
申请人： James M. Cleeves , Roy E. Scheuerlein
发明人： James M. Cleeves , Roy E. Scheuerlein
IPC分类号： G11C11/34 , H01L27/092
CPC分类号： H01L27/105 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A die is formed with different and optimized critical dimensions in different device levels and areas of those device levels using photolithography and etch techniques. One aspect of the invention provides for a memory array formed above a substrate, with driver circuitry formed in the substrate. A level of the memory array consists of, for example, parallel rails and a fan-out region. It is desirable to maximize density of the rails and minimize cost of lithography for the entire memory array. This can be achieved by forming the rails at a tighter pitch than the CMOS circuitry beneath it, allowing cheaper lithography tools to be used when forming the CMOS, and similarly by optimizing lithography and etch techniques for a device level to produce a tight pitch in the rails, and a more relaxed pitch in the less-critical fan-out region.
摘要翻译：在使用光刻和蚀刻技术的不同器件级别和那些器件级别的区域中，使用不同且优化的临界尺寸形成管芯。本发明的一个方面提供了形成在衬底上的存储器阵列，其中驱动电路形成在衬底中。存储器阵列的一个级别包括例如平行轨道和扇出区域。希望使轨道的密度最大化并最小化整个存储器阵列的光刻成本。这可以通过以比它下面的CMOS电路更紧的间距形成轨道来实现，从而允许在形成CMOS时使用更便宜的光刻工具，并且类似地通过优化用于器件级别的光刻和蚀刻技术以在轨道，并且在不太关键的扇出区域更放松。

58. 发明授权

US07423304B2 Optimization of critical dimensions and pitch of patterned features in and above a substrate 有权
标题翻译：优化衬底中和图案上的图案特征的临界尺寸和间距
公开(公告)号：US07423304B2
公开(公告)日：2008-09-09
申请号：US10728437
申请日：2003-12-05
申请人： James M. Cleeves , Roy E. Scheuerlein
发明人： James M. Cleeves , Roy E. Scheuerlein
IPC分类号： H01L29/80 , H01L31/112
CPC分类号： H01L27/105 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A die is formed with different and optimized critical dimensions in different device levels and areas of those device levels using photolithography and etch techniques. One aspect of the invention provides for a memory array formed above a substrate, with driver circuitry formed in the substrate. A level of the memory array consists of, for example, parallel rails and a fan-out region. It is desirable to maximize density of the rails and minimize cost of lithography for the entire memory array. This can be achieved by forming the rails at a tighter pitch than the CMOS circuitry beneath it, allowing cheaper lithography tools to be used when forming the CMOS, and similarly by optimizing lithography and etch techniques for a device level to produce a tight pitch in the rails, and a more relaxed pitch in the less-critical fan-out region.
摘要翻译：在使用光刻和蚀刻技术的不同器件级别和那些器件级别的区域中，使用不同且优化的临界尺寸形成管芯。本发明的一个方面提供了形成在衬底上的存储器阵列，其中驱动电路形成在衬底中。存储器阵列的一个级别包括例如平行轨道和扇出区域。希望使轨道的密度最大化并最小化整个存储器阵列的光刻成本。这可以通过以比它下面的CMOS电路更紧的间距形成轨道来实现，从而允许在形成CMOS时使用更便宜的光刻工具，并且类似地通过优化用于器件级别的光刻和蚀刻技术来产生紧密的间距轨道，并且在不太关键的扇出区域更放松。

59. 发明授权

US07158102B2 System and method for recalibrating flat panel field emission displays 有权
标题翻译：重新校准平板式场发射显示器的系统和方法
公开(公告)号：US07158102B2
公开(公告)日：2007-01-02
申请号：US10133161
申请日：2002-04-26
申请人： Ronald L. Hansen , James C. Dunphy , Christopher J. Spindt , James M. Cleeves , Jerome M. Truppa , Gregory M. Fink , Yukinobu Iguchi
发明人： Ronald L. Hansen , James C. Dunphy , Christopher J. Spindt , James M. Cleeves , Jerome M. Truppa , Gregory M. Fink , Yukinobu Iguchi
IPC分类号： G09G3/20 , G09G3/22
CPC分类号： G09G3/22 , G09G3/2011 , G09G3/2014 , G09G5/02 , G09G2310/06 , G09G2320/0285 , G09G2320/029 , Y10S345/904
摘要： A field emission display (FED) having a correction system with a correction coefficient derived from emission current is presented. Within one embodiment in accordance with the present invention, a field emission display has an anode at the faceplate and a focus structure. The anode potential is held at ground while the focus structure potential is held between, but is not limited to, 40 and 50 volts. The current flowing to the focus structure is measured and used as the basis for the correction coefficient for the field emission display.
摘要翻译：提出了具有从发射电流导出的校正系数的校正系统的场发射显示（FED）。在根据本发明的一个实施例中，场发射显示器在面板处具有阳极和聚焦结构。阳极电位保持在地，而聚焦结构电位保持在40和50伏之间，但不限于此。测量流向焦点结构的电流，并将其用作场发射显示的校正系数的基础。

60. 发明授权

US07129538B2 Dense arrays and charge storage devices 有权
公开(公告)号：US07129538B2
公开(公告)日：2006-10-31
申请号：US10842008
申请日：2004-05-10
申请人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Andrew J. Walker , Christopher Petti , Igor G. Kouznetzov , Mark G. Johnson , Paul M. Farmwald , Brad Herner
发明人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Andrew J. Walker , Christopher Petti , Igor G. Kouznetzov , Mark G. Johnson , Paul M. Farmwald , Brad Herner
IPC分类号： H01L29/788
CPC分类号： H01L27/11582 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C2211/5612 , H01L21/31053 , H01L21/76819 , H01L21/8221 , H01L23/528 , H01L23/5329 , H01L27/0688 , H01L27/112 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/11558 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L27/11578 , H01L27/1158 , H01L27/12 , H01L27/1203 , H01L29/0626 , H01L29/0661 , H01L29/16 , H01L29/1604 , H01L29/42324 , H01L29/42332 , H01L29/42364 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/7391 , H01L29/78642 , H01L29/7881 , H01L29/7889 , H01L29/792 , H01L29/7926 , H01L29/861 , H01L29/8616
摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

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