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51. 发明专利

JP2002118158A METHOD AND APPARATUS FOR INSPECTING CIRCUIT PATTERN 审中-公开
公开(公告)号：JP2002118158A
公开(公告)日：2002-04-19
申请号：JP2001210150
申请日：2001-07-11
申请人： HITACHI LTD
发明人： NOZOE MARI , SHINADA HIROYUKI , SUGIYAMA KATSUYA , TAKATO ATSUKO , HIROI TAKASHI , YOSHIMURA KAZUSHI , SUGIMOTO ARITOSHI , YODA HARUO , KURODA KATSUHIRO , USAMI YASUTSUGU , TANAKA MAKI , KANEKO YUTAKA , TOYAMA HIROSHI , INO TADAO , YAJIMA YUSUKE , ANDO MASAAKI , MAEDA SHUNJI , KUBOTA HITOSHI
IPC分类号： G01B15/00 , G01R31/02 , H01J37/20 , H01J37/28 , H01L21/027 , H01L21/66
摘要： PROBLEM TO BE SOLVED: To enable high-speed, stable, and accurate inspection of circuit pattern having insulating materials in a method for inspection by detecting a defect, contamination, residue, or the like appearing on the circuit pattern of a semiconductor-device wafer, by radiating an electron beam onto the wafer and comparing the secondary electron image with a reference image. SOLUTION: A high-current electron beam 19 is radiated only at one time or several times of short time duration onto the wafer 9 to be inspected to form an electron beam image before the electric potentials of the circuit pattern materials change. Besides, in addition to the first electron beam for forming the image for the inspection, a second charged-particle beam 104 is radiated beforehand onto the wafer 9 to be inspected to conduct the inspection after the condition of the electric potentials of the circuit pattern materials are stabilized. The secondary-electron detection signal is digitized and transferred to efficiently obtain a high-quality electron-beam image with a high S/N ratio.

52. 发明专利

JP2002043385A SEMICONDUCTOR WAFER HAVING TEST PATTERN, METHOD FOR INSPECTING SEMICONDUCTOR WAFER, METHOD FOR MANAGING MANUFACTURING PROCESS, AND METHOD FOR MANUFACTURING SEMICONDUCTOR 失效
公开(公告)号：JP2002043385A
公开(公告)日：2002-02-08
申请号：JP2000226859
申请日：2000-07-27
申请人： HITACHI LTD
发明人： TANAKA MAKI , WATANABE MASAHIRO , HIROI TAKASHI , SHISHIDO CHIE , KUNI TOMOHIRO , WATANABE KENJI , SUGIMOTO ARITOSHI , NOZOE MARI
IPC分类号： G01R31/28 , H01L21/66 , H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To provide a test pattern with which a circuit pattern can be inspected for defects with high sensitivity in a semiconductor manufacturing process, a method for detecting defect, and a method for managing manufacturing process both of which use the test pattern. SOLUTION: The variation of the misalignment amounts of an interlayer pattern is monitored from the occurring amounts of defects in the misalignment amounts of a plurality of test patterns having different misalignment amounts. Alternatively, defects such as short circuits, continuity defects, short circuits caused by foreign matters, etc., are detected by forming test patterns having different circuit patterns.

53. 发明专利

JP2001124713A DEVICE AND METHOD FOR INSPECTING CIRCUIT PATTERN 失效
公开(公告)号：JP2001124713A
公开(公告)日：2001-05-11
申请号：JP30497099
申请日：1999-10-27
申请人： HITACHI LTD
发明人： FUNATSU RYUICHI , SHINADA HIROYUKI , NINOMIYA HIROSHI , HIROI TAKASHI
IPC分类号： G01B15/00 , G01B15/04 , G01N23/225 , H01J37/04 , H01J37/22 , H01J37/244 , H01J37/28 , H01L21/66 , H05K3/00
摘要： PROBLEM TO BE SOLVED: To provide a device and method for inspecting a circuit pattern that can inspect the defect of the circuit pattern at high speed, and at the same time can observe the defect with high sensitivity. SOLUTION: A semiconductor detector is provided in a detector for inspecting a defect, and a photomultiplier is provided in a detector for observing the defect. Also, an E cross B deflector that can change the directions of electric and magnetic fields so that a secondary charged particle can be detected by one of the two detectors is provided.

54. 发明专利

JP2001035893A APPARATUS FOR INSPECTING CIRCUIT PATTERN 失效
公开(公告)号：JP2001035893A
公开(公告)日：2001-02-09
申请号：JP20874999
申请日：1999-07-23
申请人： HITACHI LTD
发明人： ITO MASANORI , MACHIDA KAZUHISA , NOZOE MARI , USAMI YASUTSUGU , HIROI TAKASHI , MORIOKA HIROSHI
IPC分类号： G01N21/88 , G01N21/956 , H01L21/66
摘要： PROBLEM TO BE SOLVED: To pick out process failure of a semiconductor device quickly by displaying a screen for designating an inspection region corresponding to a chip and an inspection result screen of a designated inspection region. SOLUTION: A region 1 is located at an upper part on a screen and a guidance region 2 describing the operation and state is located below. A region 3 located in the center of the screen comprises a screen 3a for designating the shelf number list of cassette and the inspection region of wafer, a screen 2b for inputting an inspection object or inspection conditions, and a screen 3c for displaying inspection conditions and inspection results wherein the contents to be displayed are changed depending on the operation or the state of progress. According to the arrangement, process failure of a semiconductor device can be picked up quickly.

55. 发明专利

JP2000099742A FAULT DETECTION METHOD AND DEVICE THEREFOR 失效
公开(公告)号：JP2000099742A
公开(公告)日：2000-04-07
申请号：JP26985899
申请日：1999-09-24
申请人： HITACHI LTD
发明人： HIROI TAKASHI , KUBOTA HITOSHI , MAEDA SHUNJI , MAKIHIRA HIROSHI
IPC分类号： G01B11/24 , G01N21/88 , G01N21/956 , G06T1/00 , G06T7/00 , H01L21/66
摘要： PROBLEM TO BE SOLVED: To reduce the influence of a sampling error by performing aligning the 1st and 2nd pattern images to each other with accuracy of pixel unit or smaller and detecting a pattern fault based on the amount of slippage between both pattern images which are aligned to each other. SOLUTION: Every part is initialized by a command given from a total control part 21 and then the pattern of a wafer 1 which is illuminated by a light source 3 and an illumination optical system 4 undergoes a photoelectric transduction by a one-dimensional image sensor 6 via an objective lens 5 and synchronously with the scanning of an XY stage 2 to detect a two-dimensional pattern, and made to a detection image 10 of a two-dimensional 1st pattern that is digitized by an A/D converter 7 and stored in an image memory part 8. An image extraction part 12 extracts a comparison image 11 of a 2nd pattern by referring to the address of the part 8. A matching part 13 performs the alignment between the images 10 and 11 with accuracy less than a pixel unit, and a fault detection part 19 detects the faults of patterns based on the amount of slippage between both pattern images.

56. 发明专利

JPH10340347A PATTERN INSPECTING METHOD, DEVICE THEREFOR AND PRODUCTION OF SEMICONDUCTOR WAFER 失效
公开(公告)号：JPH10340347A
公开(公告)日：1998-12-22
申请号：JP15065297
申请日：1997-06-09
申请人： HITACHI LTD
发明人： SHISHIDO CHIE , WATANABE MASAHIRO , HIROI TAKASHI , TANAKA MAKI , KUNI TOMOHIRO , SHINADA HIROYUKI , NOZOE MARI , SUGIMOTO ARITOSHI
IPC分类号： H01L21/66 , G06T1/00 , G06T7/00
摘要： PROBLEM TO BE SOLVED: To detect a defect through simple coordinate designation when inspecting an object having plural patterns while mixing a place having two-dimensional (2D) repeatedness with a section having repeatedness only in X and Y directions. SOLUTION: A concerned point 101 is compared with comparison objects at plural positions separated just for a repetition pitch such as 102a-d, for example, and only the section having differences at all the positions is extracted as a defect candidate. Thus, even a 2D repeated section or a place having repeatedness only in the X or Y direction can be checked. The section having no repeatedness in both the X and Y directions such as an isolate point is extracted as the defect candidate but when the defect candidate commonly occurs in plural objects, it is not defined as a defect. Thus, such candidates are extruded and a true defect is discriminated.

57. 发明专利

JPH10318950A METHOD AND APPARATUS FOR INSPECTION OF PATTERN 失效
公开(公告)号：JPH10318950A
公开(公告)日：1998-12-04
申请号：JP13146097
申请日：1997-05-21
申请人： HITACHI LTD
发明人： SHISHIDO CHIE , HIROI TAKASHI , YODA HARUO , WATANABE MASAHIRO , KUNI TOMOHIRO , TANAKA MAKI , NINOMIYA TAKANORI , DOI HIDEAKI , MAEDA SHUNJI , NOZOE MARI , SHINADA HIROYUKI , TAKATO ATSUKO , SUGIMOTO ARITOSHI , USAMI YASUTSUGU
IPC分类号： G01N23/20 , G01N21/88 , G01N21/956 , G01N23/225 , G06T1/00 , H01L21/66 , G06T7/00
摘要： PROBLEM TO BE SOLVED: To judge a defect candidate by setting a permissible range in accordance with a positional shift amount between designated area images of two second- dimensional images, obtaining a distance by a gradational value between partial images of the images, and comparing the distance with the permissible range. SOLUTION: Electrons are generated from an object 100 to be inspected through the scanning of electron beams 30, and detected by an electron detector 35. A detection signal is sent to an A/D converter 39 through an amplifier 36. An output of the A/D converter is delayed by a delay circuit 41 by, e.g. a movement time of one chip, whereby image signals of the same point of adjacent two chips are generated. The chips can hence be compared and inspected. Two second-dimensional images are registered per pixel unit at a registration part 42 per pixel unit, and a positional shift amount of not larger than one pixel of images is detected by a shift detection part 43. A distance of partial images of the images is obtained for every pixel at a differential extraction circuit 49. The distance is compared with a distance threshold value obtained at a threshold value operation circuit 48 for every pixel from the positional shift amount and a gradational value of the images. When the distance is not larger than the threshold value, the object is judged as a defect candidate.

58. 发明专利

JPH10253544A METHOD AND APPARATUS FOR VISUAL EXAMINATION 失效
公开(公告)号：JPH10253544A
公开(公告)日：1998-09-25
申请号：JP279398
申请日：1998-01-09
申请人： HITACHI LTD
发明人： TAKAGI YUJI , SHISHIDO CHIE , MAEDA SHUNJI , HIROI TAKASHI , TANAKA MAKI , KUNI TOMOHIRO , AZUMA JUNZO , MATSUYAMA YUKIO
IPC分类号： G01B11/30 , G01B15/04 , G01B15/08 , G01N21/88 , G01N21/93 , G01N21/956 , G01R31/302 , H01J37/22 , H01L21/66
摘要： PROBLEM TO BE SOLVED: To eliminate an erroneous detection by correcting uneven density and distortions of two images containing patterns which should be originally identical and comparing the both to detect and discriminate parts differing from each other as defects. SOLUTION: Images f (x, y) and g (x, y) from an image memory section are inputted by a roughly positioning circuit 21 to be roughly positioned. An uneven density correction circuit 22 receiving the results inputted corrects uneven density values of the patterns which should be originally identical and reduces any uneven density difference existing at parts without defect to such an extent that the difference can be recognized to be normal. Then, to remove effect by unsteady distortions of the images, positional deviations are corrected by a distortion correcting circuit 23 so that any distortion of the images will not be detected and discriminated as defects. The two images subjected to the correction of the distortions further undergoes a highly accurate positioning with a precisely positioning circuit 24. A density circuit 25 performs a comparison processing of the images thus finished with the correction of the uneven density and distortions and the positioning and any different part therebetween is detected and discriminated as defect. This eliminates erroneous detection, thereby enabling highly reliable detection of fine defects.

59. 发明专利

JPH1012684A METHOD AND EQUIPMENT FOR INSPECTING SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH1012684A
公开(公告)日：1998-01-16
申请号：JP16555096
申请日：1996-06-26
申请人： HITACHI LTD
发明人： TANAKA MAKI , HIROI TAKASHI , WATANABE MASAHIRO , KUNI TOMOHIRO , ITO FUMIKAZU , AZUMA JUNZO , SHIMASE AKIRA , OOGAYA KAORU
IPC分类号： G01B15/04 , G01N23/225 , G01R31/302 , H01L21/66
摘要： PROBLEM TO BE SOLVED: To provide an inspecting method using a scanning electron microscope and an equipment for it with which an electron beam which is stable extending over a long time is obtained for a sample without being affected by charging-up. SOLUTION: Charging-up is controlled by irradiating the surface of a sample wafer with an electron shower and an ion shower. Charging-up is controlled with a controlling calculator 20 according to an inspection condition and a material quality of the sample, etc. A stable electron beam image wherein a condition of charging-up does not charge is inputted with a secondary electron detector 15, and then compared/inspected at a picture processing part 19, to detect a defect of a semiconductor device. By this, an influence on the electron bean image due to charging-up of the surface of the sample is avoided, and a stable inspection extending over a long time is realized with the electron beam image. Further, by feeding an inspection result back to a semiconductor manufacturing process, a defective coefficient of the semiconductor device is reduced, and reliability is improved.

60. 发明专利

JPH07318326A APPARATUS AND METHOD FOR INSPECTION OF PATTERN 失效
公开(公告)号：JPH07318326A
公开(公告)日：1995-12-08
申请号：JP11620294
申请日：1994-05-30
申请人： HITACHI LTD
发明人： MAEDA SHUNJI , KUBOTA HITOSHI , HIROI TAKASHI , YOSHITAKE YASUHIRO , MAKIHIRA HIROSHI
IPC分类号： G01B11/24
摘要： PURPOSE:To provide a method and apparatus in which a minute circuit pattern is detected with high resolution. CONSTITUTION:By using a pupil 10 for an objective lens 9 or a means which detects the pupil via a lens forming an image in a position which is conjugate with it and by using image information detected by the means, the distribution of diffracted light, e.g. information on the distribution of zero-order diffracted light and + or - first-order diffracted light, is obtained, and ring-belt-shaped illumination is controlled in such a way that they are arranged inside an opening in a well-balanced manner. Zero-order light is obliquely incident on a wafer 1 by the ring-belt-shaped illumination, the zero-order diffracted light as reflected light and either + first-order diffracted light or-first-order diffracted light are taken into the opening of the objective lens 9, and sufficient resolution is obtained. In addition, the zero-order diffracted light as the reflected light and either the + first-order diffracted light or the-first-order diffracted light are balanced with reference to an optical axis so as to be capable of dealing with various circuit patterns.

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