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51. 发明授权

US06252299B1 Stacked semiconductor device including improved lead frame arrangement 有权
标题翻译：堆叠的半导体器件包括改进的引线框布置
公开(公告)号：US06252299B1
公开(公告)日：2001-06-26
申请号：US09161725
申请日：1998-09-29
申请人： Masachika Masuda , Tamaki Wada , Michiaki Sugiyama , Hirotaka Nishizawa , Toshio Sugano , Yasushi Takahashi , Masayasu Kawamura
发明人： Masachika Masuda , Tamaki Wada , Michiaki Sugiyama , Hirotaka Nishizawa , Toshio Sugano , Yasushi Takahashi , Masayasu Kawamura
IPC分类号： H01L2328
CPC分类号： H01L24/06 , H01L23/4951 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05554 , H01L2224/05599 , H01L2224/06136 , H01L2224/32145 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/4826 , H01L2224/48599 , H01L2224/49113 , H01L2224/49171 , H01L2224/73215 , H01L2224/85201 , H01L2224/85205 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01039 , H01L2924/01055 , H01L2924/01058 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/07802 , H01L2924/12042 , H01L2924/14 , H01L2924/181 , H01L2924/30105 , H01L2924/3011 , Y10T29/49121 , H01L2924/00 , H01L2924/00012 , H01L2224/85399
摘要： A semiconductor device comprising a resin mold, two semiconductor chips positioned inside the resin mold and having front and back surfaces and external terminals formed on the front surfaces, and leads extending from the inside to the outside of the resin mold, wherein each of said leads is branched into two branch leads in at least the resin mold, the one branch lead is secured to the surface of the one semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, the other branch lead is secured to the surface of the other semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, and the two semiconductor chips are stacked one upon the other, with their back surfaces opposed to each other.
摘要翻译：一种半导体器件，包括树脂模具，位于树脂模具内部的两个半导体芯片，具有形成在前表面上的前后表面和外部端子以及从树脂模具的内部延伸到外部的引线，其中每个所述引线至少在树脂模具中分支成两个分支引线，一个分支引线固定到一个半导体芯片的表面，并通过导线与表面上的外部端子电连接，另一个分支引线被固定到另一个半导体芯片的表面，并通过导线与表面上的外部端子电连接，并且两个半导体芯片彼此堆叠，并且它们的背面彼此相对。

52. 发明授权

US06169698A Voltage generating circuit for semiconductor memory sense amplifier 有权
标题翻译：半导体存储器读出放大器的电压产生电路
公开(公告)号：US06169698A
公开(公告)日：2001-01-02
申请号：US09189076
申请日：1998-11-09
申请人： Shunichi Sukegawa , Shinji Bessho , Masayuki Hira , Yasushi Takahashi , Tsutomu Takahashi , Koji Arai
发明人： Shunichi Sukegawa , Shinji Bessho , Masayuki Hira , Yasushi Takahashi , Tsutomu Takahashi , Koji Arai
IPC分类号： G11C700
CPC分类号： G11C5/063 , G11C5/143 , G11C5/147 , G11C7/06
摘要： Drop in the power supply level right after change can be suppressed greatly when changing the power to the internal power supply voltage from the external power supply voltage of an overdrive system. Voltage generating circuit VG0 is connected to the VDL line which raises the VDL line to a voltage higher than VDL beforehand prior to changing to internal power supply voltage VDL from external power supply voltage VDD, and restores the VDL line voltage which drops after the change to VDL. More specifically, there are detecting circuit part 40 which detects the VDL line potential, first switching element M1 connected between the VDL line and the VDD line and which operates according to the detected result of detecting circuit part 40, and second switching element M2 connected between common voltage VSS and connection node ND1 between first switching element M1 and detecting circuit part 40, which changes the potential of connection node ND1 by conducting according to input preliminary voltage step up signal MVDL, and by it conducts first switching element M1 for a fixed time.
摘要翻译：在从过驱动系统的外部电源电压改变内部电源电压的电源时，可以大幅度地抑制变更后的电源电平下降。在从外部电源电压VDD变为内部电源电压VDL之前，将电压生成电路VG0与VDL线连接，将VDL线预先升压至高于VDL的电压，并且将变更后降低的VDL线电压恢复为 VDL。更具体地，存在检测VDL线电位的检测电路部40，连接在VDL线与VDD线之间的第一开关元件M1，其根据检测电路部40的检测结果进行动作，第二开关元件M2连接在第一开关元件M1和检测电路部分40之间的公共电压VSS和连接节点ND1，其通过根据输入的初步升压信号MVDL进行导通来改变连接节点ND1的电位，并且通过其将第一开关元件M1导通固定时间。

53. 发明授权

US6031779A Dynamic memory 失效
标题翻译：动态内存
公开(公告)号：US6031779A
公开(公告)日：2000-02-29
申请号：US058147
申请日：1998-04-10
申请人： Yasushi Takahashi , Tsutomu Takahashi , Kouji Arai , Tsugio Takahashi , Shunichi Sukegawa , Shinji Bessho , Masayuki Hira
发明人： Yasushi Takahashi , Tsutomu Takahashi , Kouji Arai , Tsugio Takahashi , Shunichi Sukegawa , Shinji Bessho , Masayuki Hira
IPC分类号： G11C11/407 , G11C7/06 , G11C8/14 , G11C11/401 , G11C11/408 , G11C11/409 , G11C11/4091 , H01L21/8242 , H01L27/108 , G11C7/00
CPC分类号： G11C11/4091 , G11C11/408 , G11C7/06 , G11C8/14 , G11C2207/065
摘要： Described herein is a dynamic memory. An N channel type voltage clamp MOSFET is provided which has a drain supplied with a supply voltage supplied from an external terminal, a gate to which a boosted constant voltage is applied, and a source which outputs a constant voltage. The clamp voltage outputted from the source of the voltage clamp MOSFET is supplied to a common source line for each of P channel type amplification MOSFETs constituting a sense amplifier via a P channel type first power MOSFET switch-controlled by a sense amplifier activation signal, as a voltage for operating the sense amplifier. Further, the constant voltage outputted from the source of the voltage clamp MOSFET is supplied to an N-well region in which the P channel type first power MOSFET and the P channel type MOSFETs constituting the sense amplifier are formed, as a bias voltage.
摘要翻译：这里描述的是动态存储器。提供了一种N沟道型电压钳位MOSFET，其具有供给从外部端子提供的电源电压的漏极，施加升压恒定电压的栅极和输出恒定电压的源极。从电压钳位MOSFET的源极输出的钳位电压通过由读出放大器激活信号开关控制的P沟道型第一功率MOSFET构成读出放大器的每个P沟道型放大器MOSFET，被提供给公共源极线，如用于操作读出放大器的电压。此外，从电压钳位MOSFET的源极输出的恒定电压被提供给形成P沟道型第一功率MOSFET和构成读出放大器的P沟道型MOSFET的N阱区域作为偏置电压。

54. 发明授权

US5426042A Klebsella oxytoca ferm BP-I/3616 and immobilization thereof with a gelating agent in pores of a membrane 失效
标题翻译： Klebsella oxytoca ferm BP-I / 3616，并用胶凝剂在膜的孔中固定
公开(公告)号：US5426042A
公开(公告)日：1995-06-20
申请号：US179593
申请日：1994-01-07
申请人： Shigeru Maeda , Akira Ohki , Takeshi Sato , Naho Kato , Hirofumi Akano , Yoshiya Kawamura , Keizo Hatagaki , Yasushi Takahashi , Mikio Yamada , Hajime Okumura
发明人： Shigeru Maeda , Akira Ohki , Takeshi Sato , Naho Kato , Hirofumi Akano , Yoshiya Kawamura , Keizo Hatagaki , Yasushi Takahashi , Mikio Yamada , Hajime Okumura
IPC分类号： C12Q1/00 , G01N33/18 , C12N11/10 , C12N1/12 , C12N11/04 , G01N27/26
CPC分类号： G01N33/1806 , C12Q1/001 , G01N33/1866 , G01N33/1893 , Y10S435/817 , Y10S435/852
摘要： A BOD analyzer is prepared having a microbe sensor containing an oxygen electrode and a microbe membrane. The microbe membrane is made by immobilizing microorganisms belonging to the genus Klebsiella in the membrane. Specifically, the BOD analyzer has a flow cell equipped with a microbe sensor containing an oxygen electrode and a microbe membrane, and a liquid passage which is connected with an entrance of the flow cell and which is equipped with an outlet. The microbe membrane is made by immobilizing microorganisms belonging to Klebsiella oxytoca 12092 strain in a porous hydrophilic membrane having an average pore size of 0.65-3 .mu.m in diameter by using at least one gelating agent selected from alginic acid or salts thereof, agar, gellan gum, xathane gum, gelatine, carageenan, locust bean gum, methylcellulose, pectin, or pullulan. The BOD analyzer can be used for batch or continuous BOD analysis and enables carrying out BOD analysis in a short period of time.
摘要翻译：制备具有含有氧电极和微生物膜的微生物传感器的BOD分析仪。微生物膜通过将属于克雷伯菌属的微生物固定在膜中而制成。具体而言，BOD分析装置具有配置有含有氧电极和微生物膜的微生物传感器的流通池，与流通池的入口连接并具有出口的液体通道。通过使用至少一种选自藻酸或其盐，琼脂，结冷胶的凝胶剂，将属于克雷伯氏菌12092菌株的微生物直接固定在平均孔径为0.65-3μm的多孔亲水膜中来制备微生物膜口香糖，xathane胶，明胶，角叉菜胶，刺槐豆胶，甲基纤维素，果胶或支链淀粉。 BOD分析仪可用于批量或连续BOD分析，可在短时间内进行BOD分析。

55. 发明授权

US5420433A Charged particle beam exposure apparatus 失效
标题翻译：带电粒子束曝光装置
公开(公告)号：US5420433A
公开(公告)日：1995-05-30
申请号：US214415
申请日：1994-03-18
申请人： Yoshihisa Oae , Yasushi Takahashi , Hiroshi Yasuda
发明人： Yoshihisa Oae , Yasushi Takahashi , Hiroshi Yasuda
IPC分类号： H01L21/027 , G03F7/20 , H01J37/30 , H01J37/317
CPC分类号： H01J37/3002 , H01J2237/022 , H01J2237/3175
摘要： A barrier electrode is formed above an article to be exposed so as to be opposite the surface of the article to be exposed. A voltage is applied to the barrier electrode so as to form a barrier electric field surrounding the optical axis of a charged particle beam and surrounding the article to be exposed.
摘要翻译：阻挡电极形成在要暴露的物品的上方，以与要暴露的物品的表面相对。向阻挡电极施加电压，以形成围绕带电粒子束的光轴并围绕待曝光的物品的阻挡电场。

56. 发明授权

US5288567A Stencil mask and charged particle beam exposure method and apparatus using the stencil mask 失效
公开(公告)号：US5288567A
公开(公告)日：1994-02-22
申请号：US718433
申请日：1991-06-20
申请人： Kiichi Sakamoto , Yasushi Takahashi , Yoshihisa Oae , Hiroshi Yasuda
发明人： Kiichi Sakamoto , Yasushi Takahashi , Yoshihisa Oae , Hiroshi Yasuda
IPC分类号： H01L21/027 , G03F1/20 , G03F7/20 , H01J37/04 , H01J37/317 , H01L21/30 , G03F9/00
CPC分类号： B82Y10/00 , B82Y40/00 , G03F1/20 , G03F7/2047 , H01J37/045 , H01J37/3174
摘要： A stencil mask is used for exposing a pattern on a wafer using a charged particle beam which is transmitted through the stencil mask. The stencil mask is made up of a plate, and at least a block pattern region formed on the plate. The block pattern region includes apertures of arbitrary shapes for transmitting the charged particle beam which irradiates the apertures within the block pattern region in one shot of the charged particle beam. The block pattern region forms a block mask in which a pair of confronting blanking electrodes is provided with respect to at least predetermined ones of the apertures.

57. 发明授权

US5287000A Resin-encapsulated semiconductor memory device useful for single in-line packages 失效
标题翻译：树脂封装的半导体存储器件可用于单个在线封装
公开(公告)号：US5287000A
公开(公告)日：1994-02-15
申请号：US674969
申请日：1991-03-26
申请人： Yasushi Takahashi , Kazuyuki Miyazawa , Hidetoshi Iwai , Masaya Muranaka , Yoshitaka Kinoshita , Satoru Koshiba
发明人： Yasushi Takahashi , Kazuyuki Miyazawa , Hidetoshi Iwai , Masaya Muranaka , Yoshitaka Kinoshita , Satoru Koshiba
IPC分类号： H01L23/495 , H01L23/48 , H01L27/10 , H01L29/44 , H02G3/08
CPC分类号： H01L24/06 , H01L23/4951 , H01L23/49541 , H01L24/49 , H01L2224/05554 , H01L2224/05624 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/48624 , H01L2224/48724 , H01L2224/48799 , H01L2224/49171 , H01L2224/49179 , H01L2224/73265 , H01L2224/85201 , H01L2224/85205 , H01L24/45 , H01L24/48 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01047 , H01L2924/0105 , H01L2924/01058 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/12036 , H01L2924/1301 , H01L2924/1305 , H01L2924/14 , H01L2924/181 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011
摘要： According to one aspect of the present invention, a semiconductor chip, which can be mounted in a zigzag in-line type package (ZIP) partially using a tabless lead frame, includes bonding pads arranged on the chip so that the chip can be applied also to other different types of packages. These different types of packages include a small out-line J-bent type package (SOJ) which uses a lead frame with tab, and a dual in-line type package (DIP) which uses a tabless lead frame. Further, a plurality of bonding pad pairs are provided amongst the bonding pads on the chip, each pad of such bonding pad pairs having the same function as the other pad associated therewith thereby duplicating a common function in different bonding pads on the semiconductor chip so as to make the semiconductor chip compatible with a variety of or different types of packages. In accordance with another aspect of the invention, a resin-encapsulated semiconductor device of the ZIP structure is provided in which a semiconductor pellet having a plurality of external terminals disposed on a device-forming surface along each side of the planar shape is encapsulated with a resin, wherein inner leads for signals connected electrically with external terminals, disposed opposing to the surface of the resin-encapsulated portion disposed with outer leads and disposed along the most remote side of the semiconductor pellet, are arranged so as to overlap the semiconductor pellet.
摘要翻译：根据本发明的一个方面，可以使用无引线引线框架部分地以锯齿形的在线型封装（ZIP）安装的半导体芯片包括布置在芯片上的焊盘，使得芯片也可以被应用到其他不同类型的包。这些不同类型的封装包括使用带引脚的引线框架的小型外部J型弯曲型封装（SOJ）和使用无引脚引线框架的双列直插型封装（DIP）。此外，在芯片上的接合焊盘之间设置多个接合焊盘对，这种接合焊盘对的每个焊盘具有与其相关联的另一个焊盘相同的功能，从而在半导体芯片上的不同接合焊盘中复制共同的功能，以便使半导体芯片与各种或不同类型的封装兼容。根据本发明的另一方面，提供了一种ZIP结构的树脂封装的半导体器件，其中具有设置在沿着平面形状的每一侧的器件形成表面上的多个外部端子的半导体芯片被封装在树脂，其中与外部端子电连接的信号的内部引线设置成与设置有外部引线并沿着半导体芯片的最远侧设置的树脂封装部分的表面相对设置，以与半导体芯片重叠。

58. 发明授权

US5215623A Blanking aperture array and method of producing same 失效
标题翻译：空白孔阵列及其生产方法
公开(公告)号：US5215623A
公开(公告)日：1993-06-01
申请号：US685678
申请日：1991-04-16
申请人： Yasushi Takahashi , Tomiyasu Saito
发明人： Yasushi Takahashi , Tomiyasu Saito
IPC分类号： H01L21/027 , H01J37/04 , H01J37/317 , H01L21/30
CPC分类号： B82Y10/00 , B82Y40/00 , H01J37/045 , H01J37/3177 , Y10T428/24322
摘要： A blanking aperture array for use in an electron beam exposure system and a method of producing the same. An electrode layer is formed on a substrate having shift register devices, and then an electron beam aperture is formed, extending as an aligned aperture and associated opening through the substrate and electrode layer, respectively, to thereby effectively form a deep electron beam aperture.

59. 发明授权

US5121381A Optical switching apparatus for digital signal cross connection and method of interswitch optical transmission of digital signals 失效
标题翻译：数字信号交叉用光开关装置及数字信号交会间光传输方法
公开(公告)号：US5121381A
公开(公告)日：1992-06-09
申请号：US397553
申请日：1989-08-23
申请人： Yasushi Takahashi , Yoshitaka Takasaki
发明人： Yasushi Takahashi , Yoshitaka Takasaki
IPC分类号： G02F1/313 , H04B10/032 , H04B10/27 , H04J14/02 , H04Q3/52 , H04Q11/00 , H04Q11/02
CPC分类号： H04J14/02 , H04Q11/0001 , H04J14/029 , H04Q2011/0081
摘要： Disclosed is an optical switching apparatus comprising means for converting serial optical or electrical signals into parallel signals in a time division mode, first and second time division switch groups and a space division switch group for cross connecting the signal of the optical or electrical signals, and means for generating the edited optical or electrical signals as serial signals again.
摘要翻译：公开了一种光开关装置，包括用于将串行光信号或电信号以时分模式转换为并行信号的装置，第一和第二时分开关组以及用于交叉连接光信号或电信号的信号的空分开关组，以及用于将编辑的光学或电信号再次生成为串行信号的装置。

60. 发明授权

US4934820A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US4934820A
公开(公告)日：1990-06-19
申请号：US256862
申请日：1988-10-12
申请人： Yasushi Takahashi , Kazuyuki Miyazawa , Hidetoshi Iwai , Masaya Muranaka
发明人： Yasushi Takahashi , Kazuyuki Miyazawa , Hidetoshi Iwai , Masaya Muranaka
IPC分类号： H01L21/60 , G11C11/401 , H01L23/495 , H01L23/50
CPC分类号： H01L24/49 , H01L23/4951 , H01L23/49541 , H01L23/49555 , H01L24/05 , H01L2224/04042 , H01L2224/05554 , H01L2224/05624 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48624 , H01L2224/49171 , H01L2224/73265 , H01L2224/85424 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01047 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/10253 , H01L2924/14 , H01L2924/181 , H01L2924/3011
摘要： According to the present invention, a semiconductor chip is mounted on a zigzag in-line type package (ZIP) partially using a tabless lead frame and bonding pads are arranged on the chip so that the chip can be applied also to other different types of packages. As different types of packages there are a small out-line J-bent type package (SOJ) for which there is used a lead frame with tab and a dual in-line type package (DIP) for which there is used a tabless lead frame. Further, a plurality of bonding pad pairs are provided among the bonding pads on the chip each pad of such bonding pad pairs having the same function as the other pad associated therewith thereby duplicating a common function in different bonding pads on the semiconductor chip so as to readily facilitate, or make compatible, the semiconductor chip to a variety of or different types of packages.
摘要翻译：根据本发明，半导体芯片部分地使用无引线引线框安装在Z字形在线型封装（ZIP）上，并且焊盘布置在芯片上，使得芯片也可以应用于其他不同类型的封装。作为不同类型的封装，有一个小型的外部J型弯曲型封装（SOJ），其中使用了带有引脚的引线框架和双列直插式封装（DIP），其中使用无引脚引线框架。此外，在芯片上的接合焊盘之间设置多个接合焊盘对，这样的焊盘对的每个焊盘具有与其相关的另一焊盘相同的功能，从而在半导体芯片上的不同接合焊盘中复制共同的功能，以便容易地将半导体芯片促进或兼容到各种或不同类型的封装。

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