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1. 发明授权

US5426613A Semiconductor memory device with improved substrate arrangement to permit forming a plurality of different types of random access memory, and a testing method therefor 失效
标题翻译：具有改进的基板布置以允许形成多种不同类型的随机存取存储器的半导体存储器件及其测试方法
公开(公告)号：US5426613A
公开(公告)日：1995-06-20
申请号：US972907
申请日：1992-11-06
申请人： Yasushi Takahashi , Hidetoshi Iwai , Satoshi Oguchi , Hisashi Nakamura , Hiroyuki Uchiyama , Toshitugu Takekuma , Shigetoshi Sakomura , Kazuyuki Miyazawa , Masamichi Ishihara , Ryoichi Hori , Takeshi Kizaki , Yoshihisa Koyama , Haruo Ii , Masaya Muranaka , Hidetomo Aoyagi , Hiromi Matsuura
发明人： Yasushi Takahashi , Hidetoshi Iwai , Satoshi Oguchi , Hisashi Nakamura , Hiroyuki Uchiyama , Toshitugu Takekuma , Shigetoshi Sakomura , Kazuyuki Miyazawa , Masamichi Ishihara , Ryoichi Hori , Takeshi Kizaki , Yoshihisa Koyama , Haruo Ii , Masaya Muranaka , Hidetomo Aoyagi , Hiromi Matsuura
IPC分类号： G11C5/00 , G11C5/02 , G11C7/10 , G11C11/4074 , G11C11/408 , G11C11/4096 , G11C29/00 , G11C29/02 , G11C29/46 , G11C29/50 , G11C7/00 , G11C8/00
CPC分类号： G11C29/027 , G11C11/4074 , G11C11/4082 , G11C11/4096 , G11C29/02 , G11C29/46 , G11C29/50 , G11C29/50012 , G11C5/00 , G11C5/025 , G11C7/1045 , G11C11/401 , G11C2029/5006 , G11C29/78
摘要： A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.
摘要翻译：提供了一种半导体存储器件，其包括适于形成具有不同封装规格，不同位结构和不同工作模式的大量类型的DRAM的衬底布置。结合这些，接合垫被布置在适于不同包装类型的最佳位置处。还提供了各种布局布置以最小化空间并改善访问时间。提供了额外的功能，包括改进的输出缓冲器电路，保护电路和测试方法以便于半导体存储器件的操作。

2. 发明授权

US5287000A Resin-encapsulated semiconductor memory device useful for single in-line packages 失效
标题翻译：树脂封装的半导体存储器件可用于单个在线封装
公开(公告)号：US5287000A
公开(公告)日：1994-02-15
申请号：US674969
申请日：1991-03-26
申请人： Yasushi Takahashi , Kazuyuki Miyazawa , Hidetoshi Iwai , Masaya Muranaka , Yoshitaka Kinoshita , Satoru Koshiba
发明人： Yasushi Takahashi , Kazuyuki Miyazawa , Hidetoshi Iwai , Masaya Muranaka , Yoshitaka Kinoshita , Satoru Koshiba
IPC分类号： H01L23/495 , H01L23/48 , H01L27/10 , H01L29/44 , H02G3/08
CPC分类号： H01L24/06 , H01L23/4951 , H01L23/49541 , H01L24/49 , H01L2224/05554 , H01L2224/05624 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/48624 , H01L2224/48724 , H01L2224/48799 , H01L2224/49171 , H01L2224/49179 , H01L2224/73265 , H01L2224/85201 , H01L2224/85205 , H01L24/45 , H01L24/48 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01047 , H01L2924/0105 , H01L2924/01058 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/12036 , H01L2924/1301 , H01L2924/1305 , H01L2924/14 , H01L2924/181 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011
摘要： According to one aspect of the present invention, a semiconductor chip, which can be mounted in a zigzag in-line type package (ZIP) partially using a tabless lead frame, includes bonding pads arranged on the chip so that the chip can be applied also to other different types of packages. These different types of packages include a small out-line J-bent type package (SOJ) which uses a lead frame with tab, and a dual in-line type package (DIP) which uses a tabless lead frame. Further, a plurality of bonding pad pairs are provided amongst the bonding pads on the chip, each pad of such bonding pad pairs having the same function as the other pad associated therewith thereby duplicating a common function in different bonding pads on the semiconductor chip so as to make the semiconductor chip compatible with a variety of or different types of packages. In accordance with another aspect of the invention, a resin-encapsulated semiconductor device of the ZIP structure is provided in which a semiconductor pellet having a plurality of external terminals disposed on a device-forming surface along each side of the planar shape is encapsulated with a resin, wherein inner leads for signals connected electrically with external terminals, disposed opposing to the surface of the resin-encapsulated portion disposed with outer leads and disposed along the most remote side of the semiconductor pellet, are arranged so as to overlap the semiconductor pellet.
摘要翻译：根据本发明的一个方面，可以使用无引线引线框架部分地以锯齿形的在线型封装（ZIP）安装的半导体芯片包括布置在芯片上的焊盘，使得芯片也可以被应用到其他不同类型的包。这些不同类型的封装包括使用带引脚的引线框架的小型外部J型弯曲型封装（SOJ）和使用无引脚引线框架的双列直插型封装（DIP）。此外，在芯片上的接合焊盘之间设置多个接合焊盘对，这种接合焊盘对的每个焊盘具有与其相关联的另一个焊盘相同的功能，从而在半导体芯片上的不同接合焊盘中复制共同的功能，以便使半导体芯片与各种或不同类型的封装兼容。根据本发明的另一方面，提供了一种ZIP结构的树脂封装的半导体器件，其中具有设置在沿着平面形状的每一侧的器件形成表面上的多个外部端子的半导体芯片被封装在树脂，其中与外部端子电连接的信号的内部引线设置成与设置有外部引线并沿着半导体芯片的最远侧设置的树脂封装部分的表面相对设置，以与半导体芯片重叠。

3. 发明授权

US4934820A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US4934820A
公开(公告)日：1990-06-19
申请号：US256862
申请日：1988-10-12
申请人： Yasushi Takahashi , Kazuyuki Miyazawa , Hidetoshi Iwai , Masaya Muranaka
发明人： Yasushi Takahashi , Kazuyuki Miyazawa , Hidetoshi Iwai , Masaya Muranaka
IPC分类号： H01L21/60 , G11C11/401 , H01L23/495 , H01L23/50
CPC分类号： H01L24/49 , H01L23/4951 , H01L23/49541 , H01L23/49555 , H01L24/05 , H01L2224/04042 , H01L2224/05554 , H01L2224/05624 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48624 , H01L2224/49171 , H01L2224/73265 , H01L2224/85424 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01047 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/10253 , H01L2924/14 , H01L2924/181 , H01L2924/3011
摘要： According to the present invention, a semiconductor chip is mounted on a zigzag in-line type package (ZIP) partially using a tabless lead frame and bonding pads are arranged on the chip so that the chip can be applied also to other different types of packages. As different types of packages there are a small out-line J-bent type package (SOJ) for which there is used a lead frame with tab and a dual in-line type package (DIP) for which there is used a tabless lead frame. Further, a plurality of bonding pad pairs are provided among the bonding pads on the chip each pad of such bonding pad pairs having the same function as the other pad associated therewith thereby duplicating a common function in different bonding pads on the semiconductor chip so as to readily facilitate, or make compatible, the semiconductor chip to a variety of or different types of packages.
摘要翻译：根据本发明，半导体芯片部分地使用无引线引线框安装在Z字形在线型封装（ZIP）上，并且焊盘布置在芯片上，使得芯片也可以应用于其他不同类型的封装。作为不同类型的封装，有一个小型的外部J型弯曲型封装（SOJ），其中使用了带有引脚的引线框架和双列直插式封装（DIP），其中使用无引脚引线框架。此外，在芯片上的接合焊盘之间设置多个接合焊盘对，这样的焊盘对的每个焊盘具有与其相关的另一焊盘相同的功能，从而在半导体芯片上的不同接合焊盘中复制共同的功能，以便容易地将半导体芯片促进或兼容到各种或不同类型的封装。

4. 发明授权

US5217917A Semiconductor memory device with improved substrate arrangement to permit forming a plurality of different types of random access memory, and a testing method therefor 失效
标题翻译：具有改进的基板布置以允许形成多种不同类型的随机存取存储器的半导体存储器件及其测试方法
公开(公告)号：US5217917A
公开(公告)日：1993-06-08
申请号：US496280
申请日：1990-03-20
申请人： Yasushi Takahashi , Hidetoshi Iwai , Satoshi Oguchi , Hisashi Nakamura , Hiroyuki Uchiyama , Toshitugu Takemuma , Shigetoshi Sakomura , Kazuyuki Miyazawa , Masamichi Ishihara , Ryoichi Hori , Takeshi Kizaki , Yoshihisa Koyama , Haruo Ii , Masaya Muranaka , Hidetomo Aoyagi , Hiromi Matsuura
发明人： Yasushi Takahashi , Hidetoshi Iwai , Satoshi Oguchi , Hisashi Nakamura , Hiroyuki Uchiyama , Toshitugu Takemuma , Shigetoshi Sakomura , Kazuyuki Miyazawa , Masamichi Ishihara , Ryoichi Hori , Takeshi Kizaki , Yoshihisa Koyama , Haruo Ii , Masaya Muranaka , Hidetomo Aoyagi , Hiromi Matsuura
IPC分类号： G11C5/00 , G11C5/02 , G11C7/10 , G11C11/4074 , G11C11/408 , G11C11/4096 , G11C29/00 , G11C29/02 , G11C29/46 , G11C29/50
CPC分类号： G11C29/027 , G11C11/4074 , G11C11/4082 , G11C11/4096 , G11C29/02 , G11C29/46 , G11C29/50 , G11C29/50012 , G11C5/00 , G11C5/025 , G11C7/1045 , G11C11/401 , G11C2029/5006 , G11C29/78
摘要： A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.
摘要翻译：提供了一种半导体存储器件，其包括适于形成具有不同封装规格，不同位结构和不同工作模式的大量类型的DRAM的衬底布置。结合这些，接合垫被布置在适于不同包装类型的最佳位置处。还提供了各种布局布置以最小化空间并改善访问时间。提供了额外的功能，包括改进的输出缓冲器电路，保护电路和测试方法以便于半导体存储器件的操作。

5. 发明授权

US5151772A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5151772A
公开(公告)日：1992-09-29
申请号：US616705
申请日：1990-11-20
申请人： Yasushi Takahashi , Hiromi Matsuura , Yoshihisa Koyama , Masaya Muranaka , Katsutaka Kimura , Kazuyuki Miyazawa , Masamichi Ishihara , Hidetoshi Iwai
发明人： Yasushi Takahashi , Hiromi Matsuura , Yoshihisa Koyama , Masaya Muranaka , Katsutaka Kimura , Kazuyuki Miyazawa , Masamichi Ishihara , Hidetoshi Iwai
IPC分类号： H01L23/522 , H01L27/108
CPC分类号： H01L23/5226 , H01L27/10805 , H01L2924/0002 , Y10S257/923
摘要： A semiconductor integrated circuit device is provided which includes a memory cell array located in a generally central area of a semiconductor substrate with peripheral circuits located at both ends of the semiconductor substrate. A wiring layer is also provided which couples the peripheral circuits to one another. This wiring layer is arranged to have a double-layer structure of first and second aluminum layers which are electrically coupled to one another.
摘要翻译：提供一种半导体集成电路器件，其包括位于半导体衬底的大致中心区域中的存储单元阵列，其具有位于半导体衬底两端的外围电路。还提供了将外围电路彼此耦合的布线层。该布线层被布置成具有彼此电耦合的第一和第二铝层的双层结构。

6. 发明授权

US5805513A Semiconductor memory device with improved substrate arrangement to permit forming a plurality of different types of random access memory, and a testing method therefor 失效
公开(公告)号：US5805513A
公开(公告)日：1998-09-08
申请号：US432867
申请日：1995-05-02
申请人： Yasushi Takahashi , Hidetoshi Iwai , Satoshi Oguchi , Hisashi Nakamura , Hiroyuki Uchiyama , Toshitugu Takekuma , Shigetoshi Sakomura , Kazuyuki Miyazawa , Masamichi Ishihara , Ryoichi Hori , Takeshi Kizaki , Yoshihisa Koyama , Haruo Ii , Masaya Muranaka , Hidetomo Aoyagi , Hiromi Matsuura
发明人： Yasushi Takahashi , Hidetoshi Iwai , Satoshi Oguchi , Hisashi Nakamura , Hiroyuki Uchiyama , Toshitugu Takekuma , Shigetoshi Sakomura , Kazuyuki Miyazawa , Masamichi Ishihara , Ryoichi Hori , Takeshi Kizaki , Yoshihisa Koyama , Haruo Ii , Masaya Muranaka , Hidetomo Aoyagi , Hiromi Matsuura
IPC分类号： G11C5/00 , G11C5/02 , G11C7/10 , G11C11/4074 , G11C11/408 , G11C11/4096 , G11C29/00 , G11C29/02 , G11C29/46 , G11C29/50 , G11C7/00
CPC分类号： G11C29/027 , G11C11/4074 , G11C11/4082 , G11C11/4096 , G11C29/02 , G11C29/46 , G11C29/50 , G11C29/50012 , G11C5/00 , G11C5/025 , G11C7/1045 , G11C11/401 , G11C2029/5006 , G11C29/78
摘要： A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.

7. 发明授权

US5485425A Semiconductor memory device having redundant column and operation method thereof 失效
标题翻译：具有冗余列的半导体存储器件及其操作方法
公开(公告)号：US5485425A
公开(公告)日：1996-01-16
申请号：US375727
申请日：1995-01-20
申请人： Hidetoshi Iwai , Masaya Muranaka , Takumi Nasu , Shunichi Sukegawa
发明人： Hidetoshi Iwai , Masaya Muranaka , Takumi Nasu , Shunichi Sukegawa
IPC分类号： G11C11/401 , G11C17/12 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C17/126 , G11C29/84
摘要： There is provided a semiconductor memory device having a redundant column. This memory device has a redundant column disposed in the direction of the Y-system address, a ROM accessed by using an X-system address, a Y-system address signal having a defective cell included in the cells therein being electrically written into the ROM, a comparator circuit for comparing a signal read out from this ROM with a Y-system address signal and outputting a coincidence signal upon coincidence, and a defect relieving circuit responsive to output of the coincidence signal from this comparator circuit to cause selection of the redundant column of Y system instead of the Y-system address selection device.
摘要翻译：提供了具有冗余列的半导体存储器件。该存储装置具有沿Y系统地址的方向设置的冗余列，通过使用X系统地址访问的ROM，其中包含在其中的单元中的具有缺陷单元的Y系统地址信号被电写入ROM 比较电路，用于将从该ROM读出的信号与Y系统地址信号进行比较，并且一致地输出一致信号，以及响应来自该比较器电路的符合信号的输出的缺陷消除电路，以选择冗余 Y系列的列，而不是Y系统地址选择设备。

8. 发明授权

US06577530B2 Semiconductor memory device having memory cells each capable of storing three or more values 失效
公开(公告)号：US06577530B2
公开(公告)日：2003-06-10
申请号：US09982162
申请日：2001-10-19
申请人： Masaya Muranaka , Yutaka Ito
发明人： Masaya Muranaka , Yutaka Ito
IPC分类号： G11C1140
CPC分类号： H01L27/105 , G11C11/5692 , G11C16/0433 , H01L27/108 , H01L27/115 , H01L27/1203
摘要： Memory cells are used which each have a MOSFET that holds an information voltage of three or more values at its gate, a writing transistor that supplies the information voltage of three or more values to the gate of the MOSFET, and a reading transistor connected in series with the MOSFET. A plurality of reference voltages corresponding to the information voltage of three or more values are applied from a source line to the sources of the MOSFETs, so that digital data is produced by a combination of on-state/off-state of the MOSFET and the plurality of reference voltages or that the source voltages themselves of the MOSFETs are produced as read voltages.

9. 发明授权

US5021998A Semiconductor memory device with low-house pads for electron beam test 失效
标题翻译：半导体存储器件，具有用于电子束测试的低屋垫
公开(公告)号：US5021998A
公开(公告)日：1991-06-04
申请号：US339843
申请日：1989-04-18
申请人： Yukihide Suzuki , Masaya Muranaka , Masamichi Ishihara
发明人： Yukihide Suzuki , Masaya Muranaka , Masamichi Ishihara
IPC分类号： G11C29/00 , G11C29/50 , H01L21/66 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10808
摘要： Disclosed are measurement (observation) pads for judging whether or not a dynamic random access memory (DRAM) adopting a shared sense system is functioning as designed. Concretely, measurement pads are formed by the step of forming a second layer of wiring respectively connected to pairs of complementary data lines which are formed by the step of forming a first layer of wiring, and the signal waveforms of the pairs of complementary data lines are measured using the measurement pads. Further, the measurement pads are provided between wiring layers which become fixed potentials in, at least, the operation of measuring data. In addition, each of the measurement pads is used in common by data lines which are respectively connected to two memory cells located in different memory cell mats.
摘要翻译：公开了用于判断采用共享感测系统的动态随机存取存储器（DRAM）是否如此设计的功能的测量（观察）焊盘。具体地，通过形成分别连接到形成第一层布线的步骤形成的互补数据线对的第二层布线的步骤形成测量焊盘，并且互补数据线对的信号波形是使用测量垫测量。此外，至少在测量数据的操作中，测量焊盘设置在成为固定电位的布线层之间。此外，每个测量焊盘由分别连接到位于不同存储单元垫中的两个存储单元的数据线共同使用。

10. 发明授权

US07702704B2 Random number generating method and semiconductor integrated circuit device 失效
标题翻译：随机数生成方法和半导体集成电路器件
公开(公告)号：US07702704B2
公开(公告)日：2010-04-20
申请号：US10588788
申请日：2004-02-12
申请人： Masaya Muranaka
发明人： Masaya Muranaka
IPC分类号： G06F1/02
CPC分类号： G06F7/588 , H04L9/06
摘要： A random number generating method for an electronic device including a plurality of unit circuits each first and second logic circuits, each logic circuit having a same shape and being formed through a same fabrication process, and an amplifier circuit for forming a binary signal by amplifying a noise superposed on the differential voltage of threshold voltages of the first and the second logic circuits; and a signal variation detecting circuit for forming an output signal in response to a variation in any of a plurality of binary signals outputted from the plurality of unit circuits, wherein a plurality of binary signals outputted from the signal variation detecting circuit are combined to generate a random number.
摘要翻译：一种电子设备的随机数生成方法，包括每个第一和第二逻辑电路的多个单位电路，每个逻辑电路具有相同的形状并通过相同的制造过程形成，以及放大器电路，用于通过放大二进制信号来形成二进制信号噪声叠加在第一和第二逻辑电路的阈值电压的差分电压上; 以及信号变化检测电路，用于响应于从多个单位电路输出的多个二进制信号中的任何一个的变化而形成输出信号，其中从信号变化检测电路输出的多个二进制信号被组合以产生随机数。

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