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51. 发明授权

US07864574B2 Memory device and memory programming method 有权
标题翻译：存储器和存储器编程方法
公开(公告)号：US07864574B2
公开(公告)日：2011-01-04
申请号：US12453108
申请日：2009-04-29
申请人： Kyoung Lae Cho , Yong June Kim , Seung-Hwan Song , Jun Jin Kong
发明人： Kyoung Lae Cho , Yong June Kim , Seung-Hwan Song , Jun Jin Kong
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C2211/5621
摘要： Provided are memory devices and memory programming methods. A memory device may include a multi-bit cell array including a plurality of multi-bit cells, a programming unit configured to program a first data page in the plurality of multi-bit cells and to program a second data page in the multi-bit cells with the programmed first data page, a first controller configured to divide the multi-bit cells with the programmed first data page into a first group and a second group, and a second controller configured to set a target threshold voltage interval of each of the multi-bit cells included in the first group based on first read voltage levels and the second data page, and to set a target threshold voltage interval of each of the multi-bit cells included in the second group based on second read threshold voltage levels and the second data page.
摘要翻译：提供的是存储器件和存储器编程方法。存储器件可以包括包括多个多位单元的多位单元阵列，编程单元，被配置为对多个多位单元中的第一数据页进行编程，并编程多位单元中的第二数据页具有编程的第一数据页的单元，被配置为将多位单元与编程的第一数据页划分为第一组和第二组的第一控制器，以及配置成将每个的第一数据页的目标阈值电压间隔基于第一读取电压电平和第二数据页面包括在第一组中的多位单元，并且基于第二读取阈值电压电平来设置包括在第二组中的每个多位单元的目标阈值电压间隔，以及第二个数据页面。

52. 发明申请

US20100241928A1 Data Processing System Having ECC Encoding and Decoding Circuits Therein with Code Rate Selection Based on Bit Error Rate Detection 审中-公开
标题翻译：具有基于误码率检测的码率选择的ECC编码和解码电路的数据处理系统
公开(公告)号：US20100241928A1
公开(公告)日：2010-09-23
申请号：US12716793
申请日：2010-03-03
申请人： Jaehong Kim , Yong June Kim , Junjin Kong , Seung-Hwan Song
发明人： Jaehong Kim , Yong June Kim , Junjin Kong , Seung-Hwan Song
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/618 , G06F11/1012 , H03M13/13 , H03M13/353 , H03M13/3738 , H03M13/6356 , H03M13/6362
摘要： A data processing system includes an error checking and correction (ECC) encoding circuit, an integrated circuit memory and a code rate control circuit. The ECC encoding circuit is configured to selectively apply a plurality of unique ECC code rates to write data received by the data processing system during an operation to convert the write data into encoded data, in response to a code rate selection signal. The integrated circuit memory includes a plurality of storage regions therein. These storage regions are configured to receive respective portions of the encoded data from the ECC encoding circuit. The code rate control circuit is configured to generate the code rate selection signal. This code rate selection signal has a value that specifies the corresponding ECC code rate to be applied to respective portions of the write data.
摘要翻译：数据处理系统包括纠错（ECC）编码电路，集成电路存储器和码率控制电路。 ECC编码电路被配置为响应于码率选择信号，在操作期间选择性地应用多个唯一ECC码率来写入由数据处理系统接收的数据，以将写入数据转换为编码数据。集成电路存储器包括多个存储区域。这些存储区域被配置为从ECC编码电路接收编码数据的相应部分。码率控制电路被配置为产生码率选择信号。该码率选择信号具有指定应用于写入数据的各个部分的相应的ECC码率的值。

53. 发明授权

US07639539B2 Method and apparatus for programming data of memory cells considering floating poly coupling 有权
标题翻译：考虑浮动聚合耦合的存储器单元的数据编程方法和装置
公开(公告)号：US07639539B2
公开(公告)日：2009-12-29
申请号：US11905674
申请日：2007-10-03
申请人： Kyoung Lae Cho , Jun Jin Kong , Young Hwan Lee , Nam Phil Jo , Sung Chung Park , Seung-Hwan Song
发明人： Kyoung Lae Cho , Jun Jin Kong , Young Hwan Lee , Nam Phil Jo , Sung Chung Park , Seung-Hwan Song
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3418 , G11C16/3427
摘要： A method and an apparatus for programming data of memory cells considering coupling are provided. The method includes: calculating a change of a threshold voltage based on source data of the memory cells; converting source data which will be programmed based on the calculated change of the threshold voltage; and programming the converted source data.
摘要翻译：提供了考虑耦合的存储器单元的数据编程方法和装置。该方法包括：基于存储器单元的源数据计算阈值电压的变化; 基于所计算的阈值电压的变化来转换将被编程的源数据; 并对转换的源数据进行编程。

54. 发明申请

US20090207671A1 Memory data detecting apparatus and method for controlling reference voltage based on error in stored data 有权
标题翻译：存储器数据检测装置和基于存储数据中的误差来控制参考电压的方法
公开(公告)号：US20090207671A1
公开(公告)日：2009-08-20
申请号：US12216745
申请日：2008-07-10
申请人： Dong Hun Yu , Kyoung Lae Cho , Dong Hyuk Chae , Jun Jin Kong , Jae Hong Kim , Seung-Hwan Song
发明人： Dong Hun Yu , Kyoung Lae Cho , Dong Hyuk Chae , Jun Jin Kong , Jae Hong Kim , Seung-Hwan Song
IPC分类号： G11C7/00 , G11C29/04
CPC分类号： G11C7/1006 , G11C7/14 , G11C11/5642 , G11C29/00 , G11C29/028 , G11C29/42 , G11C29/50 , G11C2211/5634
摘要： Example embodiments may relate to a method and an apparatus for reading data stored in a memory, for example, providing a method and an apparatus for controlling a reference voltage based on an error of the stored data. Example embodiments may provide a memory data detecting apparatus including a first voltage comparator to compare a threshold voltage of a memory cell with a first reference voltage, a first data determiner to determine a value of at least one data bit stored in the memory cell according to a result of the comparison, an error verifier to verify whether an error occurs in the determined value, a reference voltage determiner to determine a second reference voltage that is lower than the first reference voltage based on a result of the verification, and a second data determiner to re-determine the value of the data based on the determined second reference voltage.
摘要翻译：示例性实施例可以涉及用于读取存储在存储器中的数据的方法和装置，例如提供一种基于存储的数据的错误来控制参考电压的方法和装置。示例性实施例可以提供一种存储器数据检测装置，其包括用于将存储器单元的阈值电压与第一参考电压进行比较的第一电压比较器，第一数据确定器，用于根据存储器单元存储的至少一个数据位的值，根据比较结果，用于验证所确定的值是否发生错误验证器，基于验证结果确定低于第一参考电压的第二参考电压的参考电压确定器，以及第二数据确定器，以基于所确定的第二参考电压重新确定数据的值。

55. 发明申请

US20090201729A1 Memory device and memory device heat treatment method 失效
标题翻译：记忆体和记忆体热处理方法
公开(公告)号：US20090201729A1
公开(公告)日：2009-08-13
申请号：US12219104
申请日：2008-07-16
申请人： Seung-Hwan Song , Jun Jin Kong , Jae Hong Kim , Young Hwan Lee , Dong Hyuk Chae , Tae Hun Kim , Kyoung Lae Cho
发明人： Seung-Hwan Song , Jun Jin Kong , Jae Hong Kim , Young Hwan Lee , Dong Hyuk Chae , Tae Hun Kim , Kyoung Lae Cho
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C7/04 , G11C11/5621 , G11C16/3427 , G11C16/349 , G11C29/00
摘要： A memory device and a memory device heat treatment method are provided. The memory device may include: a non-volatile memory device; one or more heating devices configured to contact with the non-volatile memory device and heat the non-volatile memory device; and a controller configured to control an operation of the one or more heating devices based on operational information of the non-volatile memory device. Through this, it may be possible to improve an available period of the non-volatile memory device.
摘要翻译：提供了一种存储器件和存储器件热处理方法。存储器件可以包括：非易失性存储器件; 配置成与所述非易失性存储器件接触并加热所述非易失性存储器件的一个或多个加热器件; 以及控制器，被配置为基于所述非易失性存储器件的操作信息来控制所述一个或多个加热装置的操作。由此，可以改善非易失性存储器件的可用周期。

56. 发明授权

US07507553B2 Galleria mellonella derived composition for detecting peptidoglycan, a method for use thereof, and a diagnostic kit containing the same 失效
标题翻译：用于检测肽聚糖的环孢霉烯衍生组合物，其使用方法和含有该肽的诊断试剂盒
公开(公告)号：US07507553B2
公开(公告)日：2009-03-24
申请号：US11460406
申请日：2006-07-27
申请人： Bu-Soo Park , Bok-Luel Lee , Ji-Won Park , Jeong-Mi Yeo , Hyun-Sic Kim , Chang-Hun Joo , Moon-Suk Kim , Seung-Hwan Song , Jong-Won Yoon , Yeon-Sung Park , Hong-Lak Kim , Joong-Hyuck Auh , Tae-Hoon Cho
发明人： Bu-Soo Park , Bok-Luel Lee , Ji-Won Park , Jeong-Mi Yeo , Hyun-Sic Kim , Chang-Hun Joo , Moon-Suk Kim , Seung-Hwan Song , Jong-Won Yoon , Yeon-Sung Park , Hong-Lak Kim , Joong-Hyuck Auh , Tae-Hoon Cho
IPC分类号： C12Q1/26
CPC分类号： G01N33/56911 , C12Q1/04 , C12Q1/26 , G01N2333/43552
摘要： The present invention relates to a composition for selectively detecting an extremely small amount of peptidoglycan in sample, a preparation method of the composition, and a detection kit for peptidoglycan. It is possible to quantify a small amount of peptidoglycan contained in human blood, tissue, body fluid, water or food, and to diagnose an infection of microorganism with peptidoglycan as a component of cell wall using the composition and the detection kit. In addition, the composition can be applied for a diagnosis reagent of detecting an infection of Gram-positive bacteria in animal or human being in advance, and thus, can be used for the prevention or treatment of food poisonings and bacterial sepsis.
摘要翻译：本发明涉及用于选择性地检测样品中极少量的肽聚糖的组合物，该组合物的制备方法和用于肽聚糖的检测试剂盒。使用组合物和检测试剂盒，可以量化少量的人血液，组织，体液，水或食物中的肽聚糖，并利用肽聚糖作为细胞壁的组分来诊断微生物的感染。此外，该组合物可以预先用于检测动物或人类中革兰氏阳性菌感染的诊断试剂，因此可用于预防或治疗食物中毒和细菌性败血症。

57. 发明申请

US20090027238A1 Apparatuses and methods for encoding and decoding 有权
标题翻译：用于编码和解码的装置和方法
公开(公告)号：US20090027238A1
公开(公告)日：2009-01-29
申请号：US12010025
申请日：2008-01-18
申请人： Jun Jin Kong , Sung Chung Park , Seung-Hwan Song , Jong Han Kim , Young Hwan Lee , Kyoung Lae Cho , Nam Phil Jo , Sung-Jae Byun
发明人： Jun Jin Kong , Sung Chung Park , Seung-Hwan Song , Jong Han Kim , Young Hwan Lee , Kyoung Lae Cho , Nam Phil Jo , Sung-Jae Byun
IPC分类号： H03M7/00
CPC分类号： H03M13/235 , H03M13/6561
摘要： A code encoding apparatus includes a delay circuit and a code generator. The delay circuit generates delayed information based on p-bit input information received in parallel. The delayed information is generated according to a clock. The code generator generates n·p-bit code based on at least one of the input information and the delayed information, where n is a rational number.
摘要翻译：码编码装置包括延迟电路和码发生器。延迟电路基于并行接收的p位输入信息产生延迟信息。延迟信息根据时钟生成。代码生成器基于输入信息和延迟信息中的至少一个生成n.p位代码，其中n是有理数。

58. 发明申请

US20080276149A1 Error control code apparatuses and methods of using the same 有权
标题翻译：错误控制代码设备及其使用方法
公开(公告)号：US20080276149A1
公开(公告)日：2008-11-06
申请号：US11905733
申请日：2007-10-03
申请人： Jun Jin Kong , Seung-Hwan Song , Young Hwan Lee , Dong Hyuk Chae , Kyoung Lae Cho , Nam Phil Jo , Sung Chung Park , Dong Ku Kang
发明人： Jun Jin Kong , Seung-Hwan Song , Young Hwan Lee , Dong Hyuk Chae , Kyoung Lae Cho , Nam Phil Jo , Sung Chung Park , Dong Ku Kang
IPC分类号： G06F11/07
CPC分类号： G06F11/1008
摘要： An Error Control Code (ECC) apparatus may include a control signal generator that generates an ECC control signal based on channel information. The ECC apparatus also may include: a plurality of ECC encoding controllers that output data respectively inputted via storage elements corresponding to the ECC control signal; and/or an encoding unit that encodes, using a plurality of data outputted from the plurality of ECC encoding controllers, encoding input data into a number of subdata corresponding to the ECC control signal. In addition or in the alternative, the ECC apparatus may include: a plurality of ECC decoding controllers that output data respectively inputted via the storage elements corresponding to the ECC control signal; and/or a decoding unit that decodes, using a plurality of data outputted from the plurality of ECC decoding controllers, a number of decoding input data corresponding to the ECC control signal into one piece of output data.
摘要翻译：错误控制码（ECC）装置可以包括基于频道信息产生ECC控制信号的控制信号发生器。 ECC装置还可以包括：多个ECC编码控制器，其输出经由与ECC控制信号对应的存储元件分别输入的数据; 和/或编码单元，其使用从所述多个ECC编码控制器输出的多个数据，将输入数据编码为对应于所述ECC控制信号的多个子数据进行编码。另外或者可选地，ECC装置可以包括：多个ECC解码控制器，其输出经由与ECC控制信号对应的存储元件分别输入的数据; 和/或解码单元，其使用从所述多个ECC解码控制器输出的多个数据将对应于所述ECC控制信号的多个解码输入数据解码为一条输出数据。

59. 发明申请

US20080244339A1 Read level control apparatuses and methods 有权
标题翻译：读取电平控制装置和方法
公开(公告)号：US20080244339A1
公开(公告)日：2008-10-02
申请号：US12010043
申请日：2008-01-18
申请人： Jun Jin Kong , Sung Chung Park , Dongku Kang , Dong Hyuk Chae , Seung Jae Lee , Nam Phil Jo , Seung-Hwan Song
发明人： Jun Jin Kong , Sung Chung Park , Dongku Kang , Dong Hyuk Chae , Seung Jae Lee , Nam Phil Jo , Seung-Hwan Song
IPC分类号： G06F11/00
CPC分类号： G11C29/42 , G06F11/1068 , G11C11/5628 , G11C29/028 , G11C2029/0409 , G11C2029/0411
摘要： Various read level control apparatuses and methods are provided. In various embodiments, the read level control apparatuses may include an error control code (ECC) decoding unit for ECC decoding data read from a storage unit, and a monitoring unit for monitoring a bit error rate (BER) based on the ECC decoded data and the read data. The apparatus may additionally include an error determination unit for determining an error rate of the read data based on the monitored BER, and a level control unit for controlling a read level of the storage unit based on the error rate.
摘要翻译：提供各种读取级别控制装置和方法。在各种实施例中，读取级别控制装置可以包括用于对从存储单元读取的数据进行ECC解码的错误控制代码（ECC）解码单元和用于基于ECC解码数据监视误码率（BER）的监视单元，以及读数据。该装置还可以包括用于基于所监视的BER来确定读取数据的错误率的错误确定单元，以及用于基于错误率来控制存储单元的读取电平的电平控制单元。

60. 发明授权

US08773922B2 Non-volatile memory device, memory card and system, and method determining read voltage by comparing referenced program data with comparative read data 失效
标题翻译：非易失性存储器件，存储卡和系统，以及通过将参考程序数据与比较读取数据进行比较来确定读取电压的方法
公开(公告)号：US08773922B2
公开(公告)日：2014-07-08
申请号：US12614545
申请日：2009-11-09
申请人： Seung-Hwan Song , Jaehong Kim , Kyoung Lae Cho , Yong June Kim , Jun Jin Kong , Jong Han Kim
发明人： Seung-Hwan Song , Jaehong Kim , Kyoung Lae Cho , Yong June Kim , Jun Jin Kong , Jong Han Kim
IPC分类号： G11C7/06
CPC分类号： G11C16/26 , G11C11/5642 , G11C29/00 , G11C2211/5634
摘要： A non-volatile semiconductor memory device and related method of determining a read voltage are disclosed. The non-volatile semiconductor memory device includes; a memory cell array including a plurality of memory cells, a read voltage determination unit configured to determine an optimal read voltage by comparing reference data obtained during a program operation with comparative data obtained during a subsequent read operation and changing a current read voltage to a new read voltage based on a result of the comparison, and a read voltage generation unit configured to generate the new read voltage in response to a read voltage control signal provided by the read voltage determination unit.
摘要翻译：公开了一种非易失性半导体存储器件及确定读取电压的相关方法。非易失性半导体存储器件包括：包括多个存储单元的存储单元阵列，读电压确定单元，被配置为通过将在编程操作期间获得的参考数据与在随后的读取操作期间获得的比较数据进行比较来确定最佳读取电压，并将当前读取电压改变为新的基于比较结果的读取电压和读取电压生成单元，被配置为响应于由读取电压确定单元提供的读取电压控制信号而产生新的读取电压。

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