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1. 发明申请

US20080276149A1 Error control code apparatuses and methods of using the same 有权
标题翻译：错误控制代码设备及其使用方法
公开(公告)号：US20080276149A1
公开(公告)日：2008-11-06
申请号：US11905733
申请日：2007-10-03
申请人： Jun Jin Kong , Seung-Hwan Song , Young Hwan Lee , Dong Hyuk Chae , Kyoung Lae Cho , Nam Phil Jo , Sung Chung Park , Dong Ku Kang
发明人： Jun Jin Kong , Seung-Hwan Song , Young Hwan Lee , Dong Hyuk Chae , Kyoung Lae Cho , Nam Phil Jo , Sung Chung Park , Dong Ku Kang
IPC分类号： G06F11/07
CPC分类号： G06F11/1008
摘要： An Error Control Code (ECC) apparatus may include a control signal generator that generates an ECC control signal based on channel information. The ECC apparatus also may include: a plurality of ECC encoding controllers that output data respectively inputted via storage elements corresponding to the ECC control signal; and/or an encoding unit that encodes, using a plurality of data outputted from the plurality of ECC encoding controllers, encoding input data into a number of subdata corresponding to the ECC control signal. In addition or in the alternative, the ECC apparatus may include: a plurality of ECC decoding controllers that output data respectively inputted via the storage elements corresponding to the ECC control signal; and/or a decoding unit that decodes, using a plurality of data outputted from the plurality of ECC decoding controllers, a number of decoding input data corresponding to the ECC control signal into one piece of output data.
摘要翻译：错误控制码（ECC）装置可以包括基于频道信息产生ECC控制信号的控制信号发生器。 ECC装置还可以包括：多个ECC编码控制器，其输出经由与ECC控制信号对应的存储元件分别输入的数据; 和/或编码单元，其使用从所述多个ECC编码控制器输出的多个数据，将输入数据编码为对应于所述ECC控制信号的多个子数据进行编码。另外或者可选地，ECC装置可以包括：多个ECC解码控制器，其输出经由与ECC控制信号对应的存储元件分别输入的数据; 和/或解码单元，其使用从所述多个ECC解码控制器输出的多个数据将对应于所述ECC控制信号的多个解码输入数据解码为一条输出数据。

2. 发明授权

US08112693B2 Error control code apparatuses and methods of using the same 有权
标题翻译：错误控制代码设备及其使用方法
公开(公告)号：US08112693B2
公开(公告)日：2012-02-07
申请号：US11905734
申请日：2007-10-03
申请人： Jun Jin Kong , Seung-Hwan Song , Dong Hyuk Chae , Kyoung Lae Cho , Seung Jae Lee , Nam Phil Jo , Sung Chung Park , Dong Ku Kang
发明人： Jun Jin Kong , Seung-Hwan Song , Dong Hyuk Chae , Kyoung Lae Cho , Seung Jae Lee , Nam Phil Jo , Sung Chung Park , Dong Ku Kang
IPC分类号： G11C29/00
CPC分类号： G06F11/1072
摘要： An Error Control Code (ECC) apparatus applied to a memory of a Multi-Level Cell (MLC) method may include: a bypass control signal generator generating a bypass control signal; and an ECC performing unit that may include at least two ECC decoding blocks, determining whether to bypass a portion of the at least two ECC decoding blocks based on the bypass control signal, and/or performing an ECC decoding. In addition or in the alternative, the ECC performing unit may include at least two ECC encoding blocks, determining whether to bypass a portion of the at least two ECC encoding blocks based on the bypass control signal, and/or performing an ECC encoding. An ECC method applied to a memory of a MLC method and a computer-readable recording medium storing a program for implementing an EEC method applied to a memory of a MLC method are also disclose.
摘要翻译：应用于多电平单元（MLC）方法的存储器的错误控制码（ECC）装置可以包括：旁路控制信号发生器，其生成旁路控制信号; 以及ECC执行单元，其可以包括至少两个ECC解码块，基于旁路控制信号确定是否绕过所述至少两个ECC解码块的一部分，和/或执行ECC解码。另外或在替代方案中，ECC执行单元可以包括至少两个ECC编码块，基于旁路控制信号确定是否绕过至少两个ECC编码块的一部分，和/或执行ECC编码。还公开了应用于MLC方法的存储器的ECC方法和存储用于实现应用于MLC方法的存储器的EEC方法的程序的计算机可读记录介质。

3. 发明授权

US08028215B2 Error control code apparatuses and methods of using the same 有权
标题翻译：错误控制代码设备及其使用方法
公开(公告)号：US08028215B2
公开(公告)日：2011-09-27
申请号：US11905733
申请日：2007-10-03
申请人： Jun Jin Kong , Seung-Hwan Song , Young Hwan Lee , Dong Hyuk Chae , Kyong Lae Cho , Nam Phil Jo , Sung Chung Park , Dong Ku Kang
发明人： Jun Jin Kong , Seung-Hwan Song , Young Hwan Lee , Dong Hyuk Chae , Kyong Lae Cho , Nam Phil Jo , Sung Chung Park , Dong Ku Kang
IPC分类号： H03M13/00 , G06F11/00
CPC分类号： G06F11/1008
摘要： An Error Control Code (ECC) apparatus may include a control signal generator that generates an ECC control signal based on channel information. The ECC apparatus also may include: a plurality of ECC encoding controllers that output data respectively inputted via storage elements corresponding to the ECC control signal; and/or an encoding unit that encodes, using a plurality of data outputted from the plurality of ECC encoding controllers, encoding input data into a number of subdata corresponding to the ECC control signal. In addition or in the alternative, the ECC apparatus may include: a plurality of ECC decoding controllers that output data respectively inputted via the storage elements corresponding to the ECC control signal; and/or a decoding unit that decodes, using a plurality of data outputted from the plurality of ECC decoding controllers, a number of decoding input data corresponding to the ECC control signal into one piece of output data.
摘要翻译：错误控制码（ECC）装置可以包括基于频道信息产生ECC控制信号的控制信号发生器。 ECC装置还可以包括：多个ECC编码控制器，其输出经由与ECC控制信号对应的存储元件分别输入的数据; 和/或编码单元，其使用从所述多个ECC编码控制器输出的多个数据，将输入数据编码为对应于所述ECC控制信号的多个子数据进行编码。另外或者可选地，ECC装置可以包括：多个ECC解码控制器，其输出经由与ECC控制信号对应的存储元件分别输入的数据; 和/或解码单元，其使用从所述多个ECC解码控制器输出的多个数据将对应于所述ECC控制信号的多个解码输入数据解码为一条输出数据。

4. 发明授权

US07706181B2 Multi-bit programming device and method using single-bit memory cells 有权
标题翻译：多位编程设备和使用单位存储单元的方法
公开(公告)号：US07706181B2
公开(公告)日：2010-04-27
申请号：US11896349
申请日：2007-08-31
申请人： Sung-Jae Byun , Dong Hyuk Chae , Kyoung Lae Cho , Jun Jin Kong , Young Hwan Lee , Seung Jae Lee , Nam Phil Jo , Dong Ku Kang
发明人： Sung-Jae Byun , Dong Hyuk Chae , Kyoung Lae Cho , Jun Jin Kong , Young Hwan Lee , Seung Jae Lee , Nam Phil Jo , Dong Ku Kang
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C11/5628 , G11C2211/5621 , G11C2211/5641
摘要： A multi-bit programming device and method for a non-volatile memory are provided. In one example embodiment, a multi-bit programming device may include a multi-bit programming unit configured to multi-bit program original multi-bit data to a target memory cell in a memory cell array, and a backup programming unit configured to select backup memory cells in the memory cell array with respect to each bit of the original multi-bit data, and program each bit of the original multi-bit data to a respective one of the selected backup memory cells.
摘要翻译：提供了一种用于非易失性存储器的多位编程设备和方法。在一个示例实施例中，多位编程设备可以包括多位编程单元，其被配置为将原始多位数据多位地编程到存储单元阵列中的目标存储器单元，以及备份编程单元，被配置为选择备份相对于原始多位数据的每个位存储单元阵列中的存储器单元，以及将原始多位数据的每个位编程到所选择的备份存储器单元中的相应一个。

5. 发明申请

US20080273405A1 Multi-bit programming device and method of multi-bit programming 有权
标题翻译：多位编程设备和多位编程方法
公开(公告)号：US20080273405A1
公开(公告)日：2008-11-06
申请号：US11896349
申请日：2007-08-31
申请人： Sung-Jae Byun , Dong Hyuk Chae , Kyoung Lae Cho , Jun Jin Kong , Young Hwan Lee , Seung Jae Lee , Nam Phil Jo , Dong Ku Kang
发明人： Sung-Jae Byun , Dong Hyuk Chae , Kyoung Lae Cho , Jun Jin Kong , Young Hwan Lee , Seung Jae Lee , Nam Phil Jo , Dong Ku Kang
IPC分类号： G11C7/00
CPC分类号： G11C11/5628 , G11C2211/5621 , G11C2211/5641
摘要： A multi-bit programming device and method for a non-volatile memory are provided. In one example embodiment, a multi-bit programming device may include a multi-bit programming unit configured to multi-bit program original multi-bit data to a target memory cell in a memory cell array, and a backup programming unit configured to select backup memory cells in the memory cell array with respect to each bit of the original multi-bit data, and program each bit of the original multi-bit data to a respective one of the selected backup memory cells.
摘要翻译：提供了一种用于非易失性存储器的多位编程设备和方法。在一个示例实施例中，多位编程设备可以包括多位编程单元，其被配置为将原始多位数据多位地编程到存储单元阵列中的目标存储器单元，以及备份编程单元，被配置为选择备份相对于原始多位数据的每个位存储单元阵列中的存储器单元，以及将原始多位数据的每个位编程到所选择的备份存储器单元中的相应一个。

6. 发明申请

US20090103359A1 Apparatus and method of multi-bit programming 有权
标题翻译：多位编程的装置和方法
公开(公告)号：US20090103359A1
公开(公告)日：2009-04-23
申请号：US12073101
申请日：2008-02-29
申请人： Seung-Hwan SONG , Kyoung Lae Cho , Heeseok Eun , Dong Hyuk Chae , Jun Jin Kong , Sung Chung Park
发明人： Seung-Hwan SONG , Kyoung Lae Cho , Heeseok Eun , Dong Hyuk Chae , Jun Jin Kong , Sung Chung Park
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5642 , G11C16/3418 , G11C2211/5621
摘要： Multi-bit programming apparatuses and/or methods are provided. A multi-bit programming apparatus may comprise: a multi-bit cell array that includes a first multi-bit cell and a second multi-bit cell; a programming unit for programming first data in the first multi-bit cell, and programming second data in the second multi-bit cell; and a verification unit for verifying whether the first data is programmed in the first multi-bit cell using a first verification voltage, and verifying whether the second data is programmed in the second multi-bit cell using a second verification voltage. The multi-bit programming apparatus may generate better threshold voltage distributions in a multi-bit cell memory.
摘要翻译：提供了多位编程设备和/或方法。多比特编程装置可以包括：包括第一多比特小区和第二多比特小区的多比特单元阵列; 编程单元，用于对第一多位单元中的第一数据进行编程，以及编程第二多位单元中的第二数据; 以及验证单元，用于使用第一验证电压来验证第一数据是否被编程在第一多位单元中，以及使用第二验证电压来验证第二数据是否被编程在第二多位单元中。多比特编程装置可以在多比特单元存储器中产生更好的阈值电压分布。

7. 发明申请

US20090046510A1 Apparatus and method for multi-bit programming 审中-公开
标题翻译：多位编程的装置和方法
公开(公告)号：US20090046510A1
公开(公告)日：2009-02-19
申请号：US12007775
申请日：2008-01-15
申请人： Seung-Hwan Song , Jun Jin Kong , Sung Chung Park , Heeseok Eun , Dong Hyuk Chae , Kyoung Lae Cho
发明人： Seung-Hwan Song , Jun Jin Kong , Sung Chung Park , Heeseok Eun , Dong Hyuk Chae , Kyoung Lae Cho
IPC分类号： G11C7/10
CPC分类号： G11C11/5628 , G11C16/0483 , G11C2211/5641
摘要： Multi-bit programming apparatuses and methods are provided. A multi-bit programming apparatus may include: a first programming unit that stores data corresponding to a number of first bits in at least one first memory cell that may be connected to at least one first bit line; and a second programming unit that stores data corresponding to a number of second bits in at least one second memory cell that may be connected to at least one second bit line. Through this, it may be possible to improve data reliability and increase a number of bits to be stored in the entire memory cell.
摘要翻译：提供了多位编程设备和方法。一种多位编程设备可以包括：第一编程单元，其存储对应于可连接到至少一个第一位线的至少一个第一存储器单元中的多个第一位的数据; 以及第二编程单元，其将可能连接到至少一个第二位线的至少一个第二存储器单元中的与第二位数相对应的数据存储。由此，可以提高数据可靠性并增加要存储在整个存储单元中的位数。

8. 发明授权

US08004886B2 Apparatus and method of multi-bit programming 有权
标题翻译：多位编程的装置和方法
公开(公告)号：US08004886B2
公开(公告)日：2011-08-23
申请号：US12073101
申请日：2008-02-29
申请人： Seung-Hwan Song , Kyoung Lae Cho , Heeseok Eun , Dong Hyuk Chae , Jun Jin Kong , Sung Chung Park
发明人： Seung-Hwan Song , Kyoung Lae Cho , Heeseok Eun , Dong Hyuk Chae , Jun Jin Kong , Sung Chung Park
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5642 , G11C16/3418 , G11C2211/5621
摘要： Multi-bit programming apparatuses and/or methods are provided. A multi-bit programming apparatus may comprise: a multi-bit cell array that includes a first multi-bit cell and a second multi-bit cell; a programming unit for programming first data in the first multi-bit cell, and programming second data in the second multi-bit cell; and a verification unit for verifying whether the first data is programmed in the first multi-bit cell using a first verification voltage, and verifying whether the second data is programmed in the second multi-bit cell using a second verification voltage. The multi-bit programming apparatus may generate better threshold voltage distributions in a multi-bit cell memory.
摘要翻译：提供了多位编程设备和/或方法。多比特编程装置可以包括：包括第一多比特小区和第二多比特小区的多比特单元阵列; 编程单元，用于对第一多位单元中的第一数据进行编程，以及编程第二多位单元中的第二数据; 以及验证单元，用于使用第一验证电压来验证第一数据是否被编程在第一多位单元中，以及使用第二验证电压来验证第二数据是否被编程在第二多位单元中。多比特编程装置可以在多比特单元存储器中产生更好的阈值电压分布。

9. 发明授权

US07821828B2 Memory device and memory device heat treatment method 失效
标题翻译：记忆体和记忆体热处理方法
公开(公告)号：US07821828B2
公开(公告)日：2010-10-26
申请号：US12219104
申请日：2008-07-16
申请人： Seung-Hwan Song , Jun Jin Kong , Jae Hong Kim , Young Hwan Lee , Dong Hyuk Chae , Tae Hun Kim , Kyoung Lae Cho
发明人： Seung-Hwan Song , Jun Jin Kong , Jae Hong Kim , Young Hwan Lee , Dong Hyuk Chae , Tae Hun Kim , Kyoung Lae Cho
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C7/04 , G11C11/5621 , G11C16/3427 , G11C16/349 , G11C29/00
摘要： A memory device and a memory device heat treatment method are provided. The memory device may include: a non-volatile memory device; one or more heating devices configured to contact with the non-volatile memory device and heat the non-volatile memory device; and a controller configured to control an operation of the one or more heating devices based on operational information of the non-volatile memory device. Through this, it may be possible to improve an available period of the non-volatile memory device.
摘要翻译：提供了一种存储器件和存储器件热处理方法。存储器件可以包括：非易失性存储器件; 配置成与所述非易失性存储器件接触并加热所述非易失性存储器件的一个或多个加热器件; 以及控制器，被配置为基于所述非易失性存储器件的操作信息来控制所述一个或多个加热装置的操作。由此，可以改善非易失性存储器件的可用周期。

10. 发明申请

US20090201729A1 Memory device and memory device heat treatment method 失效
标题翻译：记忆体和记忆体热处理方法
公开(公告)号：US20090201729A1
公开(公告)日：2009-08-13
申请号：US12219104
申请日：2008-07-16
申请人： Seung-Hwan Song , Jun Jin Kong , Jae Hong Kim , Young Hwan Lee , Dong Hyuk Chae , Tae Hun Kim , Kyoung Lae Cho
发明人： Seung-Hwan Song , Jun Jin Kong , Jae Hong Kim , Young Hwan Lee , Dong Hyuk Chae , Tae Hun Kim , Kyoung Lae Cho
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C7/04 , G11C11/5621 , G11C16/3427 , G11C16/349 , G11C29/00
摘要： A memory device and a memory device heat treatment method are provided. The memory device may include: a non-volatile memory device; one or more heating devices configured to contact with the non-volatile memory device and heat the non-volatile memory device; and a controller configured to control an operation of the one or more heating devices based on operational information of the non-volatile memory device. Through this, it may be possible to improve an available period of the non-volatile memory device.
摘要翻译：提供了一种存储器件和存储器件热处理方法。存储器件可以包括：非易失性存储器件; 配置成与所述非易失性存储器件接触并加热所述非易失性存储器件的一个或多个加热器件; 以及控制器，被配置为基于所述非易失性存储器件的操作信息来控制所述一个或多个加热装置的操作。由此，可以改善非易失性存储器件的可用周期。

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