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51. 发明专利

JP2000349150A SEMICONDUCTOR DEVICE AND MANUFACTURE OF THE SAME 失效
公开(公告)号：JP2000349150A
公开(公告)日：2000-12-15
申请号：JP15875899
申请日：1999-06-04
申请人： HITACHI LTD
发明人： FUKADA SHINICHI , NOJIRI KAZUO , YUNOGAMI TAKASHI , HOTTA SHOJI , AOKI HIDEO , OSHIMA TAKAFUMI , KOBAYASHI NOBUYOSHI
IPC分类号： H01L23/522 , H01L21/3205 , H01L21/3213 , H01L21/768 , H01L23/532
摘要： PROBLEM TO BE SOLVED: To avoid leaving foreign objects in a dual damascene groove (connection hole) so as to improve a semiconductor device in wiring connection reliability and performance. SOLUTION: This manufacturing method is carried out through such a manner where insulating films 34 to 38 are successively formed on a fourth wiring layer 33 (insulating films 34, 36, and 38 are formed of silicon nitride, and insulating films 35 and 37 are formed of silicon oxide), and a groove pattern 40 is transferred onto the insulating film 38 through a photolithography method. A anti-reflection film 41 is formed to be filled into the groove pattern 40 cut in the insulating film 38, and a resist film 42 with a hole pattern 43 is formed. An etching operation is carried out using the resist film 42 as a mask, by which the hole pattern 43 is transferred onto the insulating films 38, 37, 36, and 35. Then, the resist film 42 and the anti-reflection 41 are removed off, and the groove pattern 40 and the hole pattern 43 are each transferred onto the insulating films 37 and 35 using the insulating film 38 as a mask.

52. 发明专利

JP2000340566A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2000340566A
公开(公告)日：2000-12-08
申请号：JP14906399
申请日：1999-05-28
申请人： HITACHI LTD
发明人： YAMADA YOHEI , FUKADA SHINICHI
IPC分类号： H01L21/3205 , H01L21/768
摘要： PROBLEM TO BE SOLVED: To enable reduction of dishings and erosion in a step of polishing a wiring layer other than a wiring layer embedded in a groove for the wiring layer made in an insulation film or the like by a chemical and mechanical polishing(CMP) method. SOLUTION: Prior to the step of making grooves 14 for a wiring layer in an insulating film 9, a step is provided of forming projected steps 12 of a non- photosensitive material in the vicinity of the grooves 14. For example, a step is provided for removing a barrier metal film 15 and a wiring metal layer 16 on the insulating film 9, to form a damascene wiring layer made of the barrier metal film 15 embedded in the grooves 14 and the metal layer 16.

53. 发明专利

JPH11265890A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH11265890A
公开(公告)日：1999-09-28
申请号：JP6649298
申请日：1998-03-17
申请人： HITACHI LTD
发明人： FUKADA SHINICHI
IPC分类号： H01L23/52 , H01L21/28 , H01L21/304 , H01L21/3205 , H01L21/768
摘要： PROBLEM TO BE SOLVED: To facilitate the CMP of Cu/Ta laminated structure, and at the same time to obtain Cu wiring having superior bonding properties with on underlying layer. SOLUTION: An insulating film 2 with an opening is formed on a substrate 1, a titanium film 3 and a tantalum film 4 are laminated on the opening for forming a barrier film, and a copper wiring 5 is formed for collectively polishing and removing the copper wiring 5 and a barrier layer which consists of the titanium film 3 and the tantalum film 4 in one CMP process, thus shortening the process and improving the bonding properties between the substrate and the barrier film.

54. 发明专利

JPH1197648A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH1197648A
公开(公告)日：1999-04-09
申请号：JP25910597
申请日：1997-09-24
申请人： HITACHI LTD
发明人： OYU SHIZUNORI , OKURA OSAMU , SUGIMOTO ARITOSHI , TADAKI YOSHITAKA , OGASAWARA MAKOTO , HORIGUCHI SHINJI , HASEGAWA NORIO , FUKADA SHINICHI
IPC分类号： H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide a technique for realizing a long refresh time of a relief cell of a DRAM, without increasing a chip area greatly and without complicating a process. SOLUTION: The depth of a field-relaxing layer 8r of a relief cell is formed deeper than that of a field-relaxing layer 8 of an ordinary cell, by making the width of a field oxide film 3 in a region, wherein a relief cell is formed larger than the field oxide film 3 in a region where an normal memory cell is formed. Junction electric field is reduced by enlarging a depletion layer of a source and a drain (n-type semiconductor region 7) of a relief cell.

55. 发明专利

JPH1140566A FORMATION OF COPPER WIRING AND COPPER WIRING STRUCTURE 失效
公开(公告)号：JPH1140566A
公开(公告)日：1999-02-12
申请号：JP19620097
申请日：1997-07-22
申请人： HITACHI LTD
发明人： FUKADA SHINICHI , KOBAYASHI NOBUYOSHI , NAGASAWA KOICHI , AKABOSHI HARUO
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/522 , H05K1/03 , H05K3/38 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To form a fine multilayer interconnection at low cost without restricted in terms of material solid state properties of Cu, by finishing all processes required for formation of an insulation film between wirings, etc., in advance, and forming a Cu wiring in a groove (opening part) formed on the insulation film by removing a dummy wiring. SOLUTION: Cu wirings of a first layer and a second layer are formed on a substrate 1. To put it concretely, they are formed by laminating a first base metal layer 2 and a Cu wiring layer 3 on the substrate 1 comprising a plate of Si or ceramic. And a Cu diffusion prevention insulation film 4 is so formed as to cover a side wall thereof, and a space among the Cu wirings 3 is filled with an insulation film 5, to form a first layer wiring. The top surface of the first layer wiring has been flattened, and it is overlaid with a second layer wiring comprising a second base metal layer 6, a second Cu wiring layer 7, a second Cu diffusion prevention insulation film 8 and a second insulation film 9. Wirings above the second layer can be formed by laminating in the same manner.

56. 发明专利

JPH1012568A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH1012568A
公开(公告)日：1998-01-16
申请号：JP16329496
申请日：1996-06-24
申请人： HITACHI LTD
发明人： OYU SHIZUNORI , KAWAMOTO YOSHIFUMI , KOBAYASHI NOBUYOSHI , FUKADA SHINICHI , FUKUDA TAKUYA
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/336 , H01L21/768 , H01L23/52 , H01L23/522 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide shaving of an element-isolating insulation film due to poor alignment in the photolithography or dry over-etching and p-n junction leak. SOLUTION: A silicide layer 14 is formed on the surface of a diffused layer 4 defined by a p-n junction in a region surrounded by an element-isolating insulation film 2. A conductive film 15 is formed on the silicide layer 14 and surrounded by an inter-electrode insulation film 5 formed after forming that film 15. The upper surfaces of both films 15 and 5 are flattened. This simplifies required steps for electric connection to the region defined by the p-n junction, thereby obtaining a semiconductor device having a high reliability with reduced p-n junction leak.

57. 发明专利

JPH09148434A INTERLAYER CONNECTION METHOD FOR WIRING 失效
公开(公告)号：JPH09148434A
公开(公告)日：1997-06-06
申请号：JP31031895
申请日：1995-11-29
申请人： HITACHI LTD
发明人： FUKADA SHINICHI , GOSHIMA HIDEKAZU , NAKANISHI SHIGEHIKO , KOBAYASHI NOBUYOSHI
IPC分类号： H01L21/28 , H01L21/324 , H01L21/768 , H01L23/522
摘要： PROBLEM TO BE SOLVED: To stop a deeper connection hole with wiring metal by high-pressure stopping art so as to take interlayer connection, by making an interlayer insulating film have the three layer structure of upper, intermediate, and lower layers, and making the intermediate layer have a thickness half or over the whole of the interlayer insulating film, and besides, making the bore of the connection hole largest at the intermediate layer. SOLUTION: There is a wiring layer patterned already on a substrate 1, and thereon an interlayer insulating film 9 is made. This interlayer insulating film 9 consists of the three layers of an upper layer 8, an intermediate layer 7, and a lower layer 6. The thickness of the interlayer insulating film 9 is not equal within the board 1, but at least in the opening area of the connection hole 10, the intermediate layer 7 is the thickest. Especially, the intermediate layer 7 has a thickness of not less than 50% and not more than 90% of the whole interlayer insulating film 9. That is, this means that the thickness of the intermediate layer 7 accounting for of the whole of the interlayer insulating film 9 requires 50% or more at the least. Hereby, it becomes possible to take an interlayer insulating film 9 by stopping the deep connection hole with wiring metal by high-pressure stopping art, without providing a pad metallic layer.

58. 发明专利

JPH08288386A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH08288386A
公开(公告)日：1996-11-01
申请号：JP9216795
申请日：1995-04-18
申请人： HITACHI LTD
发明人： FUKADA SHINICHI , HIRASAWA MASANARI
IPC分类号： H01L23/522 , H01L21/203 , H01L21/324 , H01L21/768 , H01L29/78 , H01L29/786
摘要： PURPOSE: To make a diffused layer surface conductive and low in resistance without causing an increase of a leak current in P-N junction, by a method wherein the thickness of a conductor layer formed selectively by diffusing an element into a substrate is varied and thereby the layer is made to have a specified film thickness distribution. CONSTITUTION: At least a part of regions of a semiconductor substrate 1 of which the surface is divided into the regions in a plurality, of which the circumferences are partitioned by an insulating film 2, is covered with a conductor layer 9 formed selectively by diffusing an element into the substrate 1. In a semiconductor device constructed in this way, the thickness of the conductor layer 9 is varied according to a distance (r) from the outer periphery of the conductor layer 9, and one substrate region wherein an average thickness d(r1 ) of the conductor layer 9 at the distance (r)=r1 is d(r1 )>d(r2 ) in relation to the average thickness d(r2 ) at (r)=r2 (r1

59. 发明专利

JPH0621234A THIN FILM MULTILAYER INTERCONNECTION AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH0621234A
公开(公告)日：1994-01-28
申请号：JP20020292
申请日：1992-07-06
申请人： HITACHI LTD
发明人： FUKADA SHINICHI , SUWA MOTOHIRO , KUDO KAZUE , MINEMURA TETSUO
IPC分类号： H01L23/522 , H01L21/768 , H01L21/90
摘要： PURPOSE:To provide thin film multilayer interconnections having an interconnection structure for obtaining reliability of a connecting part of through hole interconnection to a lower interconnection layer and simultaneously effective to prevent peeling of an interconnection from an insulating layer at a periphery of a through hole and a method for forming the same. CONSTITUTION:Multilayer interconnections formed on a substrate and having a lower interconnection layer 11, an interlayer insulating layer 53, an upper interconnection layer 51 and a through hole interconnection 10 are formed by sequentially forming the layers 11, 10 and then sequentially forming a mask layer for the through hole interconnection and a lower interconnection pattern layer of different materials by photolithography technique. Further, after a lower interconnection pattern is transferred to the through hole interconnection layer by etching technique, only the lower interconnection pattern layer is removed, the layer 11 is formed by etching with the transferred lower interconnection pattern as a mask and the interconnection 10 is formed by etching with a mask layer for the through hole interconnection as a mask, and formed in a structure in which a connecting surface of different metals is isolated from a bottom of the through hole and having a reverse tapered through hole interconnection.

60. 发明专利

JPH05144811A THIN FILM SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH05144811A
公开(公告)日：1993-06-11
申请号：JP30800691
申请日：1991-11-22
申请人： HITACHI LTD
发明人： KUDO KAZUE , FUKADA SHINICHI , SUWA MOTOHIRO
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522
摘要： PURPOSE:To solve the problem of film exfoliation of wiring due to film stress and the wire disconnection and the like due to stress migration by a method wherein an insulating film is formed without oxidizing the wiring in a semiconductor device having the wiring consisting of Cu or the alloy mainly composed of Cu. CONSTITUTION:A wiring layer 1, consisting of Cu or an alloy mainly composed of Cu, is formed on the thermally oxidized SiO2, film 5 formed on the surface of an Si substrate 4, then an insulating film, consisting of a non-oxidized layer 2, and an oxide film 3, which is thicker than the insulating film, are formed successively from the side of the wiring layer 1.

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