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51. 发明申请

US20070262395A1 Memory cell access devices and methods of making the same 审中-公开
标题翻译：存储单元访问设备及其制作方法
公开(公告)号：US20070262395A1
公开(公告)日：2007-11-15
申请号：US11432442
申请日：2006-05-11
申请人： Jasper Gibbons , Darren Young , Kunal Parekh , Casey Smith
发明人： Jasper Gibbons , Darren Young , Kunal Parekh , Casey Smith
IPC分类号： H01L29/94
CPC分类号： H01L29/4236 , H01L21/823425 , H01L21/82345 , H01L29/407 , H01L29/66621 , H01L29/7831
摘要： Planar access transistor devices and recessed access transistor devices used with semiconductor devices may include gate electrodes having materials with multiple work functions, materials that are electrically isolated from each other and supplied with two or more voltage supplies, or materials that create a diode junction within the gate electrode. Access device drivers are also provided which are capable of driving distinct or identical voltages to the gate electrodes.
摘要翻译：与半导体器件一起使用的平面存取晶体管器件和凹槽存取晶体管器件可以包括具有多个功函数的材料的栅电极，彼此电隔离并且被提供有两个或更多个电压源的材料，或在其内产生二极管结的材料栅电极。还提供了能够驱动与栅电极不同或相同电压的访问设备驱动器。

52. 发明授权

US07265016B2 Stepped gate configuration for non-volatile memory 有权
公开(公告)号：US07265016B2
公开(公告)日：2007-09-04
申请号：US11257637
申请日：2005-10-25
申请人： H. Montgomery Manning , Kunal Parekh
发明人： H. Montgomery Manning , Kunal Parekh
IPC分类号： H01L21/336
CPC分类号： H01L21/28282 , G11C16/0416 , G11C16/0483 , H01L29/7923
摘要： A memory device having a field effect transistor with a stepped gate dielectric and a method of making the same are herein disclosed. The stepped gate dielectric is formed on a semiconductor substrate and consists of a pair of charge trapping dielectrics separated by a gate dielectric; a gate conductor is formed thereover. Source and drain areas are formed in the semiconductor substrate on opposing sides of the pair of charge trapping dielectrics. The memory device is made by forming a charge trapping dielectric layer on a semiconductor substrate. A trench is formed through the charge trapping dielectric layer to expose a portion of the semiconductor substrate. A gate dielectric layer is formed within the trench and a gate conductor layer is formed over the charge trapping and gate dielectric layers.

53. 发明申请

US20060240637A1 Methods of forming semiconductor constructions 失效
公开(公告)号：US20060240637A1
公开(公告)日：2006-10-26
申请号：US11472950
申请日：2006-06-21
申请人： Kunal Parekh , Chandra Mouli , M. Roberts , Fernando Gonzalez
发明人： Kunal Parekh , Chandra Mouli , M. Roberts , Fernando Gonzalez
IPC分类号： H01L21/76 , H01L21/31
CPC分类号： H01L21/76801 , H01L21/76829 , H01L21/76834 , H01L21/823462 , H01L21/823481 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/785
摘要： The invention includes methods of forming and/or passivating semiconductor constructions. In particular aspects, various oxides of a semiconductor substrate can be formed by exposing semiconductive material of the substrate to deuterium-enriched steam. In other aspects, a semiconductor construction is passivated by subjecting the construction to an anneal at a temperature of greater than or equal to 350° C. while exposing the construction to a deuterium-enriched ambient.

54. 发明申请

US20060097327A1 Low resistance semiconductor process and structures 有权
公开(公告)号：US20060097327A1
公开(公告)日：2006-05-11
申请号：US11305598
申请日：2005-12-16
申请人： Michael Hermes , Kunal Parekh
发明人： Michael Hermes , Kunal Parekh
IPC分类号： H01L29/76
CPC分类号： H01L21/76897 , H01L21/31111 , H01L21/31116 , H01L21/76889 , H01L21/823425 , H01L21/823475
摘要： A process for forming a semiconductor device comprises the steps of providing a semiconductor substrate assembly comprising a semiconductor wafer having an active area formed therein, a plurality of transistor gates each having a TEOS cap thereon and a pair of nitride spacers along each gate, a plurality of conductive plugs each contacting the wafer, and a BPSG layer overlying the transistor gates and contacting the active area. A portion of the BPSG layer is etched thereby exposing the TEOS caps. A portion of the BPSG layer remains on the active area after completion of the etch. Subsequently, a portion of the TEOS caps are removed to expose the transistor gates and a titanium silicide layer is formed simultaneously to contact the transistor gates and the plugs. An inventive structure resulting from the inventive process is also described.

55. 发明申请

US20060092726A1 Memory redundancy programming 有权
公开(公告)号：US20060092726A1
公开(公告)日：2006-05-04
申请号：US11299868
申请日：2005-12-12
申请人： Kunal Parekh
发明人： Kunal Parekh
IPC分类号： G11C29/00
CPC分类号： G11C17/18 , G11C29/789
摘要： A method and apparatus is provided for performing a redundancy programming. The system of the present invention includes a device testing unit for performing a memory test. The system also includes a memory device operatively coupled to the device testing unit. The memory device includes an access transistor that includes a charge trapping area. A threshold voltage of the access transistor is modified upon trapping of charges in the charge trapping unit. The memory device also includes a memory element and a fuse associated with the memory element. The fuse is capable of entering an alternative state in response to modifying the threshold voltage of the access transistor. The state of the fuse may be used to program or de-program the memory element.

56. 发明申请

US20060082004A1 Methods of forming memory circuitry 有权
公开(公告)号：US20060082004A1
公开(公告)日：2006-04-20
申请号：US11292028
申请日：2005-12-01
申请人： Kunal Parekh , Byron Burgess
发明人： Kunal Parekh , Byron Burgess
IPC分类号： H01L23/58
CPC分类号： H01L21/76897 , H01L21/76831 , H01L21/76834 , H01L21/76895 , H01L27/10814 , H01L27/10855 , H01L27/10888 , H01L27/10894 , Y10S257/905 , Y10S257/906 , Y10S257/907
摘要： The invention includes methods of forming memory circuitry. In one implementation, a semiconductor substrate includes a pair of word lines having a bit node received therebetween. A bit node contact opening is formed within insulative material over the bit node. Sacrificial plugging material is formed within the bit node contact opening between the pair of word lines. Sacrificial plugging material is removed from the bit node contact opening between the pair of word lines, and it is replaced with conductive material that is in electrical connection with the bit node. Thereafter, the conductive material is formed into a bit line.

57. 发明申请

US20060043466A1 Stepped gate configuration for non-volatile memory 有权
公开(公告)号：US20060043466A1
公开(公告)日：2006-03-02
申请号：US11257636
申请日：2005-10-25
申请人： H. Manning , Kunal Parekh
发明人： H. Manning , Kunal Parekh
IPC分类号： H01L29/788
CPC分类号： H01L21/28282 , G11C16/0416 , G11C16/0483 , H01L29/7923
摘要： A memory device having a field effect transistor with a stepped gate dielectric and a method of making the same are herein disclosed. The stepped gate dielectric is formed on a semiconductor substrate and consists of a pair of charge trapping dielectrics separated by a gate dielectric; a gate conductor is formed thereover. Source and drain areas are formed in the semiconductor substrate on opposing sides of the pair of charge trapping dielectrics. The memory device is made by forming a charge trapping dielectric layer on a semiconductor substrate. A trench is formed through the charge trapping dielectric layer to expose a portion of the semiconductor substrate. A gate dielectric layer is formed within the trench and a gate conductor layer is formed over the charge trapping and gate dielectric layers.

58. 发明申请

US20050207215A1 Methods of forming memory circuitry 失效
标题翻译：形成存储器电路的方法
公开(公告)号：US20050207215A1
公开(公告)日：2005-09-22
申请号：US11135534
申请日：2005-05-23
申请人： Kunal Parekh , Byron Burgess
发明人： Kunal Parekh , Byron Burgess
IPC分类号： G11C11/00 , H01L21/60 , H01L21/8234 , H01L21/8242 , H01L27/108
CPC分类号： H01L21/76897 , H01L21/76831 , H01L21/76834 , H01L21/76895 , H01L27/10814 , H01L27/10855 , H01L27/10888 , H01L27/10894 , Y10S257/905 , Y10S257/906 , Y10S257/907
摘要： The invention includes methods of forming memory circuitry. In one implementation, a semiconductor substrate includes a pair of word lines having a bit node received therebetween. A bit node contact opening is formed within insulative material over the bit node. Sacrificial plugging material is formed within the bit node contact opening between the pair of word lines. Sacrificial plugging material is removed from the bit node contact opening between the pair of word lines, and it is replaced with conductive material that is in electrical connection with the bit node. Thereafter, the conductive material is formed into a bit line.
摘要翻译：本发明包括形成存储器电路的方法。在一个实施方案中，半导体衬底包括一对在其间接收的位节点的字线。在位节点上的绝缘材料内形成位节点接触开口。牺牲性封堵材料形成在一对字线之间的位节点接触开口内。牺牲性封堵材料从一对字线对之间的位节点接触开口移除，并由与位节点电连接的导电材料代替。之后，将导电材料形成为位线。

59. 发明申请

US20050181567A1 Double blanket ion implant method and structure 审中-公开
标题翻译：双层离子注入法和结构
公开(公告)号：US20050181567A1
公开(公告)日：2005-08-18
申请号：US11094377
申请日：2005-03-31
申请人： Mark Fischer , Charles Dennison , Fawad Ahmed , Richard Lane , John Zahurak , Kunal Parekh
发明人： Mark Fischer , Charles Dennison , Fawad Ahmed , Richard Lane , John Zahurak , Kunal Parekh
IPC分类号： H01L21/265 , H01L21/28 , H01L21/336 , H01L21/8234 , H01L21/8244
CPC分类号： H01L21/2652 , H01L21/2658 , H01L21/28247 , H01L29/6656 , H01L29/6659
摘要： A double blanket ion implant method for forming diffulsion regions in memory array devices, such as a MOSFET access device is disclosed. The method provides a semiconductor substrate with a gate structure formed on its surface Next, a first pair of diffulsion regions are formed in a region adjacent to the channel region by a first blanket ion implantation process. The first blanket ion implantation process has a first energy level and dose. The device is subjected to oxidizing conditions, which form oxidized sidewalls on the gate structure. A second blanket ion implantation process is conducted at the same location as the first ion implantation process adding additional dopant to the diffusion regions. The second blanket ion implantation process has a second energy level and dose. The resultant diffusion regions provide the device with improved static refresh performance over prior art devices. In addition, the first and second energy levels and doses are substantially lower than an energy level and dose used in a prior art single implantation process.
摘要翻译：公开了一种用于在诸如MOSFET访问装置的存储器阵列器件中形成差分区域的双层离子注入方法。该方法提供了在其表面上形成栅极结构的半导体衬底。接下来，通过第一覆盖离子注入工艺在与沟道区相邻的区域中形成第一对差分区域。第一次毯式离子注入工艺具有第一能级和剂量。该器件经受氧化条件，其在栅极结构上形成氧化的侧壁。在与第一离子注入工艺相同的位置处进行第二覆盖离子注入工艺，向扩散区域添加额外的掺杂剂。第二次毯子离子注入过程具有第二能量水平和剂量。所得到的扩散区域提供了比现有技术的装置更好的静态刷新性能的装置。此外，第一和第二能量水平和剂量基本上低于现有技术单一植入过程中使用的能级和剂量。

60. 发明授权

US6043119A Method of making a capacitor 失效
标题翻译：制作电容器的方法
公开(公告)号：US6043119A
公开(公告)日：2000-03-28
申请号：US906213
申请日：1997-08-04
申请人： Zhiqiang Wu , Kunal Parekh , Li Li
发明人： Zhiqiang Wu , Kunal Parekh , Li Li
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L27/10852 , H01L28/82
摘要： The present invention is directed to fabrication of a capacitor formed with a substantially concave shape and having optional folded or convoluted surfaces. The concave shape optimizes surface area within a small volume and thereby enables the capacitor to hold a significant charge so as to assist in increased miniaturization efforts in the microelectronic field. The capacitor is fabricated in microelectronic fashion consistent with a dense DRAM array. Methods of fabrication include stack building with storage nodes that extend above a semiconductor substrate surface.
摘要翻译：本发明涉及一种电容器的制造，该电容器形成为具有大致凹入形状且具有可选择的折叠或回旋表面。凹形形状在小体积内优化表面积，从而使电容器能够保持大量电荷，从而有助于微电子领域中的增加的小型化努力。电容器以与电致密DRAM阵列一致的微电子方式制造。制造方法包括具有在半导体衬底表面上方延伸的存储节点的堆叠构造。

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