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51. 发明申请

US20130330903A1 MANUFACTURABLE HIGH-K DRAM MIM CAPACITOR STRUCTURE 有权
标题翻译：可制造的高K DRAM MIM电容结构
公开(公告)号：US20130330903A1
公开(公告)日：2013-12-12
申请号：US13494808
申请日：2012-06-12
申请人： Sandra Malhotra , Wim Deweerd , Ode Hiroyuki
发明人： Sandra Malhotra , Wim Deweerd , Ode Hiroyuki
IPC分类号： H01L21/02
CPC分类号： H01L28/56 , H01L27/10852 , H01L28/60 , H01L28/90
摘要： A method for forming a capacitor stack is described. In some embodiments of the present invention, a first dielectric material is formed above a first electrode material. The first electrode material is rigid and has good mechanical strength and serves as a robust frame for the capacitor stack. The first dielectric material is sufficiently thin ( 3 nm) or lightly doped or non-doped so that it crystallizes after subsequent anneal treatments. A second electrode material is formed adjacent to the second dielectric material. The second electrode material has a high work function and a crystal structure that serves to promote the formation of the high k-value crystal structure of the second dielectric material.
摘要翻译：描述形成电容器堆叠的方法。在本发明的一些实施例中，第一电介质材料形成在第一电极材料之上。第一电极材料是刚性的并且具有良好的机械强度并且用作用于电容器叠层的坚固框架。第一介电材料足够薄（ 3nm）或轻掺杂或未掺杂，使得其在随后的退火处理之后结晶。与第二电介质材料相邻地形成第二电极材料。第二电极材料具有高功函数和用于促进形成第二电介质材料的高k值晶体结构的晶体结构。

52. 发明申请

US20130122681A1 TOP ELECTRODE TEMPLATING FOR DRAM CAPACITOR 有权
标题翻译：用于DRAM电容器的顶电极温度
公开(公告)号：US20130122681A1
公开(公告)日：2013-05-16
申请号：US13294309
申请日：2011-11-11
申请人： Sandra Malhotra , Hanhong Chen , Wim Deweerd , Hiroyuki Ode
发明人： Sandra Malhotra , Hanhong Chen , Wim Deweerd , Hiroyuki Ode
IPC分类号： H01L21/02
CPC分类号： H01L28/40 , H01L21/02186 , H01L21/02194 , H01L21/0228 , H01L21/02304 , H01L21/02356 , H01L27/10852 , H01L28/75
摘要： A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. A metal oxide second electrode layer is formed above the dielectric layer. The metal oxide second electrode layer has a crystal structure that is compatible with the crystal structure of the dielectric layer. Optionally, a second electrode bulk layer is formed above the metal oxide second electrode layer.
摘要翻译：用于形成具有低泄漏电流的DRAM MIM电容器堆叠的方法涉及使用用作促进随后沉积的介电层的高k相的模板的第一电极。高k电介质层包括可在随后的退火处理后结晶的掺杂材料。金属氧化物第二电极层形成在电介质层的上方。金属氧化物第二电极层具有与介电层的晶体结构相容的晶体结构。可选地，在金属氧化物第二电极层上形成第二电极体层。

53. 发明授权

US08415657B2 Enhanced work function layer supporting growth of rutile phase titanium oxide 有权
公开(公告)号：US08415657B2
公开(公告)日：2013-04-09
申请号：US12942238
申请日：2010-11-09
申请人： Xiangxin Rui , Pragati Kumar , Hanhong Chen , Sandra Malhotra
发明人： Xiangxin Rui , Pragati Kumar , Hanhong Chen , Sandra Malhotra
IPC分类号： H01L29/06 , H01L29/10 , H01L23/48 , H01L23/52 , H01L21/00
CPC分类号： H01L21/02 , B82Y99/00 , C01G23/047 , C01P2002/72 , C23C16/0272 , C23C16/34 , C23C16/405 , C23C16/45525 , H01L21/02186 , H01L21/0228 , H01L27/1085 , H01L28/40
摘要： This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor and DRAM cell. In particular, a bottom electrode has a material selected for lattice matching characteristics. This material may be created from a relatively inexpensive metal oxide which is processed to adopt a conductive, but difficult-to-produce oxide state, with specific crystalline form; to provide one example, specific materials are disclosed that are compatible with the growth of rutile phase titanium dioxide (TiO2) for use as a dielectric, thereby leading to predictable and reproducible higher dielectric constant and lower effective oxide thickness and, thus, greater part density at lower cost.

54. 发明申请

US20130071987A1 Band Gap Improvement In DRAM Capacitors 有权
标题翻译： DRAM电容器带隙改进
公开(公告)号：US20130071987A1
公开(公告)日：2013-03-21
申请号：US13237065
申请日：2011-09-20
申请人： Hanhong Chen , Sandra Malhotra , Wim Deweerd , Hiroyuki Ode
发明人： Hanhong Chen , Sandra Malhotra , Wim Deweerd , Hiroyuki Ode
IPC分类号： H01L21/02
CPC分类号： H01L28/40 , H01L21/02178 , H01L21/02181 , H01L21/02186 , H01L21/02189 , H01L21/02194 , H01L21/0228 , H01L27/1085 , H01L28/60
摘要： A method for forming a DRAM MIM capacitor stack having low leakage current and low EOT involves the use of an compound high k dielectric material. The dielectric material further comprises a dopant. One component of the compound high k dielectric material is present in a concentration between about 30 atomic % and about 80 atomic % and more preferably between about 40 atomic % and about 60 atomic %. In some embodiments, the compound high k dielectric material comprises an alloy of TiO2 and ZrO2 and further comprises a dopant of Al2O3. In some embodiments, the compound high k dielectric material comprises an admixture of TiO2 and HfO2 and further comprises a dopant of Al2O3.
摘要翻译：用于形成具有低漏电流和低EOT的DRAM MIM电容器堆叠的方法涉及使用复合高k电介质材料。电介质材料还包括掺杂剂。复合高k介电材料的一个组分以约30原子％至约80原子％，更优选约40原子％至约60原子％的浓度存在。在一些实施方案中，化合物高k介电材料包含TiO 2和ZrO 2的合金，并且还包含Al 2 O 3的掺杂剂。在一些实施方案中，化合物高k介电材料包含TiO 2和HfO 2的混合物，并且还包含Al 2 O 3的掺杂剂。

55. 发明申请

US20120235276A1 ELECTRODE TREATMENTS FOR ENHANCED DRAM PERFORMANCE 审中-公开
标题翻译：用于增强DRAM性能的电极处理
公开(公告)号：US20120235276A1
公开(公告)日：2012-09-20
申请号：US13051531
申请日：2011-03-18
申请人： Xiangxin Rui , Hanhong Chen , Edward Haywood , Sandra Malhotra , Takashi Arao , Naonori Fujiwara , Toshiyuki Hirota , Takakazu Kiyomura , Kenichi Koyanagi
发明人： Xiangxin Rui , Hanhong Chen , Edward Haywood , Sandra Malhotra , Takashi Arao , Naonori Fujiwara , Toshiyuki Hirota , Takakazu Kiyomura , Kenichi Koyanagi
IPC分类号： H01L29/02 , H01L21/02
CPC分类号： H01L28/60 , H01L21/02 , H01L27/1085 , H01L28/40
摘要： A method for fabricating a dynamic random access memory capacitor is disclosed. The method may comprise depositing a first titanium nitride (TiN) electrode; creating a first layer of titanium dioxide (TiO2) on the first TiN electrode; depositing a dielectric material on the first layer of titanium dioxide; and depositing a second TiN electrode on the dielectric material.
摘要翻译：公开了一种用于制造动态随机存取存储器电容器的方法。该方法可以包括沉积第一氮化钛（TiN）电极; 在第一TiN电极上形成第一层二氧化钛（TiO 2）; 在第一层二氧化钛上沉积电介质材料; 以及在所述电介质材料上沉积第二TiN电极。

56. 发明申请

US20120156889A1 METHODS FOR FORMING HIGH-K CRYSTALLINE FILMS AND RELATED DEVICES 有权
标题翻译：用于形成高K晶体薄膜和相关器件的方法
公开(公告)号：US20120156889A1
公开(公告)日：2012-06-21
申请号：US13334618
申请日：2011-12-22
申请人： Hanhong Chen , Edward Haywood , Pragati Kumar , Sandra Malhotra , Xiangxin Rui
发明人： Hanhong Chen , Edward Haywood , Pragati Kumar , Sandra Malhotra , Xiangxin Rui
IPC分类号： H01L21/316
CPC分类号： H01L28/40 , H01L21/02186 , H01L21/02189 , H01L21/0228 , H01L28/56 , H01L28/60
摘要： This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor or DRAM cell. In such a device, a high-K zirconia-based layer may be used as the primary dielectric together with a relatively inexpensive metal electrode based on titanium nitride. To prevent corruption of the electrode during device formation, a thin barrier layer can be used seal the electrode prior to the use of a high temperature process and a (high-concentration or dosage) ozone reagent (i.e., to create a high-K zirconia-based layer). In some embodiments, the barrier layer can also be zirconia-based, for example, a thin layer of doped or un-doped amorphous zirconia. Fabrication of a device in this manner facilitates formation of a device with dielectric constant of greater than 40 based on zirconia and titanium nitride, and generally helps produce less costly, increasingly dense DRAM cells and other semiconductor structures.
摘要翻译：本公开提供了制造半导体堆叠和相关联的器件（诸如电容器或DRAM单元）的方法。在这种器件中，高K氧化锆基层可以与基于氮化钛的相对廉价的金属电极一起用作主要电介质。为了防止在器件形成期间电极的损坏，可以使用薄的阻挡层，在使用高温工艺和（高浓度或剂量）的臭氧试剂之前密封电极（即，产生高K氧化锆基层）。在一些实施例中，阻挡层也可以是基于氧化锆的，例如掺杂或未掺杂的无定形氧化锆的薄层。以这种方式制造器件有助于基于氧化锆和氮化钛形成具有大于40的介电常数的器件，并且通常有助于产生更便宜的，越来越致密的DRAM电池和其它半导体结构。

57. 发明申请

US20110151136A1 METHODS FOR DEPOSITING HIGH-K DIELECTRICS 有权
标题翻译：沉积高K电介质的方法
公开(公告)号：US20110151136A1
公开(公告)日：2011-06-23
申请号：US13039819
申请日：2011-03-03
申请人： Xiangxin Rui , Sunil Shanker , Sandra Malhotra , Imran Hashim , Edward Haywood
发明人： Xiangxin Rui , Sunil Shanker , Sandra Malhotra , Imran Hashim , Edward Haywood
IPC分类号： B05D3/06 , B05D3/02 , B05D5/12
CPC分类号： H01L21/3141 , C23C16/02 , C23C16/405 , H01L21/02186 , H01L21/02271 , H01L21/02315 , H01L21/31604 , H01L28/91
摘要： Methods for depositing high-K dielectrics are described, including depositing a first electrode on a substrate, wherein the first electrode is chosen from the group consisting of platinum and ruthenium, applying an oxygen plasma treatment to the exposed metal to reduce the contact angle of a surface of the metal, and depositing a titanium oxide layer on the exposed metal using at least one of a chemical vapor deposition process and an atomic layer deposition process, wherein the titanium oxide layer comprises at least a portion rutile titanium oxide.
摘要翻译：描述了用于沉积高K电介质的方法，包括在衬底上沉积第一电极，其中第一电极选自铂和钌，对暴露的金属施加氧等离子体处理以减小接触角并且使用化学气相沉积工艺和原子层沉积工艺中的至少一种在暴露的金属上沉积氧化钛层，其中所述氧化钛层包含至少一部分金红石型氧化钛。

58. 发明申请

US20100001269A1 Methods of Combinatorial Processing for Screening Multiple Samples on a Semiconductor Substrate 有权
标题翻译：在半导体基板上筛选多个样品的组合处理方法
公开(公告)号：US20100001269A1
公开(公告)日：2010-01-07
申请号：US12167118
申请日：2008-07-02
申请人： Gaurav Verma , Kurt Weiner , Prashant Phatak , Imran Hashim , Sandra Malhotra , Tony Chiang
发明人： Gaurav Verma , Kurt Weiner , Prashant Phatak , Imran Hashim , Sandra Malhotra , Tony Chiang
IPC分类号： C23C16/00 , H01L21/66 , H01L23/58
CPC分类号： G01R31/2831 , G01R31/2834 , H01L22/34
摘要： In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.
摘要翻译：在本发明的实施例中，描述了用于这些方法的组合处理方法和测试芯片。这些方法和测试芯片能够有效地开发用于半导体制造工艺的材料，工艺和工艺顺序集成方案。通常，这些方法简化了在测试芯片上形成器件或部分形成的器件的处理顺序，使得器件可以在形成后立即进行测试。即时测试允许测试芯片上各种材料，工艺或工艺顺序的高通量测试。测试芯片具有多个位置隔离区域，其中每个区域彼此变化，并且测试芯片被设计为能够实现不同区域的高通量测试。

59. 发明申请

US20070222066A1 STRUCTURE AND METHOD OF FORMING ELECTRODEPOSITED CONTACTS 有权
标题翻译：形成电沉积联系的结构和方法
公开(公告)号：US20070222066A1
公开(公告)日：2007-09-27
申请号：US11308433
申请日：2006-03-24
申请人： Cyril Cabral , Hariklia Deligianni , Randolph Knarr , Sandra Malhotra , Stephen Rossnagel , Xiaoyan Shao , Anna Topol , Philippe Vereecken
发明人： Cyril Cabral , Hariklia Deligianni , Randolph Knarr , Sandra Malhotra , Stephen Rossnagel , Xiaoyan Shao , Anna Topol , Philippe Vereecken
IPC分类号： H01L23/48
CPC分类号： H01L23/485 , H01L21/2885 , H01L21/76843 , H01L21/76846 , H01L21/76877 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： A contact metallurgy structure comprising a patterned dielectric layer having cavities on a substrate; a silicide or germanide layer such as of cobalt and/or nickel located at the bottom of cavities; a contact layer comprising Ti or Ti/TiN located on top of the dielectric layer and inside the cavities and making contact to the silicide or germanide layer on the bottom; a diffusion barrier layer located on top of the contact layer and inside the cavities; optionally a seed layer for plating located on top of the barrier layer; a metal fill layer in vias is provided along with a method of fabrication. The metal fill layer is electrodeposited with at least one member selected from the group consisting of copper, rhodium, ruthenium, iridium, molybdenum, gold, silver, nickel, cobalt, silver, gold, cadmium and zinc and alloys thereof. When the metal fill layer is rhodium, ruthenium, or iridium, an effective diffusion barrier layer is not required between the fill metal and the dielectric. When the barrier layer is platable, such as ruthenium, rhodium, platinum, or iridium, the seed layer is not required.
摘要翻译：一种接触式冶金结构，包括在基底上具有空腔的图案化电介质层; 位于空腔底部的硅化物或锗化物层，例如钴和/或镍; 接触层，其包含位于介电层顶部并且在空腔内并与底部的硅化物或锗化物层接触的Ti或Ti / TiN; 位于所述接触层顶部和所述空腔内的扩散阻挡层; 可选地，位于阻挡层顶部的用于电镀的种子层; 提供通孔中的金属填充层以及制造方法。金属填充层用选自铜，铑，钌，铱，钼，金，银，镍，钴，银，金，镉和锌中的至少一种电池和其合金电沉积。当金属填充层是铑，钌或铱时，在填充金属和电介质之间不需要有效的扩散阻挡层。当阻挡层是可镀的，例如钌，铑，铂或铱时，不需要种子层。

60. 发明授权

US08828836B2 Method for fabricating a DRAM capacitor 有权
标题翻译：制造DRAM电容器的方法
公开(公告)号：US08828836B2
公开(公告)日：2014-09-09
申请号：US13153626
申请日：2011-06-06
申请人： Karthik Ramani , Hiroyuki Ode , Sandra Malhotra
发明人： Karthik Ramani , Hiroyuki Ode , Sandra Malhotra
IPC分类号： H01L21/20 , H01L49/02 , H01L29/92
CPC分类号： H01L28/40 , H01L28/60 , H01L28/65 , H01L29/92
摘要： A method for fabricating a dynamic random access memory (DRAM) capacitor stack is disclosed wherein the stack includes a first electrode, a dielectric layer, and a second electrode. The first electrode is formed from a conductive binary metal. A dielectric layer is formed over the first electrode. The dielectric layer is subjected to a milliseconds anneal process that serves to crystallize the dielectric material and decrease the concentration of oxygen vacancies.
摘要翻译：公开了一种用于制造动态随机存取存储器（DRAM）电容器堆叠的方法，其中堆叠包括第一电极，电介质层和第二电极。第一电极由导电二元金属形成。在第一电极上形成电介质层。对电介质层进行几毫秒的退火工艺，以使介电材料结晶并降低氧空位的浓度。

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