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1. 发明授权

US08828836B2 Method for fabricating a DRAM capacitor 有权
标题翻译：制造DRAM电容器的方法
公开(公告)号：US08828836B2
公开(公告)日：2014-09-09
申请号：US13153626
申请日：2011-06-06
申请人： Karthik Ramani , Hiroyuki Ode , Sandra Malhotra
发明人： Karthik Ramani , Hiroyuki Ode , Sandra Malhotra
IPC分类号： H01L21/20 , H01L49/02 , H01L29/92
CPC分类号： H01L28/40 , H01L28/60 , H01L28/65 , H01L29/92
摘要： A method for fabricating a dynamic random access memory (DRAM) capacitor stack is disclosed wherein the stack includes a first electrode, a dielectric layer, and a second electrode. The first electrode is formed from a conductive binary metal. A dielectric layer is formed over the first electrode. The dielectric layer is subjected to a milliseconds anneal process that serves to crystallize the dielectric material and decrease the concentration of oxygen vacancies.
摘要翻译：公开了一种用于制造动态随机存取存储器（DRAM）电容器堆叠的方法，其中堆叠包括第一电极，电介质层和第二电极。第一电极由导电二元金属形成。在第一电极上形成电介质层。对电介质层进行几毫秒的退火工艺，以使介电材料结晶并降低氧空位的浓度。

2. 发明申请

US20120262835A1 METHOD FOR FABRICATING A DRAM CAPACITOR 有权
标题翻译：制造DRAM电容器的方法
公开(公告)号：US20120262835A1
公开(公告)日：2012-10-18
申请号：US13084666
申请日：2011-04-12
申请人： Karthik Ramani , Nobumichi Fuchigami , Wim Deweerd , Hanhong Chen , Hiroyuki Ode
发明人： Karthik Ramani , Nobumichi Fuchigami , Wim Deweerd , Hanhong Chen , Hiroyuki Ode
IPC分类号： H01L21/02 , H01G4/008
CPC分类号： H01L28/40 , H01G4/1218 , H01G4/33 , H01L28/60 , H01L28/75 , Y10T29/43 , Y10T29/435 , Y10T29/49002
摘要： A method for fabricating a dynamic random access memory (DRAM) capacitor stack is disclosed wherein the stack includes a first electrode, a dielectric layer, and a second electrode. The first electrode is formed from a conductive binary metal compound and the conductive binary metal compound is annealed in a reducing atmosphere to promote the formation of a desired crystal structure. The binary metal compound may be a metal oxide. Annealing the metal oxide (i.e. molybdenum oxide) in a reducing atmosphere may result in the formation of a first electrode material (i.e. MoO2) with a rutile-phase crystal structure. This facilitates the formation of the rutile-phase crystal structure when TiO2 is used as the dielectric layer. The rutile-phase of TiO2 has a higher k value than the other possible crystal structures of TiO2 resulting in improved performance of the DRAM capacitor.
摘要翻译：公开了一种用于制造动态随机存取存储器（DRAM）电容器堆叠的方法，其中堆叠包括第一电极，电介质层和第二电极。第一电极由导电二元金属化合物形成，并且导电二元金属化合物在还原气氛中退火以促进所需晶体结构的形成。二元金属化合物可以是金属氧化物。在还原气氛中退火金属氧化物（即氧化钼）可导致形成具有金红石相晶体结构的第一电极材料（即MoO 2）。当使用TiO 2作为电介质层时，这有助于金红石相晶体结构的形成。 TiO 2的金红石相具有比其他可能的TiO 2晶体结构更高的k值，从而改善了DRAM电容器的性能。

3. 发明授权

US08813325B2 Method for fabricating a DRAM capacitor 有权
标题翻译：制造DRAM电容器的方法
公开(公告)号：US08813325B2
公开(公告)日：2014-08-26
申请号：US13084666
申请日：2011-04-12
申请人： Karthik Ramani , Nobumichi Fuchigami , Wim Deweerd , Hanhong Chen , Hiroyuki Ode
发明人： Karthik Ramani , Nobumichi Fuchigami , Wim Deweerd , Hanhong Chen , Hiroyuki Ode
IPC分类号： H01G7/00 , H01G4/12 , H01G4/33 , H01L49/02
CPC分类号： H01L28/40 , H01G4/1218 , H01G4/33 , H01L28/60 , H01L28/75 , Y10T29/43 , Y10T29/435 , Y10T29/49002
摘要： A method for fabricating a dynamic random access memory (DRAM) capacitor stack is disclosed wherein the stack includes a first electrode, a dielectric layer, and a second electrode. The first electrode is formed from a conductive binary metal compound and the conductive binary metal compound is annealed in a reducing atmosphere to promote the formation of a desired crystal structure. The binary metal compound may be a metal oxide. Annealing the metal oxide (i.e. molybdenum oxide) in a reducing atmosphere may result in the formation of a first electrode material (i.e. MoO2) with a rutile-phase crystal structure. This facilitates the formation of the rutile-phase crystal structure when TiO2 is used as the dielectric layer. The rutile-phase of TiO2 has a higher k value than the other possible crystal structures of TiO2 resulting in improved performance of the DRAM capacitor.
摘要翻译：公开了一种用于制造动态随机存取存储器（DRAM）电容器堆叠的方法，其中堆叠包括第一电极，电介质层和第二电极。第一电极由导电二元金属化合物形成，导电二元金属化合物在还原气氛中退火以促进所需晶体结构的形成。二元金属化合物可以是金属氧化物。在还原气氛中退火金属氧化物（即氧化钼）可导致形成具有金红石相晶体结构的第一电极材料（即MoO 2）。当使用TiO 2作为电介质层时，这有助于金红石相晶体结构的形成。 TiO 2的金红石相具有比其他可能的TiO 2晶体结构更高的k值，从而改善了DRAM电容器的性能。

4. 发明授权

US08574983B2 Method for fabricating a DRAM capacitor having increased thermal and chemical stability 有权
标题翻译：制造具有增加的热和化学稳定性的DRAM电容器的方法
公开(公告)号：US08574983B2
公开(公告)日：2013-11-05
申请号：US13107081
申请日：2011-05-13
申请人： Karthik Ramani , Wim Deweerd , Hiroyuki Ode
发明人： Karthik Ramani , Wim Deweerd , Hiroyuki Ode
IPC分类号： H01L21/8242 , H01L21/8244 , H01L21/8234
CPC分类号： H01G4/33 , H01G4/008 , H01G4/306 , H01L28/75
摘要： A method for fabricating a dynamic random access memory (DRAM) capacitor includes forming a first electrode film. The first electrode film comprises a conductive binary metal compound and a dopant. The dopant may have a uniform or non-uniform concentration within the first electrode film. A high-k dielectric film is formed over the first electrode film. A second electrode film is formed over the dielectric film. The second electrode film comprises a conductive binary metal compound and a dopant. The dopant may have a uniform or non-uniform concentration within the second electrode film. The dopants and their distribution are chosen so that the crystal structure of the surface of the electrode is not degraded if the electrode is to be used as a templating structure for subsequent layer formation. Additionally, the dopants and their distribution are chosen so that the work function of the electrodes is not degraded.
摘要翻译：一种用于制造动态随机存取存储器（DRAM）电容器的方法包括形成第一电极膜。第一电极膜包括导电二元金属化合物和掺杂剂。掺杂剂可以在第一电极膜内具有均匀或不均匀的浓度。在第一电极膜上形成高k电介质膜。在绝缘膜上形成第二电极膜。第二电极膜包括导电二元金属化合物和掺杂剂。掺杂剂可以在第二电极膜内具有均匀或不均匀的浓度。选择掺杂剂及其分布，使得如果将电极用作后续层形成的模板结构，则电极表面的晶体结构不会降解。此外，选择掺杂剂及其分布使得电极的功函数不降解。

5. 发明申请

US20120287553A1 METHOD FOR FABRICATING A DRAM CAPACITOR HAVING INCREASED THERMAL AND CHEMICAL STABILITY 有权
标题翻译：制造具有增加的热和化学稳定性的DRAM电容器的方法
公开(公告)号：US20120287553A1
公开(公告)日：2012-11-15
申请号：US13107081
申请日：2011-05-13
申请人： Karthik Ramani , Wim Deweerd , Hiroyuki Ode
发明人： Karthik Ramani , Wim Deweerd , Hiroyuki Ode
IPC分类号： H01G4/30 , H01G7/00
CPC分类号： H01G4/33 , H01G4/008 , H01G4/306 , H01L28/75
摘要： A method for fabricating a dynamic random access memory (DRAM) capacitor includes forming a first electrode film. The first electrode film comprises a conductive binary metal compound and a dopant. The dopant may have a uniform or non-uniform concentration within the first electrode film. A high-k dielectric film is formed over the first electrode film. A second electrode film is formed over the dielectric film. The second electrode film comprises a conductive binary metal compound and a dopant. The dopant may have a uniform or non-uniform concentration within the second electrode film. The dopants and their distribution are chosen so that the crystal structure of the surface of the electrode is not degraded if the electrode is to be used as a templating structure for subsequent layer formation. Additionally, the dopants and their distribution are chosen so that the work function of the electrodes is not degraded.
摘要翻译：一种用于制造动态随机存取存储器（DRAM）电容器的方法包括形成第一电极膜。第一电极膜包括导电二元金属化合物和掺杂剂。掺杂剂可以在第一电极膜内具有均匀或不均匀的浓度。在第一电极膜上形成高k电介质膜。在绝缘膜上形成第二电极膜。第二电极膜包括导电二元金属化合物和掺杂剂。掺杂剂可以在第二电极膜内具有均匀或不均匀的浓度。选择掺杂剂及其分布，使得如果将电极用作后续层形成的模板结构，则电极表面的晶体结构不会降解。此外，选择掺杂剂及其分布使得电极的功函数不降解。

6. 发明申请

US20130122681A1 TOP ELECTRODE TEMPLATING FOR DRAM CAPACITOR 有权
标题翻译：用于DRAM电容器的顶电极温度
公开(公告)号：US20130122681A1
公开(公告)日：2013-05-16
申请号：US13294309
申请日：2011-11-11
申请人： Sandra Malhotra , Hanhong Chen , Wim Deweerd , Hiroyuki Ode
发明人： Sandra Malhotra , Hanhong Chen , Wim Deweerd , Hiroyuki Ode
IPC分类号： H01L21/02
CPC分类号： H01L28/40 , H01L21/02186 , H01L21/02194 , H01L21/0228 , H01L21/02304 , H01L21/02356 , H01L27/10852 , H01L28/75
摘要： A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. A metal oxide second electrode layer is formed above the dielectric layer. The metal oxide second electrode layer has a crystal structure that is compatible with the crystal structure of the dielectric layer. Optionally, a second electrode bulk layer is formed above the metal oxide second electrode layer.
摘要翻译：用于形成具有低泄漏电流的DRAM MIM电容器堆叠的方法涉及使用用作促进随后沉积的介电层的高k相的模板的第一电极。高k电介质层包括可在随后的退火处理后结晶的掺杂材料。金属氧化物第二电极层形成在电介质层的上方。金属氧化物第二电极层具有与介电层的晶体结构相容的晶体结构。可选地，在金属氧化物第二电极层上形成第二电极体层。

7. 发明申请

US20130071987A1 Band Gap Improvement In DRAM Capacitors 有权
标题翻译： DRAM电容器带隙改进
公开(公告)号：US20130071987A1
公开(公告)日：2013-03-21
申请号：US13237065
申请日：2011-09-20
申请人： Hanhong Chen , Sandra Malhotra , Wim Deweerd , Hiroyuki Ode
发明人： Hanhong Chen , Sandra Malhotra , Wim Deweerd , Hiroyuki Ode
IPC分类号： H01L21/02
CPC分类号： H01L28/40 , H01L21/02178 , H01L21/02181 , H01L21/02186 , H01L21/02189 , H01L21/02194 , H01L21/0228 , H01L27/1085 , H01L28/60
摘要： A method for forming a DRAM MIM capacitor stack having low leakage current and low EOT involves the use of an compound high k dielectric material. The dielectric material further comprises a dopant. One component of the compound high k dielectric material is present in a concentration between about 30 atomic % and about 80 atomic % and more preferably between about 40 atomic % and about 60 atomic %. In some embodiments, the compound high k dielectric material comprises an alloy of TiO2 and ZrO2 and further comprises a dopant of Al2O3. In some embodiments, the compound high k dielectric material comprises an admixture of TiO2 and HfO2 and further comprises a dopant of Al2O3.
摘要翻译：用于形成具有低漏电流和低EOT的DRAM MIM电容器堆叠的方法涉及使用复合高k电介质材料。电介质材料还包括掺杂剂。复合高k介电材料的一个组分以约30原子％至约80原子％，更优选约40原子％至约60原子％的浓度存在。在一些实施方案中，化合物高k介电材料包含TiO 2和ZrO 2的合金，并且还包含Al 2 O 3的掺杂剂。在一些实施方案中，化合物高k介电材料包含TiO 2和HfO 2的混合物，并且还包含Al 2 O 3的掺杂剂。

8. 发明授权

US08765570B2 Manufacturable high-k DRAM MIM capacitor structure 有权
标题翻译：可制造的高k DRAM MIM电容器结构
公开(公告)号：US08765570B2
公开(公告)日：2014-07-01
申请号：US13494808
申请日：2012-06-12
申请人： Sandra Malhotra , Wim Deweerd , Hiroyuki Ode
发明人： Sandra Malhotra , Wim Deweerd , Hiroyuki Ode
IPC分类号： H01L21/20
CPC分类号： H01L28/56 , H01L27/10852 , H01L28/60 , H01L28/90
摘要： A method for forming a capacitor stack is described. In some embodiments of the present invention, a first dielectric material is formed above a first electrode material. The first electrode material is rigid and has good mechanical strength and serves as a robust frame for the capacitor stack. The first dielectric material is sufficiently thin ( 3 nm) or lightly doped or non-doped so that it crystallizes after subsequent anneal treatments. A second electrode material is formed adjacent to the second dielectric material. The second electrode material has a high work function and a crystal structure that serves to promote the formation of the high k-value crystal structure of the second dielectric material.
摘要翻译：描述形成电容器堆叠的方法。在本发明的一些实施例中，第一电介质材料形成在第一电极材料之上。第一电极材料是刚性的并且具有良好的机械强度并且用作用于电容器叠层的坚固框架。第一介电材料足够薄（<2nm）或高度掺杂，使得在随后的退火处理之后其保持非晶态。在第一电介质材料上方形成第二电介质材料。第二介电材料足够厚（> 3nm）或轻掺杂或未掺杂，使得其在随后的退火处理之后结晶。与第二电介质材料相邻地形成第二电极材料。第二电极材料具有高功函数和用于促进形成第二电介质材料的高k值晶体结构的晶体结构。

9. 发明授权

US08574998B2 Leakage reduction in DRAM MIM capacitors 有权
标题翻译： DRAM MIM电容器的漏电减少
公开(公告)号：US08574998B2
公开(公告)日：2013-11-05
申请号：US13311368
申请日：2011-12-05
申请人： Sandra Malhotra , Kenichi Koyanagi , Hiroyuki Ode , Xiangxin Rui , Takashi Arao , Naonori Fujiwara
发明人： Sandra Malhotra , Kenichi Koyanagi , Hiroyuki Ode , Xiangxin Rui , Takashi Arao , Naonori Fujiwara
IPC分类号： H01L21/02
CPC分类号： H01L28/40 , H01G4/1272 , H01G4/306 , H01G4/33 , H01L21/02175 , H01L21/02189 , H01L21/02192 , H01L21/02194 , H01L21/022 , H01L21/0228
摘要： A method for reducing the leakage current in DRAM MIM capacitors comprises forming a multi-layer dielectric stack from an amorphous highly doped material, an amorphous high band gap material, and a lightly or non-doped material. The highly doped material will remain amorphous (
摘要翻译：用于减少DRAM MIM电容器中的漏电流的方法包括从非晶高掺杂材料，非晶高带隙材料以及轻掺杂或非掺杂材料形成多层电介质叠层。退火步骤后，高掺杂材料将保持无定形（<30％结晶）。在退火步骤之后，高带隙材料将保持无定形（<30％结晶）。在退火步骤之后，轻掺杂或非掺杂材料将变成晶体（> = 30％结晶）。高带隙材料形成在无定形高掺杂材料和轻掺杂材料和非掺杂材料之间，并提供通过多层电介质叠层的导电的中间屏障。

10. 发明授权

US08563392B2 Method of forming an ALD material 有权
标题翻译：形成ALD材料的方法
公开(公告)号：US08563392B2
公开(公告)日：2013-10-22
申请号：US13310980
申请日：2011-12-05
申请人： Sandra Malhotra , Wim Deweerd , Edward Haywood , Hiroyuki Ode
发明人： Sandra Malhotra , Wim Deweerd , Edward Haywood , Hiroyuki Ode
IPC分类号： H01L21/02
CPC分类号： C23C16/45534 , C23C16/405 , H01L21/28562 , H01L21/32051 , H01L28/60
摘要： In some embodiments of the present invention, methods are developed wherein a gas flow of an electron donating compound (EDC) is introduced in sequence with a precursor pulse and alters the deposition of the precursor material. In some embodiments, the EDC pulse is introduced sequentially with the precursor pulse with a purge step used to remove the non-adsorbed EDC from the process chamber before the precursor is introduced. In some embodiments, the EDC pulse is introduced using a vapor draw technique or a bubbler technique. In some embodiments, the EDC pulse is introduced in the same gas distribution manifold as the precursor pulse. In some embodiments, the EDC pulse is introduced in a separate gas distribution manifold from the precursor pulse.
摘要翻译：在本发明的一些实施方案中，开发了一种方法，其中给电子化合物（EDC）的气流按前驱脉冲依次导入并改变前体材料的沉积。在一些实施方案中，EDC脉冲依次与前体脉冲一起引入，其中吹扫步骤用于在引入前体之前从处理室去除未吸附的EDC。在一些实施例中，使用蒸汽抽吸技术或起泡器技术引入EDC脉冲。在一些实施例中，EDC脉冲被引入与前驱脉冲相同的气体分配歧管中。在一些实施例中，EDC脉冲从前驱脉冲引入到单独的气体分配歧管中。

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