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51. 发明授权

US08455308B2 Fully-depleted SON 失效
标题翻译：完全耗尽的SON
公开(公告)号：US08455308B2
公开(公告)日：2013-06-04
申请号：US13048977
申请日：2011-03-16
申请人： Kangguo Cheng , Bruce Doris , Pranita Kulkarni , Ghavam Shahidi
发明人： Kangguo Cheng , Bruce Doris , Pranita Kulkarni , Ghavam Shahidi
IPC分类号： H01L21/00 , H01L21/76
CPC分类号： H01L29/786 , H01L29/66772 , H01L29/78654 , H01L29/78696
摘要： A semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes a semiconductor substrate, an insulating layer, a first semiconductor layer, a dielectric layer, a second semiconductor layer, a source and drain junction, a gate, and a spacer. The method includes the steps of forming a semiconductor substrate, forming a shallow trench isolation layer, growing a first epitaxial layer, growing a second epitaxial layer, forming a gate, forming a spacer, performing a reactive ion etching, removing a portion of the first epitaxial layer, filling the void with a dielectric, etching back a portion of the dielectric, growing a silicon layer, implanting a source and drain junction, and forming an extension.
摘要翻译：半导体器件和半导体器件的制造方法。半导体器件包括半导体衬底，绝缘层，第一半导体层，电介质层，第二半导体层，源极和漏极结，栅极和间隔物。该方法包括以下步骤：形成半导体衬底，形成浅沟槽隔离层，生长第一外延层，生长第二外延层，形成栅极，形成间隔物，执行反应离子蚀刻，去除第一外延层，用电介质填充空隙，蚀刻电介质的一部分，生长硅层，注入源极和漏极结，以及形成延伸。

52. 发明授权

US08324074B2 Structure and method to minimize regrowth and work function shift in high-k gate stacks 有权
标题翻译：最小化高k栅极堆叠中的再生长和功函数移位的结构和方法
公开(公告)号：US08324074B2
公开(公告)日：2012-12-04
申请号：US12557934
申请日：2009-09-11
申请人： Kangguo Cheng , Bruce Doris , Pranita Kulkarni
发明人： Kangguo Cheng , Bruce Doris , Pranita Kulkarni
IPC分类号： H01L21/76 , H01L29/06 , H01L21/762
CPC分类号： H01L29/0649 , H01L21/76224
摘要： The present invention provides a semiconductor structure comprising high-k material portions that are self-aligned with respect to the active areas in the semiconductor substrate and a method of fabricating the same. The high-k material is protected from oxidation during the fabrication of the semiconductor structure and regrowth of the high-k material and shifting of the high-k material work function is prevented.
摘要翻译：本发明提供了包括相对于半导体衬底中的有源区自对准的高k材料部分的半导体结构及其制造方法。在制造半导体结构期间，高k材料被保护免受氧化，并且高k材料的再生长并且防止了高k材料功函数的移位。

53. 发明申请

US20120235238A1 FULLY-DEPLETED SON 失效
标题翻译：充分的SON
公开(公告)号：US20120235238A1
公开(公告)日：2012-09-20
申请号：US13048977
申请日：2011-03-16
申请人： Kangguo Cheng , Bruce Doris , Pranita Kulkarni , Ghavam Shahidi
发明人： Kangguo Cheng , Bruce Doris , Pranita Kulkarni , Ghavam Shahidi
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/786 , H01L29/66772 , H01L29/78654 , H01L29/78696
摘要： A semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes a semiconductor substrate, an insulating layer, a first semiconductor layer, a dielectric layer, a second semiconductor layer, a source and drain junction, a gate, and a spacer. The method includes the steps of forming a semiconductor substrate, forming a shallow trench isolation layer, growing a first epitaxial layer, growing a second epitaxial layer, forming a gate, forming a spacer, performing a reactive ion etching, removing a portion of the first epitaxial layer, filling the void with a dielectric, etching back a portion of the dielectric, growing a silicon layer, implanting a source and drain junction, and forming an extension.
摘要翻译：半导体器件和半导体器件的制造方法。半导体器件包括半导体衬底，绝缘层，第一半导体层，电介质层，第二半导体层，源极和漏极结，栅极和间隔物。该方法包括以下步骤：形成半导体衬底，形成浅沟槽隔离层，生长第一外延层，生长第二外延层，形成栅极，形成间隔物，执行反应离子蚀刻，去除第一外延层，用电介质填充空隙，蚀刻电介质的一部分，生长硅层，注入源极和漏极结，以及形成延伸。

54. 发明申请

US20110316083A1 FET with Self-Aligned Back Gate 有权
标题翻译：具有自对准后门的FET
公开(公告)号：US20110316083A1
公开(公告)日：2011-12-29
申请号：US12823798
申请日：2010-06-25
申请人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni
发明人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66545 , H01L29/78648
摘要： A back-gated field effect transistor (FET) includes a substrate, the substrate comprising top semiconductor layer on top of a buried dielectric layer on top of a bottom semiconductor layer; a front gate located on the top semiconductor layer; a channel region located in the top semiconductor layer under the front gate; a source region located in the top semiconductor layer on a side of the channel region, and a drain region located in the top semiconductor layer on the side of the channel region opposite the source regions; and a back gate located in the bottom semiconductor layer, the back gate configured such that the back gate abuts the buried dielectric layer underneath the channel region, and is separated from the buried dielectric layer by a separation distance underneath the source region and the drain region.
摘要翻译：背栅式场效应晶体管（FET）包括衬底，该衬底包括位于底部半导体层顶部的掩埋电介质层顶部的顶部半导体层; 位于顶部半导体层上的前门; 位于前门下的顶部半导体层中的沟道区; 位于沟道区一侧的顶部半导体层中的源极区域和位于与源极区域相反的沟道区域侧的顶部半导体层中的漏极区域; 以及位于底部半导体层中的背栅，后栅配置成使得后栅极邻接沟道区下方的掩埋介电层，并且在源极区和漏极区之下与掩埋介电层分离距离。

55. 发明申请

US20080090366A1 Hybrid SOI-Bulk Semiconductor Transistors 失效
标题翻译：混合SOI-体半导体晶体管
公开(公告)号：US20080090366A1
公开(公告)日：2008-04-17
申请号：US11870436
申请日：2007-10-11
申请人： Huilong Zhu , Philip Oldiges , Bruce Doris , Xinlin Wang , Oleg Gluschenkov , Huajie Chen , Ying Zhang
发明人： Huilong Zhu , Philip Oldiges , Bruce Doris , Xinlin Wang , Oleg Gluschenkov , Huajie Chen , Ying Zhang
IPC分类号： H01L21/336
CPC分类号： H01L29/7849 , H01L29/0653 , H01L29/1054 , H01L29/7842 , H01L29/78603 , H01L29/78612 , H01L29/78618 , H01L29/78687
摘要： Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.
摘要翻译：场效应晶体管中的沟道深度由包括在半导体材料的层或衬底内形成的不连续膜或层的层内结构限制。因此，可以以SOI或UT-SOI技术的方式控制通道深度，但是具有较便宜的衬底和更大的通道深度控制的灵活性，同时避免SOI技术的浮体效应特性。不连续膜的轮廓或横截面形状可以被控制为奥格或阶梯形状，以改善短通道效应，并且在不增加电容的情况下降低源极/漏极和延伸电阻。也可以选择用于不连续膜的材料以在衬底或层内从晶体管沟道施加应力，并提供增加的这种应力水平以增加载流子迁移率。携带者的流动性可能会与其他有利的影响相结合。

56. 发明申请

US20080020521A1 HYBRID SUBSTRATE TECHNOLOGY FOR HIGH-MOBILITY PLANAR AND MULTIPLE-GATE MOSFETS 有权
标题翻译：混合基板技术用于高移动平面和多栅极MOSFET
公开(公告)号：US20080020521A1
公开(公告)日：2008-01-24
申请号：US11866786
申请日：2007-10-03
申请人： Bruce Doris , Meikei Ieong , Edward Nowak , Min Yang
发明人： Bruce Doris , Meikei Ieong , Edward Nowak , Min Yang
IPC分类号： H01L21/84
CPC分类号： H01L21/76251 , H01L21/76243 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/045 , H01L29/785
摘要： A hybrid substrate having a high-mobility surface for use with planar and/or multiple-gate metal oxide semiconductor field effect transistors (MOSFETs) is provided. The hybrid substrate has a first surface portion that is optimal for n-type devices, and a second surface portion that is optimal for p-type devices. Due to proper surface and wafer flat orientations in each semiconductor layers of the hybrid substrate, all gates of the devices are oriented in the same direction and all channels are located on the high mobility surface. The present invention also provides for a method of fabricating the hybrid substrate as well as a method of integrating at least one planar or multiple-gate MOSFET thereon.
摘要翻译：提供了具有用于平面和/或多栅极金属氧化物半导体场效应晶体管（MOSFET）的高迁移率表面的混合衬底。混合基板具有对于n型器件是最佳的第一表面部分和对于p型器件是最佳的第二表面部分。由于混合衬底的每个半导体层中的适当的表面和晶片平坦取向，器件的所有栅极被定向在相同的方向上，并且所有沟道都位于高迁移率表面上。本发明还提供了一种制造混合衬底的方法以及在其上集成至少一个平面或多栅极MOSFET的方法。

57. 发明申请

US20070262361A1 STRUCTURE AND METHOD FOR MANUFACTURING STRAINED SILICON DIRECTLY-ON-INSULATOR SUBSTRATE WITH HYBRID CRYSTALLINE ORIENTATION AND DIFFERENT STRESS LEVELS 有权
标题翻译：用混合晶体取向和不同应力水平制造具有应力的硅直接绝缘体衬底的结构和方法
公开(公告)号：US20070262361A1
公开(公告)日：2007-11-15
申请号：US11830464
申请日：2007-07-30
申请人： Huilong Zhu , Bruce Doris , Huajie Chen , Patricia Mooney , Stephen Bedell
发明人： Huilong Zhu , Bruce Doris , Huajie Chen , Patricia Mooney , Stephen Bedell
IPC分类号： H01L27/092
CPC分类号： H01L27/1203 , H01L21/76254 , H01L21/823807 , H01L21/823878 , H01L21/84
摘要： The present invention provides a strained Si directly on insulator (SSDOI) substrate having multiple crystallographic orientations and a method of forming thereof. Broadly, but in specific terms, the inventive SSDOI substrate includes a substrate; an insulating layer atop the substrate; and a semiconducting layer positioned atop and in direct contact with the insulating layer, the semiconducting layer comprising a first strained Si region and a second strained Si region; wherein the first strained Si region has a crystallographic orientation different from the second strained Si region and the first strained Si region has a crystallographic orientation the same or different from the second strained Si region. The strained level of the first strained Si region is different from that of the second strained Si region.
摘要翻译：本发明提供了具有多个结晶取向的应变Si直接绝缘体（SSDOI）基板及其形成方法。广义上，但是具体来说，本发明的SSDOI基板包括基板; 衬底顶部的绝缘层; 以及位于顶部并与绝缘层直接接触的半导体层，所述半导体层包括第一应变Si区和第二应变Si区; 其中所述第一应变Si区具有不同于所述第二应变Si区的晶体取向，并且所述第一应变Si区具有与所述第二应变Si区相同或不同的晶体取向。第一应变Si区域的应变水平与第二应变Si区域的应变水平不同。

58. 发明申请

US20070181930A1 Structure and method of making double-gated self-aligned finfet having gates of different lengths 有权
标题翻译：制作具有不同长度的门的双门控自对准finfet的结构和方法
公开(公告)号：US20070181930A1
公开(公告)日：2007-08-09
申请号：US10711182
申请日：2004-08-31
申请人： Huilong Zhu , Bruce Doris , Xinlin Wang , Jochen Beintner , Ying Zhang , Philip Oldiges
发明人： Huilong Zhu , Bruce Doris , Xinlin Wang , Jochen Beintner , Ying Zhang , Philip Oldiges
IPC分类号： H01L27/108
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/7855 , H01L29/7856
摘要： A gated semiconductor device is provided, in which the body has a first dimension extending in a lateral direction parallel to a major surface of a substrate, and second dimension extending in a direction at least substantially vertical and at least substantially perpendicular to the major surface, the body having a first side and a second side opposite the first side. The gated semiconductor device includes a first gate overlying the first side, and having a first gate length in the lateral direction. The gated semiconductor device further includes a second gate overlying the second side, the second gate having a second gate length in the lateral direction which is different from, and preferably shorter than the first gate length. In one embodiment, the first gate and the second gate being electrically isolated from each other. In another embodiment the first gate consists essentially of polycrystalline silicon germanium and the second gate consists essentially of polysilicon.
摘要翻译：提供了门控半导体器件，其中主体具有在平行于衬底的主表面的横向方向上延伸的第一尺寸，以及在至少基本上垂直且至少基本垂直于主表面的方向上延伸的第二尺寸，所述主体具有与所述第一侧相对的第一侧和第二侧。门控半导体器件包括覆盖第一侧的第一栅极，并且在横向上具有第一栅极长度。门控半导体器件还包括覆盖第二侧的第二栅极，第二栅极在横向上具有不同于第一栅极长度的第二栅极长度，并且优选地短于第一栅极长度。在一个实施例中，第一栅极和第二栅极彼此电隔离。在另一个实施例中，第一栅极主要由多晶硅锗组成，第二栅极主要由多晶硅组成。

59. 发明申请

US20070132039A1 Method and structure for strained FinFET devices 有权
标题翻译：应变FinFET器件的方法和结构
公开(公告)号：US20070132039A1
公开(公告)日：2007-06-14
申请号：US11701377
申请日：2007-02-02
申请人： Bruce Doris , Diane Boyd , Huilong Zhu
发明人： Bruce Doris , Diane Boyd , Huilong Zhu
IPC分类号： H01L29/76 , H01L29/94 , H01L29/84
CPC分类号： H01L29/785 , H01L29/41733 , H01L29/458 , H01L29/66795 , H01L29/7842
摘要： A method (and structure) of forming an electronic device includes forming at least one localized stressor region within the device.
摘要翻译：形成电子器件的方法（和结构）包括在器件内形成至少一个局部应力源区域。

60. 发明申请

US20070090487A1 Method for tuning epitaxial growth by interfacial doping and structure including same 有权
标题翻译：通过界面掺杂和包括其的结构来调谐外延生长的方法
公开(公告)号：US20070090487A1
公开(公告)日：2007-04-26
申请号：US11259654
申请日：2005-10-26
申请人： Katherina Babich , Bruce Doris , David Medeiros , Devendra Sadana
发明人： Katherina Babich , Bruce Doris , David Medeiros , Devendra Sadana
IPC分类号： H01L21/76 , H01L31/11
CPC分类号： H01L29/0847 , H01L21/2236 , H01L21/2256 , H01L21/26513 , H01L21/823418 , H01L21/823814 , H01L29/66628 , H01L29/7834
摘要： A method that allows for uniform, simultaneous epitaxial growth of a semiconductor material on dissimilarly doped semiconductor surfaces (n-type and p-type) that does not impart substrate thinning via a novel surface preparation scheme, as well as a structure that results from the implementation of this scheme into the process integration flow for integrated circuitry are provided. The method of the present invention can by used for the selective or nonselective epitaxial growth of semiconductor material from the dissimilar surfaces. More specifically, the invention comprises a method for counterdoping of n-FET and/or p-FET regions of silicon circuitry during the halo and/or extension implantation process utilizing a technique by which the surface characteristics of the two regions are made similar with respect to their response to wet or dry surface preparation and which renders the two previously dissimilar surfaces amenable to simultaneous epitaxial growth of raised source/drain structures; but not otherwise affecting the electrical performance of the resulting device.
摘要翻译：允许通过新颖的表面制备方案不使衬底变薄的不同掺杂的半导体表面（n型和p型）上的半导体材料均匀地同时外延生长的方法，以及由提供了将该方案实现为集成电路的过程集成流程。本发明的方法可以用于从不同的表面进行半导体材料的选择性或非选择性外延生长。更具体地说，本发明包括一种在卤素和/或延伸注入过程期间用于对硅电路的n-FET和/或p-FET区进行反掺杂的方法，利用这样的技术，使两个区域的表面特性相对于它们对湿表面或干表面制备的反应，并且使得两个先前不同的表面可以容易地升高的源极/漏极结构的同时外延生长; 但不会影响所得设备的电气性能。

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