专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US08008669B2 Programmable anti-fuse structure with DLC dielectric layer 失效
标题翻译：具有DLC介质层的可编程反熔丝结构
公开(公告)号：US08008669B2
公开(公告)日：2011-08-30
申请号：US12509892
申请日：2009-07-27
申请人： Chih-Chao Yang , David V. Horak , Takeshi Nogami , Shom Ponoth
发明人： Chih-Chao Yang , David V. Horak , Takeshi Nogami , Shom Ponoth
IPC分类号： H01L29/15
CPC分类号： H01L23/5252 , H01L23/53276 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment an anti-fuse structure is provided that includes a first dielectric material having at least a first anti-fuse region and a second anti-fuse region, wherein at least one of the anti-fuse regions includes a conductive region embedded within the first dielectric material. The anti-fuse structure further includes a first diamond like carbon layer having a first conductivity located on at least the first dielectric material in the first anti-fuse region and a second diamond like carbon layer having a second conductivity located on at least the first dielectric material in the second anti-fuse region. In this embodiment, the second conductivity is different from the first conductivity and the first diamond like carbon layer and the second diamond like carbon layer have the same thickness. The anti-fuse structure also includes a second dielectric material located atop the first and second diamond like carbon layers. The second dielectric material includes at least one conductively filled region embedded therein.
摘要翻译：在一个实施例中，提供了一种抗熔丝结构，其包括具有至少第一抗熔融区域和第二抗熔融区域的第一电介质材料，其中至少一个反熔丝区域包括嵌入在该熔断区域内的导电区域第一电介质材料。反熔丝结构还包括第一金刚石碳层，其具有位于第一抗熔融区域中的至少第一电介质材料上的第一导电性，第二类金刚石碳层具有位于至少第一电介质上的第二导电性材料在第二个反熔丝区域。在本实施例中，第二导电率不同于第一导电性，第一类金刚石碳层和第二类金刚石碳层具有相同的厚度。反熔丝结构还包括位于第一和第二金刚石状碳层顶上的第二电介质材料。第二电介质材料包括嵌入其中的至少一个导电填充区域。

52. 发明申请

US20110163450A1 INTEGRATED CIRCUIT LINE WITH ELECTROMIGRATION BARRIERS 失效
标题翻译：集成电路与电气障碍
公开(公告)号：US20110163450A1
公开(公告)日：2011-07-07
申请号：US12652485
申请日：2010-01-05
申请人： David V. Horak , Takeshi Nogami , Shom Ponoth , Chih-Chao Yang
发明人： David V. Horak , Takeshi Nogami , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L23/50 , H01L21/768
CPC分类号： H01L23/53238 , H01L21/76834 , H01L21/76847 , H01L21/76852 , H01L21/76885 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating an integrated circuit comprising an electromigration barrier in a line of the integrated circuit includes forming a spacer; forming a segmented line adjacent to opposing sides of the spacer, the segmented line formed from a first conductive material; removing the spacer to form an empty line break; and filling the empty line break with a second conductive material to form an electromigration barrier that isolates electromigration effects within individual segments of the segmented line. An integrated circuit comprising an electromigration barrier includes a line, the line comprising a first conductive material, the line further comprising a plurality of line segments separated by one or more electromigration barriers, wherein the one or more electromigration barriers comprise a second conductive material that isolates electromigration effects within individual segments of the line.
摘要翻译：一种用于制造集成电路的集成电路的方法，包括：集成电路的一行中的电迁移势垒包括形成间隔物; 形成与所述间隔物的相对侧相邻的分段线，所述分段线由第一导电材料形成; 移除间隔物以形成空线断裂; 并用第二导电材料填充空线断裂以形成电隔离屏蔽，其隔离分段线的各个段内的电迁移效应。包括电迁移屏障的集成电路包括线，该线包括第一导电材料，该线还包括由一个或多个电迁移屏障隔开的多个线段，其中所述一个或多个电迁移屏障包括隔离的第二导电材料线路各部分的电迁移效应。

53. 发明授权

US07892968B2 Via gouging methods and related semiconductor structure 有权
标题翻译：通过沟槽方法和相关的半导体结构
公开(公告)号：US07892968B2
公开(公告)日：2011-02-22
申请号：US12017141
申请日：2008-01-21
申请人： Shyng-Tsong Chen , Steven J. Holmes , David V. Horak , Takeshi Nogami , Shom Ponoth , Chih-Chao Yang
发明人： Shyng-Tsong Chen , Steven J. Holmes , David V. Horak , Takeshi Nogami , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/32139 , H01L21/31144 , H01L21/76805 , H01L21/76814 , H01L21/76831 , H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Methods for via gouging and a related semiconductor structure are disclosed. In one embodiment, the method includes forming a via opening in a dielectric material, the via opening aligned with a conductor; forming a protective coating over the dielectric material and in the via opening; performing via gouging; and removing the protective coating over horizontal surfaces of the dielectric material. A semiconductor structure may include a via having an interface with a conductor, the interface including a three-dimensionally shaped region extending into and past a surface of the conductor, wherein an outer edge of the three-dimensionally shaped region is distanced from an outermost surface of the via.
摘要翻译：公开了通孔沟槽的方法和相关的半导体结构。在一个实施例中，该方法包括在电介质材料中形成通孔，通孔与导体对准; 在介电材料和通孔开口上形成保护涂层; 通过刨花进行; 并且在电介质材料的水平表面上去除保护涂层。半导体结构可以包括与导体具有界面的通孔，所述界面包括延伸到导体表面中并经过导体表面的三维成形区域，其中三维成形区域的外边缘与最外表面的通道。

54. 发明授权

US09620619B2 Borderless contact structure 有权
公开(公告)号：US09620619B2
公开(公告)日：2017-04-11
申请号：US13348894
申请日：2012-01-12
申请人： Veeraraghavan S. Basker , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
发明人： Veeraraghavan S. Basker , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L21/20 , H01L29/78 , H01L29/66 , H01L21/768 , H01L21/28
CPC分类号： H01L29/66545 , H01L21/76897 , H01L29/66628 , H01L29/78
摘要： A borderless contact structure or partially borderless contact structure and methods of manufacture are disclosed. The method includes forming a gate structure and a space within the gate structure, defined by spacers. The method further includes blanket depositing a sealing material in the space, over the gate structure and on a semiconductor material. The method further includes removing the sealing material from over the gate structure and on the semiconductor material, leaving the sealing material within the space. The method further includes forming an interlevel dielectric material over the gate structure. The method further includes patterning the interlevel dielectric material to form an opening exposing the semiconductor material and a portion of the gate structure. The method further includes forming a contact in the opening formed in the interlevel dielectric material.

55. 发明授权

US09059254B2 Overlay-tolerant via mask and reactive ion etch (RIE) technique 有权
标题翻译：覆盖层通过掩模和反应离子蚀刻（RIE）技术
公开(公告)号：US09059254B2
公开(公告)日：2015-06-16
申请号：US13604660
申请日：2012-09-06
申请人： Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
发明人： Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L21/44 , H01L21/768 , H01L21/311
CPC分类号： H01L23/528 , H01L21/31144 , H01L21/76807 , H01L21/76816 , H01L21/76831 , H01L23/5226 , H01L2924/0002 , H01L2924/0001 , H01L2924/00
摘要： A method is provided that includes first etching a substrate according to a first mask. The first etching forms a first etch feature in the substrate to a first depth. The first etching also forms a sliver opening in the substrate. The sliver opening may then be filled with a fill material. A second mask may be formed by removing a portion of the first mask. The substrate exposed by the second mask may be etched with a second etch, in which the second etching is selective to the fill material. The second etching extends the first etch feature to a second depth that is greater than the first depth, and the second etch forms a second etch feature. The first etch feature and the second etch feature may then be filled with a conductive metal.
摘要翻译：提供了一种方法，其包括首先根据第一掩模蚀刻衬底。第一蚀刻在衬底中形成第一深度的第一蚀刻特征。第一蚀刻还在衬底中形成条条开口。然后可以用填充材料填充条子开口。可以通过去除第一掩模的一部分来形成第二掩模。可以用第二蚀刻蚀刻由第二掩模曝光的衬底，其中第二蚀刻对填充材料是选择性的。第二蚀刻将第一蚀刻特征扩展到大于第一深度的第二深度，并且第二蚀刻形成第二蚀刻特征。然后可以用导电金属填充第一蚀刻特征和第二蚀刻特征。

56. 发明授权

US08704343B2 Borderless interconnect line structure self-aligned to upper and lower level contact vias 有权
标题翻译：无边界互连线结构自对准到上层和下层接触孔
公开(公告)号：US08704343B2
公开(公告)日：2014-04-22
申请号：US13607677
申请日：2012-09-08
申请人： Shom Ponoth , David V. Horak , Charles W. Koburger, III , Chih-Chao Yang
发明人： Shom Ponoth , David V. Horak , Charles W. Koburger, III , Chih-Chao Yang
IPC分类号： H01L21/44
CPC分类号： H01L23/528 , H01L21/76885 , H01L21/76897 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A metal layer is deposited on a planar surface on which top surfaces of underlying metal vias are exposed. The metal layer is patterned to form at least one metal block, which has a horizontal cross-sectional area of a metal line to be formed and at least one overlying metal via to be formed. Each upper portion of underlying metal vias is recessed outside of the area of a metal block located directly above. The upper portion of the at least one metal block is lithographically patterned to form an integrated line and via structure including a metal line having a substantially constant width and at least one overlying metal via having the same substantially constant width and borderlessly aligned to the metal line. An overlying-level dielectric material layer is deposited and planarized so that top surface(s) of the at least one overlying metal via is/are exposed.
摘要翻译：金属层沉积在其上暴露下面的金属通孔的顶表面的平坦表面上。图案化金属层以形成至少一个金属块，其具有要形成的金属线的水平横截面积和要形成的至少一个上覆的金属通孔。下面的金属通孔的每个上部凹陷在位于正上方的金属块的区域的外部。至少一个金属块的上部被光刻地图案化以形成集成线和通孔结构，其包括具有基本上恒定的宽度的金属线和至少一个覆盖的金属通孔，其具有相同的基本上恒定的宽度并且与金属线无边界地对准。沉积和平坦化上层电介质材料层，使得至少一个上覆金属通孔的顶表面被暴露。

57. 发明授权

US08703604B2 Creation of vias and trenches with different depths 有权
标题翻译：创造不同深度的通道和沟渠
公开(公告)号：US08703604B2
公开(公告)日：2014-04-22
申请号：US13415164
申请日：2012-03-08
申请人： Shom Ponoth , David V. Horak , Takeshi Nogami , Chih-Chao Yang
发明人： Shom Ponoth , David V. Horak , Takeshi Nogami , Chih-Chao Yang
IPC分类号： H01L21/311 , H01L21/3065
CPC分类号： H01L23/5226 , H01L21/31116 , H01L21/768 , H01L21/76816 , H01L21/76829 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the invention provide a method of creating vias and trenches with different length. The method includes depositing a plurality of dielectric layers on top of a semiconductor structure with the plurality of dielectric layers being separated by at least one etch-stop layer; creating multiple openings from a top surface of the plurality of dielectric layers down into the plurality of dielectric layers by a non-selective etching process, wherein at least one of the multiple openings has a depth below the etch-step layer; and continuing etching the multiple openings by a selective etching process until one or more openings of the multiple openings that are above the etch-stop layer reach and expose the etch-stop layer. Semiconductor structures made thereby are also provided.
摘要翻译：本发明的实施例提供了一种创建具有不同长度的通孔和沟槽的方法。该方法包括在半导体结构的顶部上沉积多个电介质层，多个电介质层被至少一个蚀刻停止层隔开; 通过非选择性蚀刻工艺从所述多个电介质层的顶表面形成多个开口到多个介电层中，其中所述多个开口中的至少一个具有在所述蚀刻步骤层下方的深度; 以及通过选择性蚀刻工艺继续蚀刻多个开口，直到位于蚀刻停止层上方的多个开口的一个或多个开口到达和暴露蚀刻停止层。也提供了由此制成的半导体结构。

58. 发明申请

US20140035142A1 PROFILE CONTROL IN INTERCONNECT STRUCTURES 有权
标题翻译：互连结构中的配置控制
公开(公告)号：US20140035142A1
公开(公告)日：2014-02-06
申请号：US13562953
申请日：2012-07-31
申请人： Chih-Chao Yang , Shyng-Tsong Chen , Samuel S. Choi , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Wai-Kin Li , Christopher J. Penny , Shom Ponoth , Yunpeng Yin
发明人： Chih-Chao Yang , Shyng-Tsong Chen , Samuel S. Choi , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Wai-Kin Li , Christopher J. Penny , Shom Ponoth , Yunpeng Yin
IPC分类号： H01L23/48 , H01L21/28
CPC分类号： H01L23/53295 , H01L21/76807 , H01L21/76813 , H01L21/76831 , H01L21/76844 , H01L23/481 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： The profile of a via can be controlled by forming a profile control liner within each via opening that is formed into a dielectric material prior to forming a line opening within the dielectric material. The presence of the profile control liner within each via opening during the formation of the line opening prevents rounding of the corners of a dielectric material portion that is present beneath the line opening and adjacent the via opening.
摘要翻译：可以通过在形成介电材料之前形成电介质材料的每个通孔开口内形成轮廓控制衬垫来控制通孔的轮廓，然后在电介质材料内形成线路开口。在形成线路开口期间在每个通孔开口内存在轮廓控制衬垫防止存在于线路开口下方并且邻近通孔开口的电介质材料部分的拐角的四舍五入。

59. 发明申请

US20130313717A1 SPACER FOR ENHANCING VIA PATTERN OVERLAY TOLERENCE 审中-公开
标题翻译：通过模式叠加来增强间隔
公开(公告)号：US20130313717A1
公开(公告)日：2013-11-28
申请号：US13479893
申请日：2012-05-24
申请人： Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
发明人： Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/528 , H01L21/0337 , H01L21/31144 , H01L21/76811 , H01L21/76816 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： After formation of line openings in a hard mask layer, hard mask level spacers are formed on sidewalls of the hard mask layer. A photoresist is applied and patterned to form a via pattern including a via opening. The overlay tolerance for printing the via pattern is increased by the lateral thickness of the hard mask level spacers. A portion of a dielectric material layer is patterned to form a via cavity pattern by an etch that employs the hard mask layer and the hard mask level spacers as etch masks. The hard mask level spacers are subsequently removed, and the pattern of the line is subsequently transferred into an upper portion of the dielectric material layer, while the via cavity pattern is transferred to a lower portion of the dielectric material layer.
摘要翻译：在硬掩模层中形成线开口之后，在硬掩模层的侧壁上形成硬掩模级间隔物。施加光刻胶并图案化以形成包括通孔开口的通孔图案。用于印刷通孔图案的覆盖公差通过硬掩模级间隔物的横向厚度增加。电介质材料层的一部分被图案化以通过使用硬掩模层和硬掩模级间隔件作为蚀刻掩模的蚀刻形成通孔腔图案。随后去除硬掩模级间隔物，并且随后将该线的图案转移到电介质材料层的上部，同时通孔腔图案被转移到电介质材料层的下部。

60. 发明授权

US08569168B2 Dual-metal self-aligned wires and vias 有权
标题翻译：双金属自对准导线和通孔
公开(公告)号：US08569168B2
公开(公告)日：2013-10-29
申请号：US13371493
申请日：2012-02-13
申请人： Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
发明人： Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L21/44
CPC分类号： H01L23/485 , H01L21/76885 , H01L21/76897 , H01L23/5283 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： Method of forming a semiconductor structure which includes forming first conductive spacers on a semiconductor substrate; forming second conductive spacers with respect to the first conductive spacers, at least one of the second conductive spacers adjacent to and in contact with each of the first conductive spacers to form combined conductive spacers; recessing the second conductive spacers with respect to the first conductive spacers so that the first conductive spacers extend beyond the second conductive spacers; depositing an ILD to cover the first and second spacers except for an exposed edge of the first conductive spacers; patterning the exposed edges of the first conductive spacers to recess the edges of the first conductive spacers in predetermined locations to form recesses with respect to the ILD; and filling the recesses with an insulating material to leave unrecessed edges of the first conductive spacers as vias to subsequent wiring features.
摘要翻译：形成半导体结构的方法，包括在半导体衬底上形成第一导电间隔物; 相对于所述第一导电间隔物形成第二导电间隔物，所述第二导电间隔物中的至少一个与所述第一导电间隔物中的每一个相邻并与之接触以形成组合的导电间隔物; 相对于第一导电间隔物使第二导电间隔物凹陷，使得第一导电间隔物延伸超过第二导电间隔物; 沉积ILD以覆盖除了第一导电间隔物的暴露边缘之外的第一和第二间隔物; 图案化第一导电间隔物的暴露边缘以将预定位置中的第一导电间隔物的边缘凹入以形成相对于ILD的凹部; 并用绝缘材料填充凹槽，以将第一导电间隔物的未加工的边缘作为过孔留下以后的布线特征。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式