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1. 发明申请

US20090184400A1 VIA GOUGING METHODS AND RELATED SEMICONDUCTOR STRUCTURE 有权
标题翻译：通过采用方法和相关半导体结构
公开(公告)号：US20090184400A1
公开(公告)日：2009-07-23
申请号：US12017141
申请日：2008-01-21
申请人： Shyng-Tsong Chen , Steven J. Holmes , David V. Horak , Takeshi Nogami , Shom Ponoth , Chih-Chao Yang
发明人： Shyng-Tsong Chen , Steven J. Holmes , David V. Horak , Takeshi Nogami , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L21/311 , H01L23/538
CPC分类号： H01L21/32139 , H01L21/31144 , H01L21/76805 , H01L21/76814 , H01L21/76831 , H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Methods for via gouging and a related semiconductor structure are disclosed. In one embodiment, the method includes forming a via opening in a dielectric material, the via opening aligned with a conductor; forming a protective coating over the dielectric material and in the via opening; performing via gouging; and removing the protective coating over horizontal surfaces of the dielectric material. A semiconductor structure may include a via having an interface with a conductor, the interface including a three-dimensionally shaped region extending into and past a surface of the conductor, wherein an outer edge of the three-dimensionally shaped region is distanced from an outermost surface of the via.
摘要翻译：公开了通孔沟槽的方法和相关的半导体结构。在一个实施例中，该方法包括在电介质材料中形成通孔，通孔与导体对准; 在介电材料和通孔开口上形成保护涂层; 通过刨花进行; 并且在电介质材料的水平表面上去除保护涂层。半导体结构可以包括与导体具有界面的通孔，所述界面包括延伸到导体表面中并经过导体表面的三维成形区域，其中三维成形区域的外边缘与最外表面的通道。

2. 发明授权

US07892968B2 Via gouging methods and related semiconductor structure 有权
标题翻译：通过沟槽方法和相关的半导体结构
公开(公告)号：US07892968B2
公开(公告)日：2011-02-22
申请号：US12017141
申请日：2008-01-21
申请人： Shyng-Tsong Chen , Steven J. Holmes , David V. Horak , Takeshi Nogami , Shom Ponoth , Chih-Chao Yang
发明人： Shyng-Tsong Chen , Steven J. Holmes , David V. Horak , Takeshi Nogami , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/32139 , H01L21/31144 , H01L21/76805 , H01L21/76814 , H01L21/76831 , H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Methods for via gouging and a related semiconductor structure are disclosed. In one embodiment, the method includes forming a via opening in a dielectric material, the via opening aligned with a conductor; forming a protective coating over the dielectric material and in the via opening; performing via gouging; and removing the protective coating over horizontal surfaces of the dielectric material. A semiconductor structure may include a via having an interface with a conductor, the interface including a three-dimensionally shaped region extending into and past a surface of the conductor, wherein an outer edge of the three-dimensionally shaped region is distanced from an outermost surface of the via.
摘要翻译：公开了通孔沟槽的方法和相关的半导体结构。在一个实施例中，该方法包括在电介质材料中形成通孔，通孔与导体对准; 在介电材料和通孔开口上形成保护涂层; 通过刨花进行; 并且在电介质材料的水平表面上去除保护涂层。半导体结构可以包括与导体具有界面的通孔，所述界面包括延伸到导体表面中并经过导体表面的三维成形区域，其中三维成形区域的外边缘与最外表面的通道。

3. 发明申请

US20110193230A1 FORMATION OF AIR GAP WITH PROTECTION OF METAL LINES 失效
标题翻译：形成有保护金属线的空气隙
公开(公告)号：US20110193230A1
公开(公告)日：2011-08-11
申请号：US12700792
申请日：2010-02-05
申请人： Takeshi Nogami , Shyng-Tsong Chen , David V. Horak , Son V. Nguyen , Shom Ponoth , Chih-Chao Yang
发明人： Takeshi Nogami , Shyng-Tsong Chen , David V. Horak , Son V. Nguyen , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L24/80 , H01L21/0337 , H01L21/31144 , H01L21/7682 , H01L23/5222 , H01L23/5329 , H01L23/53295
摘要： A method is provided for fabricating a microelectronic element having an air gap in a dielectric layer thereof. A dielectric cap layer can be formed which has a first portion overlying surfaces of metal lines, the first portion extending a first height above a height of a surface of the dielectric layer and a second portion overlying the dielectric layer surface and extending a second height above the height of the surface of the dielectric layer, the second height being greater than the first height. After forming the cap layer, a mask can be formed over the cap layer. The mask can have a multiplicity of randomly disposed holes. Each hole may expose a surface of only the second portion of the cap layer which has the greater height. The mask may fully cover a surface of the first portion of the cap layer having the lower height. Subsequently, an etchant can be directed towards the first and second portions of the cap layer to form holes in the cap layer aligned with the holes in the mask. Material can be removed from the dielectric layer where exposed to the etchant by the holes in the cap layer. At such time, the mask can protect the first portion of the cap layer and the metal lines from being attacked by the etchant.
摘要翻译：提供了一种用于制造其电介质层中具有气隙的微电子元件的方法。可以形成介电盖层，其具有覆盖金属线表面的第一部分，第一部分在电介质层的表面的高度之上延伸第一高度，以及覆盖介电层表面的第二部分，并且延伸第二高度电介质层的表面的高度，第二高度大于第一高度。在形成盖层之后，可以在盖层之上形成掩模。掩模可以具有多个随机布置的孔。每个孔可以暴露仅具有较大高度的盖层的第二部分的表面。掩模可以完全覆盖具有较低高度的盖层的第一部分的表面。随后，可以将蚀刻剂引导到盖层的第一和第二部分，以在盖层中形成与掩模中的孔对准的孔。可以通过盖层中的孔从暴露于蚀刻剂的介电层去除材料。此时，掩模可以保护盖层的第一部分和金属线不被蚀刻剂侵蚀。

4. 发明授权

US08399350B2 Formation of air gap with protection of metal lines 失效
标题翻译：形成气隙，保护金属线
公开(公告)号：US08399350B2
公开(公告)日：2013-03-19
申请号：US12700792
申请日：2010-02-05
申请人： Takeshi Nogami , Shyng-Tsong Chen , David V. Horak , Son V. Nguyen , Shom Ponoth , Chih-Chao Yang
发明人： Takeshi Nogami , Shyng-Tsong Chen , David V. Horak , Son V. Nguyen , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L24/80 , H01L21/0337 , H01L21/31144 , H01L21/7682 , H01L23/5222 , H01L23/5329 , H01L23/53295
摘要： Method for fabricating a microelectronic element having an air gap in a dielectric layer thereof. A dielectric cap layer can be formed which has a first portion overlying surfaces of metal lines, the first portion extending a first height above a height of a surface of the dielectric layer, and a second portion overlying the dielectric layer surface and extending a second height above the height of the surface of the dielectric layer, the second height being greater than the first height. After forming the cap layer, a mask can be formed over the cap layer. The mask exposes a surface of only the second portion of the cap layer which has the greater height. Subsequently, an etchant can be directed towards the first and second portions of the cap layer. Material can be removed from the dielectric layer where exposed to the etchant.
摘要翻译：一种在其电介质层中具有气隙的微电子元件的制造方法。可以形成介电盖层，其具有覆盖金属线表面的第一部分，第一部分在电介质层表面的高度之上延伸第一高度，以及覆盖介电层表面的第二部分，并延伸第二高度高于介电层表面的高度，第二高度大于第一高度。在形成盖层之后，可以在盖层之上形成掩模。掩模仅暴露具有较大高度的盖层的第二部分的表面。随后，蚀刻剂可以被引导到盖层的第一和第二部分。材料可以从暴露于蚀刻剂的介电层去除。

5. 发明授权

US08404582B2 Structure and method for manufacturing interconnect structures having self-aligned dielectric caps 有权
标题翻译：用于制造具有自对准电介质盖的互连结构的结构和方法
公开(公告)号：US08404582B2
公开(公告)日：2013-03-26
申请号：US12773306
申请日：2010-05-04
申请人： David V Horak , Takeshi Nogami , Shom Ponoth , Chih-Chao Yang
发明人： David V Horak , Takeshi Nogami , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L21/4763 , H01L23/48
CPC分类号： H01L23/53238 , H01L21/76805 , H01L21/7682 , H01L21/76832 , H01L21/76834 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Interconnect structures having self-aligned dielectric caps are provided. At least one metallization level is formed on a substrate. A dielectric cap is selectively deposited on the metallization level.
摘要翻译：提供具有自对准电介质盖的互连结构。在基板上形成至少一个金属化层。电介质盖被选择性地沉积在金属化层上。

6. 发明申请

US20120153503A1 CREATION OF VIAS AND TRENCHES WITH DIFFERENT DEPTHS 有权
公开(公告)号：US20120153503A1
公开(公告)日：2012-06-21
申请号：US13407933
申请日：2012-02-29
申请人： Shom Ponoth , David V. Horak , Takeshi Nogami , Chih-Chao Yang
发明人： Shom Ponoth , David V. Horak , Takeshi Nogami , Chih-Chao Yang
IPC分类号： H01L23/522
CPC分类号： H01L23/5226 , H01L21/31116 , H01L21/768 , H01L21/76816 , H01L21/76829 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the invention provide a method of creating vias and trenches with different length. The method includes depositing a plurality of dielectric layers on top of a semiconductor structure with the plurality of dielectric layers being separated by at least one etch-stop layer; creating multiple openings from a top surface of the plurality of dielectric layers down into the plurality of dielectric layers by a non-selective etching process, wherein at least one of the multiple openings has a depth below the etch-step layer; and continuing etching the multiple openings by a selective etching process until one or more openings of the multiple openings that are above the etch-stop layer reach and expose the etch-stop layer. Semiconductor structures made thereby are also provided.

7. 发明申请

US20110101538A1 CREATION OF VIAS AND TRENCHES WITH DIFFERENT DEPTHS 失效
标题翻译：创造不同深度的VIAS和TRENCHES
公开(公告)号：US20110101538A1
公开(公告)日：2011-05-05
申请号：US12610624
申请日：2009-11-02
申请人： Shom Ponoth , David V. Horak , Takeshi Nogami , Chih-Chao Yang
发明人： Shom Ponoth , David V. Horak , Takeshi Nogami , Chih-Chao Yang
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/5226 , H01L21/31116 , H01L21/768 , H01L21/76816 , H01L21/76829 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the invention provide a method of creating vias and trenches with different length. The method includes depositing a plurality of dielectric layers on top of a semiconductor structure with the plurality of dielectric layers being separated by at least one etch-stop layer; creating multiple openings from a top surface of the plurality of dielectric layers down into the plurality of dielectric layers by a non-selective etching process, wherein at least one of the multiple openings has a depth below the etch-step layer; and continuing etching the multiple openings by a selective etching process until one or more openings of the multiple openings that are above the etch-stop layer reach and expose the etch-stop layer. Semiconductor structures made thereby are also provided.
摘要翻译：本发明的实施例提供了一种创建具有不同长度的通孔和沟槽的方法。该方法包括在半导体结构的顶部上沉积多个电介质层，多个电介质层被至少一个蚀刻停止层隔开; 通过非选择性蚀刻工艺从所述多个电介质层的顶表面形成多个开口到多个介电层中，其中所述多个开口中的至少一个具有在所述蚀刻步骤层下方的深度; 以及通过选择性蚀刻工艺继续蚀刻多个开口，直到位于蚀刻停止层上方的多个开口的一个或多个开口到达和暴露蚀刻停止层。还提供了由此制成的半导体结构。

8. 发明申请

US20110084403A1 PAD BONDING EMPLOYING A SELF-ALIGNED PLATED LINER FOR ADHESION ENHANCEMENT 有权
标题翻译：使用自对准的衬垫进行粘合增强的PAD结合
公开(公告)号：US20110084403A1
公开(公告)日：2011-04-14
申请号：US12575980
申请日：2009-10-08
申请人： Chih-Chao Yang , David V. Horak , Takeshi Nogami , Shom Ponoth
发明人： Chih-Chao Yang , David V. Horak , Takeshi Nogami , Shom Ponoth
IPC分类号： H01L23/488 , H01L21/50
CPC分类号： H01L24/80 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/82 , H01L24/92 , H01L25/50 , H01L2224/05007 , H01L2224/05014 , H01L2224/0502 , H01L2224/05099 , H01L2224/05547 , H01L2224/05554 , H01L2224/0556 , H01L2224/05599 , H01L2224/08121 , H01L2224/80001 , H01L2224/80345 , H01L2224/80357 , H01L2224/80359 , H01L2224/80895 , H01L2224/80896 , H01L2224/821 , H01L2224/9212 , H01L2225/06513 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01044 , H01L2924/01045 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01077 , H01L2924/01079 , H01L2924/1305 , H01L2924/1306 , H01L2924/00 , H01L2224/80 , H01L2224/82
摘要： Two substrates are brought together and placed in a plating bath. In one embodiment, a conductive material is plated in microscopic cavities present at the interface between a first metal pad and a second metal pad to form at least one interfacial plated metal liner portion that adheres to a surface of the first metal pad and a surface of the second metal pad. In another embodiment, at least one metal pad is recessed relative to a dielectric surface before being brought together. The two substrates are placed in a plating bath and a conductive material is plated in the cavity between the first metal pad and the second metal pad to form a contiguous plated metal liner layer that adheres to a surface of the first metal pad and a surface of the second metal pad.
摘要翻译：将两个基材放在一起并放置在电镀浴中。在一个实施例中，将导电材料电镀在存在于第一金属焊盘和第二金属焊盘之间的界面处的微观空腔中，以形成粘附到第一金属焊盘的表面的至少一个界面电镀金属衬垫部分，第二个金属垫。在另一个实施例中，至少一个金属焊盘相对于电介质表面在被聚集之前是凹进的。将两个基板放置在电镀槽中，并且将导电材料镀在第一金属焊盘和第二金属焊盘之间的空腔中，以形成附着在第一金属焊盘的表面上的连续的电镀金属衬垫层，第二个金属垫。

9. 发明申请

US20090278258A1 INTERCONNECT STRUCTURE WITH A MUSHROOM-SHAPED OXIDE CAPPING LAYER AND METHOD FOR FABRICATING SAME 有权
标题翻译：带有MUSHROOM型氧化物覆盖层的互连结构及其制造方法
公开(公告)号：US20090278258A1
公开(公告)日：2009-11-12
申请号：US12115944
申请日：2008-05-06
申请人： Chih-Chao Yang , David V. Horak , Takeshi Nogami , Shom Ponoth
发明人： Chih-Chao Yang , David V. Horak , Takeshi Nogami , Shom Ponoth
IPC分类号： H01L21/768 , H01L23/532
CPC分类号： H01L23/53295 , H01L21/76826 , H01L21/76832 , H01L21/76834 , H01L21/76885 , H01L23/53223 , H01L23/53238 , H01L23/53271 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure is provided that includes a dielectric material 52′ having a dielectric constant of 4.0 or less and including a plurality of conductive features 56 embedded therein. The dielectric material 52′ has an upper surface 52r that is located beneath an upper surface of each of the plurality of conductive features 56. A first dielectric cap 58 is located on the upper surface of the dielectric material 52′ and extends onto at least a portion of the upper surface of each of the plurality of conductive features 56. As shown, the first dielectric cap 58 forms an interface 59 with each of the plurality of conductive features 56 that is opposite to an electrical field that is generated by neighboring conductive features. The inventive structure also includes a second dielectric cap 60 located on an exposed portion of the upper surface of each of the plurality of conductive features 56 not covered with the first dielectric cap 58. The second dielectric cap 60 further covers on an exposed surface of the first dielectric cap 58.
摘要翻译：提供一种互连结构，其包括介电常数为4.0或更小的介电材料52'，并且包括嵌入其中的多个导电特征56。电介质材料52'具有位于多个导电特征56中的每一个的上表面下方的上表面52r。第一电介质盖58位于电介质材料52'的上表面上并延伸至至少一个多个导电特征56中的每一个的上表面的一部分。如图所示，第一电介质盖58形成接口59，多个导电特征56中的每一个与由相邻导电特征。本发明的结构还包括位于多个导电特征56的每一个的上表面的未被第一电介质盖58覆盖的暴露部分上的第二电介质帽60.第二电介质帽60还覆盖在第一电介质盖58。

10. 发明授权

US08482132B2 Pad bonding employing a self-aligned plated liner for adhesion enhancement 有权
公开(公告)号：US08482132B2
公开(公告)日：2013-07-09
申请号：US12575980
申请日：2009-10-08
申请人： Chih-Chao Yang , David V. Horak , Takeshi Nogami , Shom Ponoth
发明人： Chih-Chao Yang , David V. Horak , Takeshi Nogami , Shom Ponoth
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/80 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/82 , H01L24/92 , H01L25/50 , H01L2224/05007 , H01L2224/05014 , H01L2224/0502 , H01L2224/05099 , H01L2224/05547 , H01L2224/05554 , H01L2224/0556 , H01L2224/05599 , H01L2224/08121 , H01L2224/80001 , H01L2224/80345 , H01L2224/80357 , H01L2224/80359 , H01L2224/80895 , H01L2224/80896 , H01L2224/821 , H01L2224/9212 , H01L2225/06513 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01044 , H01L2924/01045 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01077 , H01L2924/01079 , H01L2924/1305 , H01L2924/1306 , H01L2924/00 , H01L2224/80 , H01L2224/82
摘要： Two substrates are brought together and placed in a plating bath. In one embodiment, a conductive material is plated in microscopic cavities present at the interface between a first metal pad and a second metal pad to form at least one interfacial plated metal liner portion that adheres to a surface of the first metal pad and a surface of the second metal pad. In another embodiment, at least one metal pad is recessed relative to a dielectric surface before being brought together. The two substrates are placed in a plating bath and a conductive material is plated in the cavity between the first metal pad and the second metal pad to form a contiguous plated metal liner layer that adheres to a surface of the first metal pad and a surface of the second metal pad.

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