专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 外观设计

USD402638S Temporary package for semiconductor dice 失效
公开(公告)号：USD402638S
公开(公告)日：1998-12-15
申请号：US70029
申请日：1997-04-25
申请人： Warren M. Farnworth , Alan G. Wood , David R. Hembree , Salman Akram
设计人： Warren M. Farnworth , Alan G. Wood , David R. Hembree , Salman Akram

52. 外观设计

USD401567S Temporary package for semiconductor dice 失效
公开(公告)号：USD401567S
公开(公告)日：1998-11-24
申请号：US70005
申请日：1997-04-25
申请人： Warren M. Farnworth , Alan G. Wood , David R. Hembree , Salman Akram
设计人： Warren M. Farnworth , Alan G. Wood , David R. Hembree , Salman Akram

53. 发明授权

US5815000A Method for testing semiconductor dice with conventionally sized temporary packages 失效
标题翻译：用常规尺寸的临时封装测试半导体裸片的方法
公开(公告)号：US5815000A
公开(公告)日：1998-09-29
申请号：US580687
申请日：1995-12-29
申请人： Warren M. Farnworth , Alan G. Wood , David R. Hembree , Salman Akram
发明人： Warren M. Farnworth , Alan G. Wood , David R. Hembree , Salman Akram
IPC分类号： G01R1/04 , G01R1/067 , G01R1/073 , G01R3/00 , G01R31/28 , H01L21/60 , H01L21/66 , H01L21/68 , H01L23/13 , H01L23/498 , H05K3/00 , H05K3/42 , G01R31/02
CPC分类号： G01R1/0466 , G01R1/0483 , G01R31/2893 , H01L21/6835 , H01L22/20 , H01L23/13 , H01L23/49816 , H01L23/49838 , H01L24/80 , H01L24/85 , H05K3/4007 , G01R3/00 , G01R31/2863 , H01L2224/16145 , H01L2224/48 , H01L2224/85001 , H01L2225/06562 , H01L24/48 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/0105 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15151 , H01L2924/15174 , H01L2924/19041 , H01L2924/30105 , H05K2201/0133 , H05K2201/0347 , H05K2201/0367 , H05K2201/0394 , H05K2201/09481 , H05K2201/09563 , H05K2203/0307 , H05K2203/0723 , H05K3/0058 , H05K3/0067 , H05K3/423
摘要： A method for packaging and testing a semiconductor die is provided. The method includes forming a temporary package for the die that has a size, shape and lead configuration that is the same as a conventional plastic or ceramic semiconductor package. The temporary package can be used for burn-in testing of the die using standard equipment. The die can then be removed from the package and certified as a known good die. In an illustrative embodiment the package is formed in a SOJ configuration. The package includes a base, an interconnect and a force applying mechanism. The package base can be formed of ceramic or plastic using a ceramic lamination process or a Cerdip formation process.
摘要翻译：提供了一种用于封装和测试半导体管芯的方法。该方法包括形成具有与常规塑料或陶瓷半导体封装相同的尺寸，形状和引线配置的裸片的临时封装。临时包装可用于使用标准设备对模具进行老化测试。然后可以将模具从包装中取出并被认证为已知的好的模具。在说明性实施例中，封装形成为SOJ构造。该包装包括底座，互连和力施加机构。封装基底可以使用陶瓷层压工艺或Cerdip形成工艺由陶瓷或塑料制成。

54. 外观设计

USD394844S Temporary package for semiconductor dice 失效
公开(公告)号：USD394844S
公开(公告)日：1998-06-02
申请号：US70050
申请日：1997-04-25
申请人： Warren M. Farnworth , Alan G. Wood , David R. Hembree , Salman Akram
设计人： Warren M. Farnworth , Alan G. Wood , David R. Hembree , Salman Akram

55. 发明授权

US07459393B2 Method for fabricating semiconductor components with thinned substrate, circuit side contacts, conductive vias and backside contacts 有权
标题翻译：用薄化衬底制造半导体元件的方法，电路侧触点，导电通孔和背面触点
公开(公告)号：US07459393B2
公开(公告)日：2008-12-02
申请号：US11497699
申请日：2006-08-02
申请人： Warren M. Farnworth , Alan G. Wood , William M. Hiatt , James M. Wark , David R. Hembree , Kyle K. Kirby , Pete A. Benson
发明人： Warren M. Farnworth , Alan G. Wood , William M. Hiatt , James M. Wark , David R. Hembree , Kyle K. Kirby , Pete A. Benson
IPC分类号： H01L21/44
CPC分类号： H01L21/561 , B33Y70/00 , B33Y80/00 , H01L21/563 , H01L21/76898 , H01L23/3114 , H01L23/481 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/97 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L2221/68331 , H01L2224/02372 , H01L2224/0401 , H01L2224/05111 , H01L2224/05118 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05169 , H01L2224/05171 , H01L2224/05178 , H01L2224/0518 , H01L2224/05181 , H01L2224/05184 , H01L2224/05559 , H01L2224/05569 , H01L2224/05572 , H01L2224/05624 , H01L2224/05644 , H01L2224/05664 , H01L2224/05666 , H01L2224/13005 , H01L2224/13006 , H01L2224/13009 , H01L2224/13024 , H01L2224/13099 , H01L2224/16145 , H01L2224/73204 , H01L2224/97 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2225/06582 , H01L2225/06596 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/15312 , H01L2924/18161 , H01L2924/19015 , H01L2924/19041 , H01L2924/351 , H01L2924/207 , H01L2224/05552 , H01L2924/00 , H01L2924/00014 , H01L2924/013
摘要： A method for fabricating a semiconductor component includes the steps of providing a substrate having a contact on a circuit side thereof, forming an opening from a backside of the substrate to the contact, forming a conductive via in the opening in electrical contact with a surface of the contact, and forming a second contact on the back side in electrical communication with the conductive via. The method can also include the steps of thinning the substrate from the backside, forming insulating layers on the circuit side and the backside, and forming a conductor and terminal contact on the circuit side in electrical communication with the conductive via. A semiconductor component includes the contact on the circuit side, the conductive via in electrical contact with the contact, and the second contact on the backside in electrical communication with the conductive via. The semiconductor component can also include the insulating layers, the conductor and the terminal contact.
摘要翻译：一种制造半导体部件的方法包括以下步骤：提供在其电路侧具有接触的基板，从基板的背面形成开口到触点，在开口中形成导电通孔，该导电通孔与接触，并且在背面形成与导电通孔电连通的第二接触。该方法还可以包括从背面减薄衬底的步骤，在电路侧和背面形成绝缘层，以及在电路侧形成与导电通孔电连通的导体和端子触点。半导体部件包括电路侧的触点，与触点电接触的导电通孔以及与导电通路电气连通的背侧的第二触点。半导体部件还可以包括绝缘层，导体和端子触头。

56. 发明授权

US07358751B2 Contact pin assembly and contactor card 有权
标题翻译：接触销总成和接触器卡
公开(公告)号：US07358751B2
公开(公告)日：2008-04-15
申请号：US11152513
申请日：2005-06-14
申请人： Kyle K. Kirby , Warren M. Farnworth , James M. Wark , William M. Hiatt , David R. Hembree , Alan G. Wood
发明人： Kyle K. Kirby , Warren M. Farnworth , James M. Wark , William M. Hiatt , David R. Hembree , Alan G. Wood
IPC分类号： G01R31/02
CPC分类号： G01R1/0735 , G01R1/07314 , H01L23/13 , H01L23/481 , H01L23/49811 , H01L23/49827 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/16235 , H01L2924/00014 , H01L2924/09701 , H01L2924/15311 , H01L2924/3511 , H01R12/714 , H01R13/24 , H01R2201/20 , H05K3/326 , H05K7/1069 , H05K2201/0314 , H05K2201/09036 , H05K2201/10378 , Y10T29/49165 , Y10T29/49174 , Y10T29/49204 , Y10T29/49222 , H01L2224/05599
摘要： A compliant contact pin assembly and a contactor card system are provided. The compliant contact pin assembly includes a contact pin formed from a portion of a substrate with the contact pin compliantly held suspended within the substrate by a compliant coupling structure. The suspension within the substrate results in a compliant deflection orthogonal to the plane of the substrate. The contact pin assembly is formed by generally thinning the substrate around the contact pin location and then specifically thinning the substrate immediately around the contact pin location for forming a void. The contact pin is compliantly coupled, in one embodiment by compliant coupling material, and in another embodiment by compliantly flexible portions of the substrate.
摘要翻译：提供了柔性接触销组件和接触器卡系统。柔性接触销组件包括由基板的一部分形成的接触销，其中触头销顺从地保持通过柔性联接结构悬挂在基板内。衬底内的悬浮液导致与衬底的平面垂直的柔顺偏转。接触销组件通过使基板围绕接触销位置大体变薄而形成，然后特别地使基板在接触销位置周围特别地变薄以形成空隙。在一个实施例中，接触销被顺从地联接，在一个实施例中通过柔性耦合材料，并且在另一个实施例中，通过柔性柔性部分的衬底。

57. 发明授权

US07297563B2 Method of making contact pin card system 失效
标题翻译：制造接触针卡系统的方法
公开(公告)号：US07297563B2
公开(公告)日：2007-11-20
申请号：US11152433
申请日：2005-06-14
申请人： Kyle K. Kirby , Warren M. Farnworth , James M. Wark , William M. Hiatt , David R. Hembree , Alan G. Wood
发明人： Kyle K. Kirby , Warren M. Farnworth , James M. Wark , William M. Hiatt , David R. Hembree , Alan G. Wood
IPC分类号： H01L21/66 , H01L23/48 , H01K3/10 , H05K1/11
CPC分类号： G01R1/0735 , G01R1/07314 , H01L23/13 , H01L23/481 , H01L23/49811 , H01L23/49827 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/16235 , H01L2924/00014 , H01L2924/09701 , H01L2924/15311 , H01L2924/3511 , H01R12/714 , H01R13/24 , H01R2201/20 , H05K3/326 , H05K7/1069 , H05K2201/0314 , H05K2201/09036 , H05K2201/10378 , Y10T29/49165 , Y10T29/49174 , Y10T29/49204 , Y10T29/49222 , H01L2224/05599
摘要： A compliant contact pin contactor card method for making is provided. The compliant contact pin assembly includes a contact pin formed from a portion of a substrate with the contact pin compliantly held suspended within the substrate by a compliant coupling structure. The suspension within the substrate results in a compliant deflection orthogonal to the plane of the substrate. The contact pin assembly is formed by generally thinning the substrate around the contact pin location and then specifically thinning the substrate immediately around the contact pin location for forming a void. The contact pin is compliantly coupled, in one embodiment by compliant coupling material, and in another embodiment by compliantly flexible portions of the substrate.
摘要翻译：提供一种兼容的接触针接触器卡制造方法。柔性接触销组件包括由基板的一部分形成的接触销，其中触头销顺从地保持通过柔性联接结构悬挂在基板内。衬底内的悬浮液导致与衬底的平面垂直的柔顺偏转。接触销组件通过使基板围绕接触销位置大体变薄而形成，然后特别地使基板在接触销位置周围特别地变薄以形成空隙。在一个实施例中，接触销被顺从地联接，在一个实施例中通过柔性耦合材料，并且在另一个实施例中，通过柔性柔性部分的衬底。

58. 发明授权

US06275052B1 Probe card and testing method for semiconductor wafers 有权
标题翻译：半导体晶圆的探针卡和测试方法
公开(公告)号：US06275052B1
公开(公告)日：2001-08-14
申请号：US09303367
申请日：1999-04-30
申请人： David R. Hembree , Warren M. Farnworth , Salman Akram , Alan G. Wood , C. Patrick Doherty , Andrew J. Krivy
发明人： David R. Hembree , Warren M. Farnworth , Salman Akram , Alan G. Wood , C. Patrick Doherty , Andrew J. Krivy
IPC分类号： G01R1073
CPC分类号： G01R1/073 , G01R31/2886
摘要： A probe card for testing semiconductor wafers, and a method and system for testing wafers using the probe card are provided. The probe card is configured for use with a conventional testing apparatus, such as a wafer probe handler, in electrical communication with test circuitry. The probe card includes an interconnect substrate having contact members for establishing electrical communication with contact locations on the wafer. The probe card also includes a membrane for physically and electrically connecting the interconnect substrate to the testing apparatus, and a compressible member for cushioning the pressure exerted on the interconnect substrate by the testing apparatus. The interconnect substrate can be formed of silicon with raised contact members having penetrating projections. Alternately the contact members can be formed as indentations for testing bumped wafers. The membrane can be similar to multi layered TAB tape including metal foil conductors attached to a flexible, electrically-insulating, elastomeric tape. The probe card can be configured to contact all of the dice on the wafer at the same time, so that test signals can be electronically applied to selected dice as required.
摘要翻译：提供了用于测试半导体晶片的探针卡，以及使用探针卡测试晶片的方法和系统。探针卡被配置用于与测试电路电连通的常规测试装置，例如晶片探测器处理器。探针卡包括具有用于与晶片上的接触位置建立电连通的接触构件的互连基板。探针卡还包括用于将互连基板物理和电连接到测试装置的膜，以及用于缓冲由测试装置施加在互连基板上的压力的可压缩构件。互连衬底可以由具有穿透突起的凸起接触构件的硅形成。或者，接触构件可以形成为用于测试凸起的晶片的凹陷。膜可以类似于多层TAB带，其包括附接到柔性，电绝缘的弹性体带的金属箔导体。探针卡可以配置为同时接触晶片上的所有骰子，以便测试信号可以根据需要以电子方式应用于选定的骰子。

59. 发明授权

US06222379B1 Conventionally sized temporary package for testing semiconductor dice 失效
标题翻译：用于测试半导体骰子的常规尺寸的临时包装
公开(公告)号：US06222379B1
公开(公告)日：2001-04-24
申请号：US09093357
申请日：1998-06-08
申请人： Warren M. Farnworth , Alan G. Wood , David R. Hembree , Salman Akram
发明人： Warren M. Farnworth , Alan G. Wood , David R. Hembree , Salman Akram
IPC分类号： G01R3102
CPC分类号： G01R1/0466 , G01R1/0483 , G01R3/00 , G01R31/2863 , G01R31/2893 , H01L21/6835 , H01L22/20 , H01L23/13 , H01L23/49816 , H01L23/49838 , H01L24/48 , H01L24/80 , H01L24/85 , H01L2224/16145 , H01L2224/48 , H01L2224/85001 , H01L2225/06562 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/0105 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15151 , H01L2924/15174 , H01L2924/181 , H01L2924/19041 , H01L2924/30105 , H05K3/0058 , H05K3/0067 , H05K3/4007 , H05K3/423 , H05K2201/0133 , H05K2201/0347 , H05K2201/0367 , H05K2201/0394 , H05K2201/09481 , H05K2201/09563 , H05K2203/0307 , H05K2203/0723 , H01L2224/78 , H01L2224/45099 , H01L2224/05599 , H01L2924/00
摘要： A method for packaging and testing a semiconductor die is provided. The method includes forming a temporary package for the die that has a size, shape and lead configuration that is the same as a conventional plastic or ceramic semiconductor package. The temporary package can be used for burn-in testing of the die using standard equipment. The die can then be removed from the package and certified as a known good die. In an illustrative embodiment the package is formed in a SOJ configuration. The package includes a base, an interconnect and a force applying mechanism. The package base can be formed of ceramic or plastic using a ceramic lamination process or a Cerdip formation process.
摘要翻译：提供了一种用于封装和测试半导体管芯的方法。该方法包括形成具有与常规塑料或陶瓷半导体封装相同的尺寸，形状和引线配置的裸片的临时封装。临时包装可用于使用标准设备对模具进行老化测试。然后可以将模具从包装中取出并被认证为已知的好的模具。在说明性实施例中，封装形成为SOJ构造。该包装包括底座，互连和力施加机构。封装基底可以使用陶瓷层压工艺或Cerdip形成工艺由陶瓷或塑料制成。

60. 发明授权

US06215322B1 Conventionally sized temporary package for testing semiconductor dice 失效
公开(公告)号：US06215322B1
公开(公告)日：2001-04-10
申请号：US08888471
申请日：1997-07-07
申请人： Warren M. Farnworth , Alan G. Wood , David R. Hembree , Salman Akram
发明人： Warren M. Farnworth , Alan G. Wood , David R. Hembree , Salman Akram
IPC分类号： G01R3102
CPC分类号： G01R1/0466 , G01R1/0483 , G01R3/00 , G01R31/2863 , G01R31/2893 , H01L21/6835 , H01L22/20 , H01L23/13 , H01L23/49816 , H01L23/49838 , H01L24/48 , H01L24/80 , H01L24/85 , H01L2224/16145 , H01L2224/48 , H01L2224/85001 , H01L2225/06562 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/0105 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15151 , H01L2924/15174 , H01L2924/181 , H01L2924/19041 , H01L2924/30105 , H05K3/0058 , H05K3/0067 , H05K3/4007 , H05K3/423 , H05K2201/0133 , H05K2201/0347 , H05K2201/0367 , H05K2201/0394 , H05K2201/09481 , H05K2201/09563 , H05K2203/0307 , H05K2203/0723 , H01L2224/78 , H01L2224/45099 , H01L2224/05599 , H01L2924/00
摘要： A method for packaging and testing a semiconductor die is provided. The method includes forming a temporary package for the die that has a size, shape and lead configuration that is the same as a conventional plastic or ceramic semiconductor package. The temporary package can be used for burn-in testing of the die using standard equipment. The die can then be removed from the package and certified as a known good die. In an illustrative embodiment the package is formed in a SOJ configuration. The package includes a base, an interconnect and a force applying mechanism. The package base can be formed of ceramic or plastic using a ceramic lamination process or a Cerdip formation process.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式