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51. 发明申请

US20120195208A1 PROGRAMMABLE MULTIFIELD PARSER PACKET 失效
标题翻译：可编程多路复用器分组
公开(公告)号：US20120195208A1
公开(公告)日：2012-08-02
申请号：US13017963
申请日：2011-01-31
申请人： Francois Abel , Jean Calvignac , Christoph Hagleitner , Jan van Lunteren , Fabrice Verplanken
发明人： Francois Abel , Jean Calvignac , Christoph Hagleitner , Jan van Lunteren , Fabrice Verplanken
IPC分类号： H04L12/26 , H04J3/24
CPC分类号： H04L69/22
摘要： A method of operating a packet parser in a computing system includes providing a configurable packet pointer by the packet parser, the packet pointer configured to index a configurable number of atomic parsing elements, the atomic parsing elements having a configurable size, in a data stream received by the computing system for extraction, wherein the indexed atomic parsing elements are non-contiguous in the data stream; and receiving the extracted indexed atomic parsing elements from the data stream by the packet parser.
摘要翻译：一种在计算系统中操作分组解析器的方法包括：由分组解析器提供可配置的分组指针，所述分组指针被配置为在接收的数据流中索引可配置数量的原子解析元素（所述原子解析元素具有可配置大小）由所述计算系统提取，其中所述索引的原子解析元素在所述数据流中不连续; 以及由分组解析器从数据流接收提取的索引原子解析元素。

52. 发明申请

US20050232270A1 Network switch and components and method of operation 审中-公开
公开(公告)号：US20050232270A1
公开(公告)日：2005-10-20
申请号：US11152699
申请日：2005-06-14
申请人： Brian Bass , Jean Calvignac , Anthony Gallo , Marco Heddes , Sridhar Rao , Michael Siegel , Brian Youngman , Fabrice Verplanken
发明人： Brian Bass , Jean Calvignac , Anthony Gallo , Marco Heddes , Sridhar Rao , Michael Siegel , Brian Youngman , Fabrice Verplanken
IPC分类号： G06F15/16 , G06F13/40 , G06F15/177 , H04L12/56
CPC分类号： H04L49/3036 , G06F13/4022 , H04L49/15 , H04L49/205 , H04L49/3009 , H04L49/351
摘要： A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a control point and a plurality of interface processors formed on a semiconductor substrate. The control point and interface processors together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network.

53. 发明授权

US06370148B1 Data communications 失效
标题翻译：数据通信
公开(公告)号：US06370148B1
公开(公告)日：2002-04-09
申请号：US09110920
申请日：1998-07-06
申请人： Jean Calvignac , Daniel Orsatti , Fabrice Verplanken , Gilles Toubol
发明人： Jean Calvignac , Daniel Orsatti , Fabrice Verplanken , Gilles Toubol
IPC分类号： H04J314
CPC分类号： H04L49/106 , H04L49/20 , H04L49/254 , H04L49/3018 , H04L49/508
摘要： An improved arbiter is described for arbitrating requests by a plurality of first data processing units for access to a plurality of second data processing units interconnected by a switching system of a type in which at any time each first unit can only access one second unit and each second unit can only be accessed by one first unit. The arbiter comprises a scheduler mechanism for repeatedly selecting access requests with a defined minimum probability of selecting a request for each first unit-second unit combination. Rearrangement storage means records requests selected by the scheduler mechanism. A rearranger is provided for repeatedly selecting a set of requests recorded in the rearrangement storage means, so that only one request per first unit and per second unit is selected, using a priority mechanism which increases the probability of selection with the length of time a request is stored in the rearrangement storage means. Finally, means are provided for communicating the grant of the selected set of requests to the switching system and for deleting the selected set of requests from the rearrangement storage means. In one embodiment, the arbiter is used for controlling switching paths in a packet data switch.
摘要翻译：描述了一种改进的仲裁器，用于对多个第一数据处理单元的请求进行仲裁，以访问多个第二数据处理单元，该多个第二数据处理单元通过一种类型的交换系统互连，其中每个第一单元在任何时候只能访问一个第二单元，并且每个第二单元只能由一个第一单元访问。仲裁器包括一个调度机制，用于以对每个第一单位 - 第二单位组合选择一个请求的限定的最小概率重复地选择访问请求。重排存储装置记录由调度机制选择的请求。提供了一种重排器，用于重复选择记录在重排存储装置中的一组请求，使得仅使用优先级机制选择每第一单元和每秒单元的一个请求，该优先级机制随着请求的长度增加选择的概率存储在重排存储装置中。最后，提供了用于将所选择的一组请求的许可传送给交换系统并且用于从重排存储装置中删除所选择的一组请求的装置。在一个实施例中，仲裁器用于控制分组数据交换机中的交换路径。

54. 发明授权

US5668798A Multiplexed TC sublayer for ATM switch 失效
标题翻译：用于ATM交换机的多路TC子层
公开(公告)号：US5668798A
公开(公告)日：1997-09-16
申请号：US547827
申请日：1995-10-25
申请人： Gilles Toubol , Jean Calvignac , Jean-Luc Frenoy , Daniel Orsatti , Luc Torres , Fabrice Verplanken
发明人： Gilles Toubol , Jean Calvignac , Jean-Luc Frenoy , Daniel Orsatti , Luc Torres , Fabrice Verplanken
IPC分类号： H04L12/70 , H04Q11/04 , H04L12/56
CPC分类号： H04Q11/0478 , H04L2012/5615 , H04L2012/5616
摘要： A data switching device, such as an ATM or Asynchronous Transfer Mode switch, includes a switching fabric with multiple input and output leads. The device also includes at least one input adapter for receiving data cells on each of a number of input ports and at least one output adapter for delivering data cells switched through the switching fabric to a target port in a set of output ports. Error and format checks are performed on incoming cells and counts are kept of the number of good cells and invalid cells received on a particular input port. To reduce hardware costs, the counts are kept in a random access memory which is shared among the input ports. Several storage locations are allocated to each input port to maintain the necessary counts.
摘要翻译：诸如ATM或异步传输模式开关的数据交换设备包括具有多个输入和输出引线的交换结构。该设备还包括至少一个用于在多个输入端口中的每一个上接收数据单元的输入适配器和至少一个输出适配器，用于将通过交换结构交换的数据单元传送到一组输出端口中的目标端口。在进入的单元格上执行错误和格式检查，并且保留在特定输入端口上接收到的良好单元和无效单元的数量的计数。为了降低硬件成本，将计数保存在随机存取存储器中，该存储器在输入端口之间共享。将几个存储位置分配给每个输入端口以维持必要的计数。

55. 发明授权

US5666361A ATM cell forwarding and label swapping method and apparatus 失效
标题翻译： ATM信元转发和标签交换方法和装置
公开(公告)号：US5666361A
公开(公告)日：1997-09-09
申请号：US547826
申请日：1995-10-25
申请人： Ange Aznar , Jean Calvignac , Jean-Luc Frenoy , Daniel Orsatti , Dominique Rigal , Luc Torres , Fabrice Verplanken
发明人： Ange Aznar , Jean Calvignac , Jean-Luc Frenoy , Daniel Orsatti , Dominique Rigal , Luc Torres , Fabrice Verplanken
IPC分类号： H04L12/54 , H04L12/70 , H04L12/935 , H04L12/937 , H04L12/56
CPC分类号： H04L12/5601 , H04L49/255 , H04L49/3081 , H04L2012/5652 , H04L2012/5681
摘要： The techniques required to switch an ATM cell between an input adapter and an output adapter are enhanced by performing two look-up operations. The first look-up operation is performed in the input adapter which receives the cell to be switched. The first look-up operation retrieve the address of the target output port and a connection control block. The second look-up operation is performed in the target output adapter and makes use of the results of the input adapter search to retrieve the information need to complete the transfer of the cell to the target output port.
摘要翻译：通过执行两次查找操作来增强在输入适配器和输出适配器之间切换ATM信元所需的技术。在接收要切换的单元的输入适配器中执行第一查找操作。第一个查找操作检索目标输出端口的地址和连接控制块。第二个查找操作在目标输出适配器中执行，并利用输入适配器搜索的结果来检索需要完成将单元传输到目标输出端口的信息。

56. 发明授权

US5629928A Dynamic fair queuing to support best effort traffic in an ATM network 失效
标题翻译：动态公平排队，以支持ATM网络中的最佳流量
公开(公告)号：US5629928A
公开(公告)日：1997-05-13
申请号：US570840
申请日：1995-12-12
申请人： Jean Calvignac , Daniel Orsatti , Fabrice Verplanken
发明人： Jean Calvignac , Daniel Orsatti , Fabrice Verplanken
IPC分类号： H04Q3/00 , H04L12/56
CPC分类号： H04L12/5602 , H04L47/10 , H04L49/3081 , H04L2012/5619 , H04L2012/5635 , H04L2012/5679
摘要： A flow control apparatus implemented in a virtual path ATM communication system comprising a plurality of nodes interconnected by physical links which comprise virtual paths including a plurality of virtual channels. A connection between two nodes is defined as the combination of a physical link, a virtual path, and a virtual channel. Connections are shared between a reserved bandwidth service and a best effort service. ATM data cells conveyed on said best effort service are routed from node to node by analyzing their virtual connection identifier. Queues, allocated as needed from a pool of free queues, are used to store all incoming ATM data cells having the same virtual channel identifier.
摘要翻译：一种在虚拟路径ATM通信系统中实现的流控制装置，包括由包括多个虚拟信道的虚拟路径的物理链路互连的多个节点。两个节点之间的连接被定义为物理链路，虚拟路径和虚拟信道的组合。连接在保留的带宽服务和尽力而为的服务之间共享。通过分析其虚拟连接标识符，在所述尽力服务上传送的ATM数据单元从节点路由到节点。根据需要从空闲队列池分配的队列用于存储具有相同虚拟信道标识符的所有传入ATM数据单元。

57. 发明授权

US5467359A Apparatus for generating and checking the error correction codes of messages in a message switching system 失效
标题翻译：用于在消息交换系统中生成和检查消息的纠错码的装置
公开(公告)号：US5467359A
公开(公告)日：1995-11-14
申请号：US24061
申请日：1993-03-01
申请人： Pierre J. Huon , Philippe Jachimcsyk , Gerard Barucchi , Jean Calvignac , Fabrice Verplanken
发明人： Pierre J. Huon , Philippe Jachimcsyk , Gerard Barucchi , Jean Calvignac , Fabrice Verplanken
IPC分类号： G06F11/10 , G06F13/00 , H03M13/00 , H04L1/00
CPC分类号： H04L1/0057 , H04L1/0041 , H04L2001/0094
摘要： An error correction apparatus includes an error control circuit which computes for each burst of a message (for a destination unit) an error correction code as a function of an initial error correction code at the first burst of the message or of the error correction code of the previous burst and of the data bytes of the burst. The burst error correction code is sent on a medium which is separate from the data transport medium as a companion of the burst. Also, the error control circuit receives the burst error correction code from an origin unit and generates the burst error correction code to be compared with the received burst error correction code. If a mismatch is detected, the burst found in error is flagged.
摘要翻译：纠错装置包括：错误控制电路，用于根据消息的第一个突发或者纠错码的初始纠错码，对消息的每个突发（对于目的地单元）计算纠错码，作为初始纠错码的函数先前的突发和突发的数据字节。突发纠错码在与数据传输介质分离的介质上发送，作为突发的伴侣。此外，误差控制电路从原点单元接收脉冲串纠错码，并产生与接收脉冲串纠错码进行比较的脉冲串纠错码。如果检测到不匹配，则会发现错误中发现的突发状况。

58. 发明申请

US20060285551A1 STM-1 TO STM-64 SDH/SONET FRAMER WITH DATA MULTIPLEXING FROM A SERIES OF CONFIGURABLE I/O PORTS 有权
标题翻译： STM-1到STM-64 SDH / SONET框架，具有从一系列可配置I / O端口进行数据多路复用
公开(公告)号：US20060285551A1
公开(公告)日：2006-12-21
申请号：US11467848
申请日：2006-08-28
申请人： Kenneth Barker , Rolf Clauberg , Jean Calvignac , Andreas Herkersdorf , Fabrice Verplanken , David Webb
发明人： Kenneth Barker , Rolf Clauberg , Jean Calvignac , Andreas Herkersdorf , Fabrice Verplanken , David Webb
IPC分类号： H04J3/22
CPC分类号： H04J3/1611 , H04J3/0685 , H04J3/22 , H04J2203/0089
摘要： The present invention relates to a device for combining at least two data signals having an input data rate into a single data stream having an output data rate being higher than the input data rate for transmission on a shared medium or vice versa, particularly, to a single SDH/SONET framer capable of handling a large range of SDH/SONET frames from STM-i to STM-j with an aggregated total capacity corresponding to an STM-j frame where i and j are integers in the range from 1 to 64 or higher according to the STM-N definition of the SDH/SONET standards. More over, the present invention can also be extended to work with STS-1 as lowest range. STS-1 exists in SONET only not SDH and corresponds to a data rate of 51.5 Mb/s a third of the 156 Mb/s of STM-1. The device according to the present invention comprises at least two ports for receiving and/or sending said at least two data signals, a port snning unit for extracting data from the data signals received by said ports and/or synthesizing data to be transmitted via the ports, respectively, whereby said port scanning unit is configured to extract data from ports providing data streams having at least two different input data rates and/or to synthesize data to be transmitted via the ports taking data streams having at least two different data rates.
摘要翻译：本发明涉及一种用于将具有输入数据速率的至少两个数据信号组合成具有高于用于在共享介质上传输的输入数据速率的输出数据速率的单个数据流的装置，反之亦然，特别涉及一种单个SDH / SONET成帧器能够处理从STM-i到STM-j的大范围的SDH / SONET帧，具有对应于STM-j帧的聚合总容量，其中i和j是从1到64的整数或根据SDH / SONET标准的STM-N定义更高。更进一步地，本发明也可以扩展到使用STS-1作为最低范围。 STS-1仅存在于SONET中而不是SDH，对应于156Mb / s的STM-1的三分之一的51.5Mb / s的数据速率。根据本发明的装置包括用于接收和/或发送所述至少两个数据信号的至少两个端口，用于从由所述端口接收的数据信号中提取数据和/或合成要通过所述端口发送的数据的端口捕捉单元其中所述端口扫描单元被配置为从提供具有至少两个不同输入数据速率的数据流的端口提取数据和/或合成要通过端口发送的数据，该数据流具有至少两个不同数据速率的数据流。

59. 发明申请

US20050232205A1 Network switch and components and method of operation 失效
标题翻译：网络交换机及组件及操作方法
公开(公告)号：US20050232205A1
公开(公告)日：2005-10-20
申请号：US11152419
申请日：2005-06-14
申请人： Brian Bass , Jean Calvignac , Anthony Gallo , Marco Heddes , Sridhar Rao , Michael Siegel , Brian Youngman , Fabrice Verplanken
发明人： Brian Bass , Jean Calvignac , Anthony Gallo , Marco Heddes , Sridhar Rao , Michael Siegel , Brian Youngman , Fabrice Verplanken
IPC分类号： G06F15/16 , G06F13/40 , G06F15/177 , H04L12/56 , H04B7/216
CPC分类号： H04L49/3036 , G06F13/4022 , H04L49/15 , H04L49/205 , H04L49/3009 , H04L49/351
摘要： A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a control point and a plurality of interface processors formed on a semiconductor substrate. The control point and interface processors together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network.
摘要翻译：一种网络交换装置，这种装置的组件，以及操作这样的装置的方法，其中通过控制点和形成在半导体衬底上的多个接口处理器的协作来增强数据流处理和灵活性。控制点和接口处理器一起形成一个网络处理器，能够在执行指导网络中的数据流的指令的情况下与包括可选交换结构设备在内的其他元件协作。

60. 发明申请

US20050232204A1 Network switch and components and method of operation 失效
公开(公告)号：US20050232204A1
公开(公告)日：2005-10-20
申请号：US11152119
申请日：2005-06-14
申请人： Brian Bass , Jean Calvignac , Anthony Gallo , Marco Heddes , Sridhar Rao , Michael Siegel , Brian Youngman , Fabrice Verplanken
发明人： Brian Bass , Jean Calvignac , Anthony Gallo , Marco Heddes , Sridhar Rao , Michael Siegel , Brian Youngman , Fabrice Verplanken
IPC分类号： G06F15/16 , G06F13/40 , G06F15/177 , H04L12/56 , H04B7/216
CPC分类号： H04L49/3036 , G06F13/4022 , H04L49/15 , H04L49/205 , H04L49/3009 , H04L49/351
摘要： A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a control point and a plurality of interface processors formed on a semiconductor substrate. The control point and interface processors together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network.

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