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1. 发明授权

US5666361A ATM cell forwarding and label swapping method and apparatus 失效
标题翻译： ATM信元转发和标签交换方法和装置
公开(公告)号：US5666361A
公开(公告)日：1997-09-09
申请号：US547826
申请日：1995-10-25
申请人： Ange Aznar , Jean Calvignac , Jean-Luc Frenoy , Daniel Orsatti , Dominique Rigal , Luc Torres , Fabrice Verplanken
发明人： Ange Aznar , Jean Calvignac , Jean-Luc Frenoy , Daniel Orsatti , Dominique Rigal , Luc Torres , Fabrice Verplanken
IPC分类号： H04L12/54 , H04L12/70 , H04L12/935 , H04L12/937 , H04L12/56
CPC分类号： H04L12/5601 , H04L49/255 , H04L49/3081 , H04L2012/5652 , H04L2012/5681
摘要： The techniques required to switch an ATM cell between an input adapter and an output adapter are enhanced by performing two look-up operations. The first look-up operation is performed in the input adapter which receives the cell to be switched. The first look-up operation retrieve the address of the target output port and a connection control block. The second look-up operation is performed in the target output adapter and makes use of the results of the input adapter search to retrieve the information need to complete the transfer of the cell to the target output port.
摘要翻译：通过执行两次查找操作来增强在输入适配器和输出适配器之间切换ATM信元所需的技术。在接收要切换的单元的输入适配器中执行第一查找操作。第一个查找操作检索目标输出端口的地址和连接控制块。第二个查找操作在目标输出适配器中执行，并利用输入适配器搜索的结果来检索需要完成将单元传输到目标输出端口的信息。

2. 发明授权

US5768273A Method and apparatus for priority level queueing in processing ATM cell header and payload 失效
标题翻译：处理ATM信元头和有效载荷的优先级排队的方法和装置
公开(公告)号：US5768273A
公开(公告)日：1998-06-16
申请号：US547828
申请日：1995-11-01
申请人： Ange Aznar , Jean Calvignac , Daniel Orsatti , Dominique Rigal , Fabrice Verplanken
发明人： Ange Aznar , Jean Calvignac , Daniel Orsatti , Dominique Rigal , Fabrice Verplanken
IPC分类号： H04L12/931 , H04L12/935 , H04J3/22
CPC分类号： H04L49/30 , H04L49/205 , H04L49/3009
摘要： An ATM switch includes one or more adapters having input ports and/or output ports and a switching fabric for switching Asynchronous Transfer Mode (ATM) cells received at the input ports to the output ports. To maintain switch throughput, cells are categorized either as real time (high priority) or non-real time (lower priority) cells. High priority cells are processed using a first set of cell processing logic at a rate at least equal to the rate at which the cells are received on the input ports. Lower priority cells are processed using a second set of cell processing logic only when no high priority cells are being processed.
摘要翻译： ATM交换机包括具有输入端口和/或输出端口的一个或多个适配器，以及用于将在输入端口处接收的异步传输模式（ATM）单元切换到输出端口的交换结构。为了保持交换机吞吐量，小区被分类为实时（高优先级）或非实时（较低优先级）小区。使用第一组信元处理逻辑以至少等于在输入端口上接收信元的速率的速率处理高优先级信元。仅当不处理高优先级单元时，才使用第二组单元处理逻辑来处理低优先级单元。

3. 发明授权

US5684797A ATM cell multicasting method and apparatus 失效
标题翻译： ATM信元多播方法及装置
公开(公告)号：US5684797A
公开(公告)日：1997-11-04
申请号：US548030
申请日：1995-10-25
申请人： Ange Aznar , Jean Calvignac , Daniel Orsatti , Dominique Rigal , Fabrice Verplanken
发明人： Ange Aznar , Jean Calvignac , Daniel Orsatti , Dominique Rigal , Fabrice Verplanken
IPC分类号： H04L12/18 , H04L12/931 , H04L12/935 , H04L12/56
CPC分类号： H04L49/201 , H04L49/30
摘要： A multicasting apparatus and method for an Asynchronous Transfer Mode (ATM) switch is described, which uses a single target port (TP) vector attached to each outgoing ATM cell. The target port vector contains identifiers of each port to which the cell has to be transmitted. After transmission of the cell, the identifier relating to respective target port is erased from the TP vector. Hence the TP vector contains only identifiers of target port to which the cell has not yet been transmitted. When the TP vector contains no identifiers, the storage location at which the ATM cell is stored during the transmission, is freed for another cell. Unicast and multicast traffic are treated identically.
摘要翻译：描述了用于异步传输模式（ATM）交换机的多播设备和方法，其使用附接到每个输出ATM信元的单个目标端口（TP）向量。目标端口向量包含单元必须发送到的每个端口的标识符。在小区的传输之后，从TP向量中删除与各目标端口有关的标识符。因此，TP向量仅包含小区尚未被发送到的目标端口的标识符。当TP向量不包含标识符时，传输期间存储ATM信元的存储位置被释放用于另一小区。单播和多播流量处理相同。

4. 发明授权

US6003060A Method and apparatus to share resources while processing multiple priority data flows 失效
标题翻译：在处理多个优先级数据流的同时共享资源的方法和装置
公开(公告)号：US6003060A
公开(公告)日：1999-12-14
申请号：US993695
申请日：1997-12-18
申请人： Ange Aznar , Jean Calvignac , Daniel Orsatti , Dominique Rigal , Fabrice Verplanken
发明人： Ange Aznar , Jean Calvignac , Daniel Orsatti , Dominique Rigal , Fabrice Verplanken
IPC分类号： G06F9/48 , G06F9/00
CPC分类号： G06F9/4881
摘要： The invention discloses a method and an apparatus for use in high speed networks such as Asynchronous Transfer Mode (ATM) networks providing support for processing multipriority data flows at media speed, the major constraint being to share the storage and the ALU between all the tasks. The invention consists first in grouping the tasks in processes and the processes in set of processes all organized in decreasing order of their priority ; `on the fly`interruption of a lower priority process/set of processes by a higher priority process/set of processes is possible as well as reuse of the shared resources during task void states inactive in a process or between processes.In the preferred embodiment of the invention, the support of the reserved bandwidth and non reserved bandwidth ATM services data flows requires two different groups of processes, the highest priority being for the group of processes serving the reserved bandwidth service.With the principle of the invention when used in network equipment the media speed is sustained and many different network traffics can be simultaneously supported. The apparatus implementing the solution of the invention, allowing sharing of resources saves place and costa by the improved reduced number of sophisticated hardware components such as static memories and programmable logic circuits.
摘要翻译：本发明公开了一种在诸如异步传输模式（ATM）网络的高速网络中使用的方法和装置，其提供了以媒体速度处理多优先级数据流的支持，主要的约束是在所有任务之间共享存储和ALU。该发明首先是将过程中的任务分组，以及所有组织过程中的任务按优先顺序排列; 通过更高优先级的进程/进程集可以“低速优先”的进程/一组进程的中断，以及任务无效状态下的共享资源在进程中或进程之间无效的重用。在本发明的优选实施例中，保留带宽和非保留带宽ATM服务数据流的支持需要两个不同的进程组，其中最高优先级用于为预留带宽服务服务的进程组。根据本发明的原理，在网络设备中使用媒体速度得以持续，同时支持不同的网络流量。实现本发明的解决方案的设备允许资源共享通过改进的诸如静态存储器和可编程逻辑电路之类的复杂硬件组件的减少的数量来节省地方和成本。

5. 发明授权

US5668798A Multiplexed TC sublayer for ATM switch 失效
标题翻译：用于ATM交换机的多路TC子层
公开(公告)号：US5668798A
公开(公告)日：1997-09-16
申请号：US547827
申请日：1995-10-25
申请人： Gilles Toubol , Jean Calvignac , Jean-Luc Frenoy , Daniel Orsatti , Luc Torres , Fabrice Verplanken
发明人： Gilles Toubol , Jean Calvignac , Jean-Luc Frenoy , Daniel Orsatti , Luc Torres , Fabrice Verplanken
IPC分类号： H04L12/70 , H04Q11/04 , H04L12/56
CPC分类号： H04Q11/0478 , H04L2012/5615 , H04L2012/5616
摘要： A data switching device, such as an ATM or Asynchronous Transfer Mode switch, includes a switching fabric with multiple input and output leads. The device also includes at least one input adapter for receiving data cells on each of a number of input ports and at least one output adapter for delivering data cells switched through the switching fabric to a target port in a set of output ports. Error and format checks are performed on incoming cells and counts are kept of the number of good cells and invalid cells received on a particular input port. To reduce hardware costs, the counts are kept in a random access memory which is shared among the input ports. Several storage locations are allocated to each input port to maintain the necessary counts.
摘要翻译：诸如ATM或异步传输模式开关的数据交换设备包括具有多个输入和输出引线的交换结构。该设备还包括至少一个用于在多个输入端口中的每一个上接收数据单元的输入适配器和至少一个输出适配器，用于将通过交换结构交换的数据单元传送到一组输出端口中的目标端口。在进入的单元格上执行错误和格式检查，并且保留在特定输入端口上接收到的良好单元和无效单元的数量的计数。为了降低硬件成本，将计数保存在随机存取存储器中，该存储器在输入端口之间共享。将几个存储位置分配给每个输入端口以维持必要的计数。

6. 发明授权

US6144637A Data communications 失效
标题翻译：数据通信
公开(公告)号：US6144637A
公开(公告)日：2000-11-07
申请号：US991911
申请日：1997-12-16
申请人： Jean Calvignac , Fabrice Verplanken , Daniel Orsatti
发明人： Jean Calvignac , Fabrice Verplanken , Daniel Orsatti
IPC分类号： H04L12/70 , H04Q11/04 , H04J3/14
CPC分类号： H04Q11/0478 , H04L2012/568
摘要： Traffic shaping apparatus is described for packet data communications networks, such as Asynchronous Transfer Mode (ATM) networks. The apparatus includes one or more packet queues for traffic having a plurality of different desired packet transfer rates, each queue being assigned to a connection having a predetermined desired packet transfer rate. Each incoming data packet is directed to the appropriate queue. Each of a plurality of timing circuits operate at a different frequency in a series of frequencies. The frequencies are selected so that the desired packet transfer rate for a connection can be established by summing outputs from more than one of the timing circuits.
摘要翻译：描述了用于分组数据通信网络（诸如异步传输模式（ATM））网络的流量整形装置。该装置包括用于具有多个不同期望分组传输速率的业务的一个或多个分组队列，每个队列被分配给具有预定的期望分组传送速率的连接。每个传入的数据包被引导到适当的队列。多个定时电路中的每一个在一系列频率中以不同的频率工作。选择频率使得可以通过对来自多于一个定时电路的输出求和来建立连接的期望分组传送速率。

7. 发明授权

US5724348A Efficient hardware/software interface for a data switch 失效
标题翻译：高效的数据交换硬件/软件界面
公开(公告)号：US5724348A
公开(公告)日：1998-03-03
申请号：US858156
申请日：1997-05-05
申请人： Claude Basso , Jean Calvignac , Mathieu Girard , Daniel Orsatti , Michel Susini , Fabrice Verplanken
发明人： Claude Basso , Jean Calvignac , Mathieu Girard , Daniel Orsatti , Michel Susini , Fabrice Verplanken
IPC分类号： H04L12/56 , H04Q11/04
CPC分类号： H04L49/30 , H04L49/104 , H04L49/254 , H04L49/255 , H04L49/3081 , H04Q11/0478 , H04L2012/5652 , H04L49/3009
摘要： A data switch is described with a multi-port data switching element, one or more input/output adapters for receiving user data cells from outside the switch and for transmitting cells switched through the switching element to a network outside the switch, and a control element including a control processor. To reduce the complexity of the data switch, the single control processor is used to control operations of hardware modules on both the the control element on which the processor is located and on the input/output adapters. The control is provided by means of control cells which generally traverse the same data paths as user data cells and generally conform to the format of user data cells, at least within the data switch. Both the control processor and the hardware modules are capable of generating control cells and transmitting them toward a target, either the control processor or hardware modules.
摘要翻译：使用多端口数据交换元件描述数据交换机，一个或多个输入/输出适配器，用于从交换机外部接收用户数据单元，以及将通过交换单元切换的小区发送到交换机外部的网络，以及控制元件包括一个控制处理器。为了降低数据交换的复杂性，单个控制处理器用于控制处理器所在的控制元件和输入/输出适配器上的硬件模块的操作。控制通过控制单元提供，控制单元通常遍历与用户数据单元相同的数据路径，并且至少在数据交换机内通常符合用户数据单元的格式。控制处理器和硬件模块都能够产生控制单元并将其发送到目标，即控制处理器或硬件模块。

8. 发明授权

US07061860B1 Network traffic shaping 有权
标题翻译：网络流量整形
公开(公告)号：US07061860B1
公开(公告)日：2006-06-13
申请号：US09706969
申请日：2000-11-06
申请人： Jean Calvignac , Fabrice Verplanken , Daniel Orsatti
发明人： Jean Calvignac , Fabrice Verplanken , Daniel Orsatti
IPC分类号： H04J3/14
CPC分类号： H04Q11/0478 , H04L2012/568
摘要： A method for shaping network traffic in a computer network is described for packet data networks. The method includes one or more packet queues for traffic having a plurality of different desired packet transfer rates, each queue being assigned to a connection having a predetermined desired packet transfer rate. Each incoming data packet is directed to the appropriate queue. Each of a plurality of timing circuits operate at a different frequency in a series of frequencies. The frequencies are selected so that the desired packet transfer rate for a connection can be established by summing outputs from more than one of the timing circuits.
摘要翻译：针对分组数据网络描述了一种用于整形计算机网络中的网络流量的方法。该方法包括用于具有多个不同期望分组传输速率的业务的一个或多个分组队列，每个队列被分配给具有预定的期望分组传送速率的连接。每个传入的数据包被引导到适当的队列。多个定时电路中的每一个在一系列频率中以不同的频率工作。选择频率使得可以通过对来自多于一个定时电路的输出求和来建立连接的期望分组传送速率。

9. 发明授权

US5794033A Method and system for in-site and on-line reprogramming of hardware logics with remote loading in a network device 失效
标题翻译：在网络设备中进行远程加载的硬件逻辑的现场和在线重新编程的方法和系统
公开(公告)号：US5794033A
公开(公告)日：1998-08-11
申请号：US547635
申请日：1995-10-24
申请人： Jeane-Paul Aldebert , Claude Basso , Jean Calvignac , Paul Chemla , Daniel Orsatti , Fabrice Verplanken , Jean-Claude Zunino
发明人： Jeane-Paul Aldebert , Claude Basso , Jean Calvignac , Paul Chemla , Daniel Orsatti , Fabrice Verplanken , Jean-Claude Zunino
IPC分类号： G06F13/38 , H03K19/177
CPC分类号： G06F13/4256
摘要： The invention discloses a method and an apparatus for in-line and on-site updating of Field Programmable Gate Arrays with remote loaded configuration data files. Flash EEPROMs which are used because of their non-volatile memories and their high density, are storing more than one configuration data file. The memories are divided in more than one part, each part of the memory for storing one configuration data file. One part of the memory also contains a flag identifying the currently loaded configuration data file. The Flash EPROM's bits being set to one same binary value before any writing operation, including the update of the configuration data file containing the flag. The setting of the bits to said binary value always identifies a valid other configuration data file in order to insure a correct re-loading of the FPGAs in case of reception of an unexpected event leading to an initialization.
摘要翻译：本发明公开了一种用于使用远程加载的配置数据文件进行现场可编程门阵列的在线和现场更新的方法和装置。由于其非易失性存储器及其高密度使用的闪存EEPROM存储多个配置数据文件。存储器分为多个部分，存储器的每个部分用于存储一个配置数据文件。存储器的一部分还包含标识当前加载的配置数据文件的标志。闪存EPROM的位在任何写入操作之前被设置为相同的二进制值，包括更新包含该标志的配置数据文件。对所述二进制值的位的设置总是标识有效的其他配置数据文件，以便在接收到导致初始化的意外事件的情况下确保正确地重新加载FPGA。

10. 发明授权

US5557266A System for cascading data switches in a communication node 失效
标题翻译：用于在通信节点中级联数据交换机的系统
公开(公告)号：US5557266A
公开(公告)日：1996-09-17
申请号：US206363
申请日：1994-03-07
申请人： Jean Calvignac , Pierre Huon , Daniel Orsatti , Gilles Toubol , Fabrice Verplanken
发明人： Jean Calvignac , Pierre Huon , Daniel Orsatti , Gilles Toubol , Fabrice Verplanken
IPC分类号： H04L12/933 , H04L12/935 , H04L12/937 , H04L29/00 , H03K17/00
CPC分类号： H04L49/15 , H04L29/00 , H04L49/103 , H04L49/254 , H04L49/3027
摘要： A system for cascading data switches in a communication node allows for transfer of data among a plurality of adapters (30-i), expanding a moderate low cost switch 31-1 with additional hardware (31-2, 31-3, 31-4) to interconnect more adapters. The data transfers are performed by a plurality of Burst Relaying Cascaders (32-i) which connect the plurality of switches (31-i). A similar interface connect each adapter to the switch. A set of address information is used by the system to route the data from the source adapter to the target adapter, allowing navigation among the intermediate switches. Each interface contains a table where the address of every adapter of the whole system could be constructed dynamically at each communication node configuration.
摘要翻译：用于在通信节点中级联数据交换的系统允许在多个适配器（30-i）之间传输数据，用附加硬件（31-2,31-3-3,34-4）扩展适度的低成本开关31-1 ）来互连更多适配器。数据传送由连接多个开关（31-i）的多个突发中继级联（32-i）执行。类似的接口将每个适配器连接到交换机。系统使用一组地址信息将数据从源适配器路由到目标适配器，允许在中间交换机之间导航。每个接口包含一个表，其中可以在每个通信节点配置下动态构建整个系统的每个适配器的地址。

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